JPH04286349A - Semiconductor integrated circuit test device - Google Patents
Semiconductor integrated circuit test deviceInfo
- Publication number
- JPH04286349A JPH04286349A JP3051521A JP5152191A JPH04286349A JP H04286349 A JPH04286349 A JP H04286349A JP 3051521 A JP3051521 A JP 3051521A JP 5152191 A JP5152191 A JP 5152191A JP H04286349 A JPH04286349 A JP H04286349A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chamber
- semiconductor integrated
- temperature
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 47
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 238000012805 post-processing Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 40
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- 239000000523 sample Substances 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000005192 partition Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 238000001035 drying Methods 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000003463 adsorbent Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、半導体集積回路の試験
装置に関する。さらに詳しくは、本発明は、例えば液体
窒素温度までの、低温で半導体集積回路の電気特性試験
をウェハ状態で行う試験装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a testing device for semiconductor integrated circuits. More specifically, the present invention relates to a test device for testing the electrical characteristics of semiconductor integrated circuits in a wafer state at low temperatures, for example, down to the temperature of liquid nitrogen.
【0002】近年、コンピュータ等の情報処理システム
、交換機等の通信システムの高速化の要求に伴い、シス
テムを構成する半導体集積回路の高速化が望まれている
。半導体集積回路の高速化のための手段の1つとして、
半導体集積回路を液体窒素温度等の低温で動作させるこ
とが考えられるため、半導体集積回路の低温での電気特
性を試験する必要が増している。一方、1枚のウェハ上
に数十個の規模で作製される半導体集積回路の試験を効
率的に行うためには、ウェハ上の半導体集積回路の入出
力端子(パッド)に直接針(プローブ)を当てて試験す
る試験装置(プローバ)が欠かせない。In recent years, with the demand for faster speeds of information processing systems such as computers and communication systems such as switching equipment, there has been a desire for faster speeds of semiconductor integrated circuits that constitute the systems. As one of the means to speed up semiconductor integrated circuits,
Since semiconductor integrated circuits may be operated at low temperatures such as liquid nitrogen temperature, there is an increasing need to test the electrical characteristics of semiconductor integrated circuits at low temperatures. On the other hand, in order to efficiently test semiconductor integrated circuits manufactured on a scale of several dozen on a single wafer, it is necessary to use probes directly to the input/output terminals (pads) of the semiconductor integrated circuits on the wafer. A test device (prober) that performs tests by applying
【0003】このため、現在、ウェハ状態で半導体集積
回路の低温での電気特性を試験する低温プローバが用い
られているが、低温冷却時に凍結した水分等がウェハ表
面に吸着しており、プローブとパッドとの良好なコンタ
クトを妨げるため、試験前に水分を主とする吸着物質を
除去する必要がある。[0003] For this reason, low-temperature probers are currently used to test the electrical characteristics of semiconductor integrated circuits at low temperatures in the wafer state. Adsorbent substances, mainly water, must be removed before testing, as they prevent good contact with the pad.
【0004】また、試験終了後、低温に冷えたウェハを
取り出す際、ウェハ表面に霜が付着する。精巧な半導体
集積回路は水に弱く、特性が劣化するため、霜が付着し
ないようにウェハを昇温し、取り出すことが有利である
。[0004]Furthermore, when the wafer is taken out after being cooled to a low temperature after the test, frost adheres to the surface of the wafer. Since sophisticated semiconductor integrated circuits are sensitive to water and their characteristics deteriorate, it is advantageous to heat the wafer and remove it to prevent frost from forming.
【0005】[0005]
【従来の技術】従来の低温プローバにおいては、試験室
にウェハを設置した後、 100℃以下の温度で半導体
集積回路を加熱しながら試験室を排気して高真空にする
ことで、ウェハ表面の吸着水分を除去していた。ところ
が、この場合、ウェハの取替時に試験室を直接大気に曝
してしまうのと、ウェハ表面の吸着水分とウェハとの結
合力が強いために、排気、すなわち吸着水分の除去に数
時間を要す上、完全に除去しきれずにプローブとパッド
とのコンタクト不良を生じることもあった。[Prior Art] In conventional low-temperature probers, after a wafer is placed in a test chamber, the test chamber is evacuated to a high vacuum while heating the semiconductor integrated circuit at a temperature of 100°C or less, thereby evacuating the wafer surface. Adsorbed moisture was removed. However, in this case, the test chamber is directly exposed to the atmosphere when replacing the wafer, and because the bond between the adsorbed moisture on the wafer surface and the wafer is strong, it takes several hours to exhaust, that is, to remove the adsorbed moisture. Moreover, it could not be completely removed, resulting in poor contact between the probe and the pad.
【0006】霜が付着することなくウェハの昇温と取り
出しを行えるようにするために、従来の低温プローバに
おいては、ヒータを用いて加熱し、室温に達したら乾燥
ガスを導入して試験室内を乾燥ガス雰囲気としていた。
この方法でも霜の付着は防げるが、タンク中の液体窒素
をすべて蒸発させねばならず、不経済であり、かつ、昇
温自体に1時間以上を要してしまう上、やはりウェハの
取替時に試験室を直接大気に曝すため、大気中の水分が
試験室内壁およびプローブカードに吸着し、次の試料の
試験準備に時間を要することになる。In order to raise the temperature of the wafer and take it out without forming frost, conventional low-temperature probers use a heater to heat the test chamber, and once it reaches room temperature, dry gas is introduced to cool the test chamber. A dry gas atmosphere was used. Although this method can also prevent frost from forming, it is uneconomical as it requires all the liquid nitrogen in the tank to evaporate, and it takes more than an hour to raise the temperature itself. Since the test chamber is directly exposed to the atmosphere, moisture in the atmosphere is adsorbed to the walls of the test chamber and the probe card, making it time consuming to prepare the next sample for testing.
【0007】[0007]
【発明が解決しようとする課題】このように、従来の低
温プローバにおいては、ウェハ上の吸着水分の除去に時
間がかかるが、その割にはウェハ上の吸着水分の除去を
確実に行うことができないため、半導体集積回路の低温
での特性試験を確実かつ迅速に行うことができず、また
ウェハの昇温や取り出しに時間がかかり、不経済でもあ
る、という問題があった。[Problems to be Solved by the Invention] As described above, in the conventional low-temperature prober, it takes time to remove the adsorbed moisture on the wafer, but in comparison, it is difficult to reliably remove the adsorbed moisture on the wafer. As a result, it is not possible to perform low-temperature characteristic tests of semiconductor integrated circuits reliably and quickly, and it also takes time to heat up and take out the wafer, which is uneconomical.
【0008】本発明は、従って、従来不確実で時間のか
かったウェハ表面の吸着水分の除去を短時間で確実に行
うことのできる機構を備え、かつ、ウェハの昇温や取り
出しが経済的に迅速に行える低温プローバを提供するこ
とを目的とする。Therefore, the present invention is equipped with a mechanism that can reliably remove adsorbed moisture on the wafer surface in a short time, which was conventionally unreliable and time-consuming, and also enables economical heating and removal of the wafer. The purpose of the present invention is to provide a low-temperature prober that can be used quickly.
【0009】[0009]
【課題を解決するための手段】本発明によれば、上記課
題を解決するため、低温で半導体集積回路の電気特性試
験を行う試験室1と、プラズマ発生機構を備えた予備室
2とを有し、試験の前工程で、前記予備室において、プ
ラズマクリーニング処理による水分の除去を行うように
したことを特徴とする半導体集積回路の試験装置が提供
される。[Means for Solving the Problems] According to the present invention, in order to solve the above problems, there is provided a test chamber 1 for testing the electrical characteristics of semiconductor integrated circuits at low temperatures, and a preliminary chamber 2 equipped with a plasma generation mechanism. There is also provided a testing apparatus for semiconductor integrated circuits, characterized in that moisture is removed by plasma cleaning in the preliminary chamber in a pre-test process.
【0010】この装置は、さらに、乾燥ガスを導入可能
な後処理室3を備え、試験終了後に、この後処理室にお
いて、乾燥ガス雰囲気中で低温から室温に昇温するよう
になされていてもよい。[0010] This apparatus further includes a post-processing chamber 3 into which dry gas can be introduced, and after the test is completed, the temperature is raised from low temperature to room temperature in a dry gas atmosphere in this post-processing chamber. good.
【0011】図1に、本発明の装置の一例を示す。図中
、1は試験室であり、ここで半導体集積回路の特性試験
を行う。2は予備室であり、試験前にウェハ表面のプラ
ズマクリーニングを行う。3は後処理室であり、低温に
冷却したウェハを室温にまで昇温する。ウェハは予備室
2から試験室1、次いで後処理室3という順序で輸送さ
れる。FIG. 1 shows an example of the apparatus of the present invention. In the figure, reference numeral 1 indicates a test room, where characteristic tests of semiconductor integrated circuits are performed. 2 is a preliminary room where plasma cleaning of the wafer surface is performed before testing. 3 is a post-processing chamber in which the wafer, which has been cooled to a low temperature, is heated to room temperature. The wafers are transported in this order from the preliminary chamber 2 to the test chamber 1 and then to the post-processing chamber 3.
【0012】0012
【作用】図2は、予備室2の詳細図である。図中に示す
ように、予備室2は、アルゴン等の不活性ガスの導入系
と、プラズマを室内で発生させるための高周波電源4お
よび電極5と、室内を排気する排気系とを備えている。
ウェハ6を予備室2内に搬送し、室内を排気した後、不
活性ガスを導入して、高周波電源を用いて放電し、プラ
ズマを発生させる。高周波電界および、シース内の電界
でエネルギーを得たプラズマ中のイオンや電子は、ウェ
ハに衝突する。このとき、プラズマ中の中性粒子の一部
もウェハに衝突する。これにより、ウェハ表面の吸着水
分を分子の形で飛散させ、ウェハ表面を浄化する。不活
性ガスを用いるのは、ウェハ上の半導体集積回路材料と
の化学反応を防ぐためである。また、ウェハに衝突する
プラズマ中の粒子のエネルギーが大きすぎると、半導体
集積回路にまで損傷を与えるため、放電エネルギーはそ
れ以下に抑えなければならない。クリーニング後、ウェ
ハを試験室1に移送して試験を行う。[Operation] FIG. 2 is a detailed view of the preliminary chamber 2. As shown in the figure, the preliminary chamber 2 is equipped with an introduction system for inert gas such as argon, a high frequency power source 4 and an electrode 5 for generating plasma in the chamber, and an exhaust system for exhausting the interior of the chamber. . After the wafer 6 is transferred into the preliminary chamber 2 and the chamber is evacuated, an inert gas is introduced and a high frequency power source is used to generate a discharge and generate plasma. Ions and electrons in the plasma that have gained energy from the high-frequency electric field and the electric field within the sheath collide with the wafer. At this time, some of the neutral particles in the plasma also collide with the wafer. As a result, the adsorbed moisture on the wafer surface is scattered in the form of molecules, and the wafer surface is purified. The purpose of using an inert gas is to prevent a chemical reaction with the semiconductor integrated circuit material on the wafer. Furthermore, if the energy of the particles in the plasma that collide with the wafer is too large, it will even damage the semiconductor integrated circuit, so the discharge energy must be kept below that level. After cleaning, the wafer is transferred to test chamber 1 and tested.
【0013】図3は、後処理室3の詳細図である。図中
に示すように、後処理室は、窒素等の乾燥ガスの導入系
と、室内を排気する排気系とを有する。試験終了後、低
温に冷却されたウェハ6は後処理室3に移送され、ヒー
タ7により室温まで昇温される。この際、室内に乾燥ガ
スを導入してウェハ表面に霜の付着するのを防ぐ。FIG. 3 is a detailed view of the post-processing chamber 3. As shown in the figure, the post-processing chamber has an introduction system for drying gas such as nitrogen, and an exhaust system for exhausting the inside of the room. After the test is completed, the wafer 6 cooled to a low temperature is transferred to the post-processing chamber 3 and heated to room temperature by the heater 7. At this time, drying gas is introduced into the room to prevent frost from adhering to the wafer surface.
【0014】図4は、試験室1の詳細図である。試験室
1はプローブカード8の交換時以外には外気に曝されな
いため、常時室内を高真空に保つことができる。FIG. 4 is a detailed view of the test chamber 1. Since the test chamber 1 is not exposed to the outside air except when replacing the probe card 8, it is possible to maintain a high vacuum inside the chamber at all times.
【0015】[0015]
【実施例】以下に本発明の実施例を挙げ、さらに説明す
る。第1隔壁9を開いてウェハを予備室2に移送した後
、室内を、例えば、1×10−5Torrにまで排気す
る。
不活性なアルゴンガスを導入し、内部圧力を、例えば2
×10−3Torrとした上で、例えば 100Wの電
力で放電させ、プラズマを作る。プラズマクリーニング
は、例えば3分間行う。この後、予備室2の内壁および
ウェハ6表面上の吸着水分は除去されているので、真空
度は、初めの1×10−5Torrよりも良くなり、3
〜5×10−6Torrに達する。達しない時には、ガ
スを導入するプロセスから再び繰り返す。図5は、クリ
ーニング処理の流れ図である。[Examples] Examples of the present invention will be given below to further explain the invention. After opening the first partition wall 9 and transferring the wafer to the preliminary chamber 2, the chamber is evacuated to, for example, 1×10 −5 Torr. Inert argon gas is introduced and the internal pressure is increased to, e.g.
×10 −3 Torr and discharge with a power of, for example, 100 W to create plasma. Plasma cleaning is performed for 3 minutes, for example. After this, since the adsorbed moisture on the inner wall of the preliminary chamber 2 and the surface of the wafer 6 has been removed, the degree of vacuum is better than the initial 1 x 10-5 Torr, and is 3.
~5×10 −6 Torr is reached. If this is not achieved, the process of introducing gas is repeated again. FIG. 5 is a flowchart of the cleaning process.
【0016】クリーニング処理後、第2隔壁10を開い
て、ウェハ6を3×10−6Torr程度の圧力の試験
室1に移送する。試験終了後、第3隔壁11を開いて1
×10−3Torrの圧力の後処理室3に輸送する。窒
素乾燥ガスを導入し、ヒータ7でウェハ6を加熱しなが
ら室温に戻す。室温に達したら、第4隔壁12を開いて
ウェハを取り出し、ウェハ格納箱に格納する。After the cleaning process, the second partition wall 10 is opened and the wafer 6 is transferred to the test chamber 1 having a pressure of about 3×10 −6 Torr. After the test, open the third partition 11 and
The sample is transported to the post-treatment chamber 3 at a pressure of ×10 −3 Torr. Nitrogen drying gas is introduced, and the wafer 6 is heated by the heater 7 while being returned to room temperature. When the temperature reaches room temperature, the fourth partition wall 12 is opened, the wafer is taken out, and the wafer is stored in a wafer storage box.
【0017】[0017]
【発明の効果】以上に説明したように、本発明によれば
、半導体集積回路の低温特性試験前に必要な吸着水分の
除去およびウェハの昇温や取り出しを確実に、しかも短
時間で行うことができ、半導体集積回路の低温特性試験
の信頼性とスループットの向上に寄与するところが大で
ある。[Effects of the Invention] As explained above, according to the present invention, it is possible to reliably remove adsorbed moisture, raise the temperature of the wafer, and take it out in a short time, which is necessary before testing the low-temperature characteristics of semiconductor integrated circuits. This greatly contributes to improving the reliability and throughput of low-temperature characteristic testing of semiconductor integrated circuits.
【図1】本発明の装置の実施例を示す模式図である。FIG. 1 is a schematic diagram showing an embodiment of the device of the present invention.
【図2】図1の装置の予備室の詳細図である。2 is a detailed view of the preliminary chamber of the device of FIG. 1; FIG.
【図3】図1の装置の後処理室の詳細図である。3 is a detailed view of the post-treatment chamber of the apparatus of FIG. 1; FIG.
【図4】図1の装置の試験室の詳細図である。4 is a detailed view of the test chamber of the apparatus of FIG. 1; FIG.
【図5】実施例におけるクリーニング処理の流れ図であ
る。FIG. 5 is a flowchart of cleaning processing in the example.
1…試験室 2…予備室 3…後処理室 4…高周波電源 5…電極 6…ウェハ 7…ヒータ 8…プローブカード 9…第1隔壁 10…第2隔壁 11…第3隔壁 12…第4隔壁 1...Examination room 2...Preliminary room 3...Post-processing room 4...High frequency power supply 5...Electrode 6...Wafer 7...Heater 8...Probe card 9...First bulkhead 10...Second partition wall 11...Third bulkhead 12...Fourth bulkhead
Claims (2)
を行う試験室(1) と、プラズマ発生機構を備えた予
備室(2) とを有し、試験の前工程で、前記予備室に
おいて、プラズマクリーニング処理による水分の除去を
行うようにしたことを特徴とする半導体集積回路の試験
装置。Claim 1: A test chamber (1) for testing the electrical characteristics of semiconductor integrated circuits at low temperatures; and a preliminary chamber (2) equipped with a plasma generation mechanism; A testing device for semiconductor integrated circuits, characterized in that moisture is removed by plasma cleaning treatment.
を行う試験室(1) と、プラズマ発生機構を備えた予
備室(2) と、乾燥ガスを導入可能な後処理室(3)
とを有し、試験の前工程で、前記予備室において、プ
ラズマクリーニング処理による水分の除去を行い、かつ
、試験終了後に、前記後処理室において、乾燥ガス雰囲
気中で低温から室温に昇温するようにしたことを特徴と
する半導体集積回路の試験装置。[Claim 2] A test chamber (1) for testing the electrical characteristics of semiconductor integrated circuits at low temperatures, a preliminary chamber (2) equipped with a plasma generation mechanism, and a post-processing chamber (3) into which dry gas can be introduced.
In the pre-test step, moisture is removed by plasma cleaning in the preliminary chamber, and after the test, the temperature is raised from low temperature to room temperature in a dry gas atmosphere in the post-treatment chamber. A test device for semiconductor integrated circuits, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3051521A JPH04286349A (en) | 1991-03-15 | 1991-03-15 | Semiconductor integrated circuit test device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3051521A JPH04286349A (en) | 1991-03-15 | 1991-03-15 | Semiconductor integrated circuit test device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04286349A true JPH04286349A (en) | 1992-10-12 |
Family
ID=12889319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3051521A Withdrawn JPH04286349A (en) | 1991-03-15 | 1991-03-15 | Semiconductor integrated circuit test device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04286349A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7901958B2 (en) | 2003-10-31 | 2011-03-08 | Renesas Electronics Corporation | Fabrication method of semiconductor integrated circuit device |
-
1991
- 1991-03-15 JP JP3051521A patent/JPH04286349A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7901958B2 (en) | 2003-10-31 | 2011-03-08 | Renesas Electronics Corporation | Fabrication method of semiconductor integrated circuit device |
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