JPH04286235A - Timing synchronization circuit - Google Patents

Abstract

PURPOSE:To provide a timing phase locked loop circuit to operate normally under a multi-path condition such as TDMA digital mobile communication. CONSTITUTION:The phase of a regenerative clock is controlled by a first phase difference detection circuit to detect phase difference between an input signal and a regenerative clock, a second phase difference detection circuit to detect the phase difference between the input signal and the regenerative clock and different from the first phase difference detection circuit in its detecting characteristic, the output of the first phase difference detection circuit, and the output of the second phase difference detection circuit.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing synchronization circuit for a demodulator for digital mobile communication.

0003

2. Description of the Related Art In recent years, digital mobile communications are on the verge of being put into practical use. Generally, a demodulator for digital communication is equipped with a timing synchronization circuit that detects the transmission timing of a digital signal and generates a reproduced clock.

On the other hand, transmission paths used in mobile communications include multipaths, and received signals are greatly distorted.

[0005] Particularly when attempting to perform digital transmission, the influence of this multipath is significant, and some measure against this is essential.

In particular, when the arrival time difference between the multipath delayed wave and the direct wave is large compared to the reciprocal of the transmission speed, this effect is extremely large, and as it is, demodulation and timing detection cannot be performed as usual. This was difficult in terms of circuits.

[0007] In particular, timing detection is extremely degraded even when the arrival time difference between the multipath delayed wave and the direct wave is less than one symbol. Examples are shown in FIGS. 28 and 29.

FIG. 28 is a diagram showing a conventional timing phase error detection system, and FIG. 29 is a diagram showing the detection error distribution in the same detection system using the multipath arrival time difference as a parameter.

[0009] Compared to the case (2) where there is no multipath arrival time difference, a large detection error occurs more frequently when the multipath arrival time difference is 0.01, and it becomes almost impossible to detect when the multipath arrival time difference is 0.4 symbols. . Conventionally, in such a multipath state, timing could not be detected with high accuracy.

Furthermore, when the multipath arrival time difference exceeds one symbol, cycle slips occur frequently and it is extremely difficult to maintain synchronization.

[0011] Incidentally, if the wireless transmission distance is 10 km at 50 to 100 kbps, multipaths reaching several symbols will be generated.

Furthermore, the above-mentioned cycle scoop is TDM.
If the A method or the like is applied to the wireless section, this becomes an extremely serious problem. That is, when a cycle skip occurs, frame synchronization cannot be maintained, resulting in complete communication failure.

As described above, conventionally, it has been difficult to establish timing synchronization when the multipath arrival time difference is large.

[0014]

[Problems to be Solved by the Invention] That is, the present invention has been made in view of the lack of a timing phase synchronization system that is resistant to multipaths for digital mobile communications, particularly for digital mobile communications using the TDMA system. ,TDMA
An object of the present invention is to provide a timing phase synchronization circuit that operates normally under multipath conditions for digital mobile communications.

[Configuration of the invention]

[0016]

[Means for Solving the Problems] In order to achieve the above-mentioned object, a first invention provides a phase error for detecting a phase difference X between a clock component of an input signal and a reproduced clock using a known pattern included in an input signal. a first phase error detection circuit whose detection characteristic is continuously or discontinuously zero at one point while the absolute value of X>constant a; It is equipped with a loop filter that inputs the output of the phase error detection circuit, and a recovered clock generation/control device that adjusts the phase of the clock timing using the output of this loop filter. Timing characterized by being expressed as 180+τ/T*180=a using the expected arrival time difference τ between the expected multipath direct wave and delayed wave of the received signal and the reciprocal T of the transmission rate (symbol rate). A second invention of the synchronous circuit includes: a first phase error detection circuit that detects a phase error between an input signal and a reproduced clock; and a first phase error detection circuit that detects a phase error between the input signal and the reproduced clock. The circuit includes a second phase error detection circuit having different detection characteristics, and a recovered clock generator that controls the phase of a recovered clock from the output of the first phase error detection circuit and the output of the second phase error detection circuit.・A timing synchronization circuit comprising a control circuit,
A third invention is based on the second invention, wherein the second phase error detection circuit detects a phase error for each symbol of the input signal if the second phase error detection circuit can detect the phase error. A fourth invention is a timing synchronization circuit characterized in that the first phase error detection circuit detects a phase error only when an input signal has a known pattern; The phase error detection circuit No. 1 is a timing synchronization circuit characterized in that it has a matched filter that matches at least a known pattern included in the input signal, and detects a time position at which the maximum output value of this matched filter is obtained, A fifth invention is based on the second invention, wherein the phase error detection characteristic of the second phase error detection circuit is:
The first phase error detection circuit realizes a linear or approximately linear characteristic at least in the vicinity of zero phase error, and the error detection characteristic of the first phase error detection circuit is such that at least the phase error is ±
This timing synchronization circuit is characterized in that it is zero within δ and the absolute value of δ<180.

[0017]

[Operation] Two different phase error detection circuits detect the phase error between the input signal and the reproduced clock, and the phase of the reproduced clock is controlled based on these detection results. Therefore, good clock timing can be obtained even in the presence of multipath.

[0018]

[Embodiment] An embodiment of the present invention will be explained with reference to the drawings.

As explained in the previous section using FIG. 29, when using the phase error detection characteristics shown in FIG. 30, the phase error cannot be detected accurately if a delayed wave is superimposed on the input signal. However, this will be explained again in comparison with the present invention. For example, assume that the current input signal is a signal S1 having a phase error X1 and a signal S2 having a phase error X2 delayed by Δt compared to the signal S1 superimposed thereon. At that time, the output of the phase error detection device is expressed as f(X), based on the assumption that the detection device is linear (in reality, it is nonlinear, but in this case, it is a degraded linear approximation due to multipath). (It can be easily inferred that the conventional example in particular is considerably degraded compared to what can be grasped by the following.) The output is expressed as f(X1)+f(X2).

By the way, when f(X) exhibits the characteristics shown in FIG. 30, there is no problem so long as Δt is sufficiently smaller than T/2, but when it approaches T/2, the phase error becomes undetectable. become. In particular, when D/U=0 dB and Δt=T/2, f(X1)+f(X2)=0. Therefore, in the conventional example, phase error detection is impossible. On the other hand, when the phase error detection characteristics of the present invention as shown in FIG. 1 are used, there is no such concern even if Δt exceeds T/2. In particular, by inputting the output of the phase error detection device to a loop filter and smoothing it, the reproduced clock generation/control device can be controlled with an average optimum value.

Furthermore, for the maximum predicted value Δt of the multipath arrival time difference, 180+180*Δt/T=a,
A place where the value of 0 is consecutive between the absolute value of X≧a is
If X is set only in the vicinity of 0, malfunctions due to the influence of multipath can be avoided. Here, the maximum predicted value of the multipath arrival time difference is approximately 2/C with respect to the zone radius 2 of the service zone of the mobile communication system. (C is the speed of light) Therefore, design may be performed by setting Δt to a*■/C. In the characteristics shown in FIG. 1, there is only one value that takes zero within the range of ±1080°, so it can support multipath up to ±2.5 symbols.

By the way, even in a place where there is no multipath, if only one having the phase error detection characteristics as shown in FIG. 1 is used, the synchronization characteristics will deteriorate on the contrary if there is no multipath. In other words, in the characteristics of FIG. 1, there are fewer stable points at which the phases settle when synchronized than in the characteristics of FIG.
The average time required for phase pull-in becomes extremely long. (Multipaths are rare when communicating near the base station.)
Therefore, by combining the outputs of two phase error detection circuits with different characteristics as shown in Figures 4 and 5, which have the advantages and disadvantages as described above, we can bring out the advantages of both and create a multipath transmission line. It is possible to construct a timing synchronization circuit that operates well even in

For example, during the initial fixed period of time when the phase is pulled in, synchronization is attempted using only the characteristics shown in FIG. 4, and then,
By switching to the characteristics shown in Figure 5 while preventing the synchronization position from shifting, both of the above drawbacks can be compensated for.
Good characteristics can be obtained. The system shown in FIG. 3 realizes this.

Furthermore, as a method for realizing the first phase error detection characteristic, the circuit shown in FIG. 6 can be used. The circuit in Figure 6 shows a case realized using digital signal processing, etc., which samples the input signal with a clock faster than the baud rate, inputs the sample value to a correlator, and detects the maximum value. be. A known pattern is inserted into the input signal, and when the known pattern is input to the correlator, the maximum value is generated at the optimal timing. The time difference between this and the zero-crossing point of the signal obtained by frequency-dividing the reproduced clock is taken as the output of the first phase error detection circuit. Here, since this is calculated based on the sampled values, the phase error detection characteristics are as shown in FIG. In this case, f(X)=0 near X=0, and X=0
High precision control in the vicinity is not possible. If only this method is used, even if there is no multipath distortion, +
Since finer control than δ and −δ′ cannot be performed, phase errors cannot be removed.

Therefore, by combining the circuit shown in FIG. 6 with a second phase error detection circuit having phase error detection characteristics as shown in FIG. A timing synchronization circuit that can eliminate clock phase errors can be provided. In this case, the first
By linearly adding the and second phase error detection circuit outputs,
For example, as shown in FIG. 8, linear characteristics can be obtained near X=0.

In addition to the embodiments described above, there are many other embodiments. FIG. 9 shows an embodiment of the first phase error detection circuit. Divide the frequency of the regenerated clock so that at least 1 in one slot
A clock having a slot period including two training sequences at equal intervals is obtained, and the time difference between the rising or falling edge of the clock and the correlator output peak is used as the output of the first phase error detection circuit.

FIG. 2 shows an example of a configuration in which a loop is formed using such a phase error detection circuit. FIG. 9a shows an embodiment of the first phase error detection circuit for obtaining the phase comparison characteristic shown in FIG. The input signal to the circuit of FIG. 9a periodically includes a training sequence as shown in FIG. 9b, and the correlator is configured to have maximum correlation with the training sequence. The characteristics shown in FIG. 5 can be obtained by counting the time difference between the peak value of the output of the correlator and the rise or fall of the frame clock obtained by dividing the reproduced clock. Note that in this method, each time a training sequence is input,
One phase error signal is output.

FIG. 10 shows an example of the first phase error detection circuit, and FIG. 11 shows its detection characteristics. This circuit consists of two types of correlators and a power calculator for input signals, a subtracter that takes the difference between them, and a delay device. The input signal is divided into two paths: one that enters the correlator after a delay, and one that enters the correlator directly.The difference between the output powers of both correlators is resampled according to the frame clock obtained by dividing the reproduced baud rate clock. It can be obtained by A in FIG. 11 increases as the delay amount of the delay device increases. Therefore, the desired A can be achieved until an appropriate amount of delay is inserted. Further, the phase error detection characteristics of this circuit can be adjusted by inserting an appropriate filter into the input terminal of FIG. The characteristics shown in FIG. 11 are obtained when a filter in which the overall characteristics of the transmitting and receiving filters are Gaussian is used at the input end.

FIG. 12 shows another embodiment of the present invention. The reproduced clock generation/control device divides the original clock appropriately to obtain a sampling clock, a baud rate clock, and a frame clock. The input signal sampled according to the sampling clock is input to the first and second phase error detection circuits.

The outputs of the first and second phase error detection circuits are each independently input to a loop filter, and are combined after being applied with different loop gains, thereby controlling the frequency division ratio for obtaining the sampling clock. do.

Here, the order of the loop filter and the constant multiplier synthesizer for loop gain multiplication may be different.

Further, desired characteristics can be obtained until the loop gains α1 and α2 are appropriately changed. Here the first
A random walk filter as shown in FIG. 13 may be used as the loop filter. This output sets the frequency division ratio 1/a of the frequency divider for sampling clock generation to 1/(a
+1) or 1/(a-1), all phases of the baud rate clock and frame clock, including the sampling clock phase, can be optimized and controlled.

FIG. 14 shows an embodiment for use in a 3-slot multiplex TDMA system. Here, the case where the first slot of the three slots is received is described. As shown in the figure, phase control using the loop filter output can prevent the duty ratios of various clocks from changing during the transmission and reception period until it is performed only during the idle period when neither transmission nor reception is occurring. .

FIG. 15 shows another embodiment of the present invention in which a receiver including the timing synchronization circuit of the present invention also includes an equalizer.

The input signal is input to the first phase error detection circuit, and a timing phase shift is detected from the training sequence inserted into the reception slot. Until this timing phase shift is detected, the input signal is temporarily
It is input to a buffer such as FO. From the detected timing phase shift, find the optimal timing of the reception slot,
It is used to resample the FIFO output and input it to the equalizer. If the timings are not synchronized, the equalizer is required to be a fractional space equalizer, but when this embodiment is used, a symbol space equalizer can be applied. Incidentally, compared to symbol space equalizers, fractional space equalizers have disadvantages such as ■ large number of taps, large circuit size, and ■ poor equalization tracking characteristics, so it is difficult to achieve low power consumption and miniaturization. This is essential for mobile communication receivers that require extremely fast equalization tracking characteristics.

FIG. 16 shows another embodiment of the present invention. In this example, a VCO (VCX
O) is used.

FIG. 17 shows another embodiment.

In the figure, the input to the first phase error detection circuit may be a signal after detection or a signal before detection. When using delayed detection for detection, the first
The conjugate complex number of the differentially decoded training sequence during transmission is used as the tap coefficient of the correlator of the phase error detection circuit. Furthermore, when directly inputting the input signal to the first phase error detection circuit, the conjugate complex number of the training sequence during transmission is used as the tap coefficient.

FIG. 18 shows another embodiment of the present invention. That is, in this embodiment, SW1 and SW2 are controlled so that the frame clock, baud rate clock, etc. are kicked off at the time of initial synchronization of the timing phases, and thereafter the timing synchronization maintenance operation is performed via the loop filter.

FIG. 19 shows an embodiment of the second phase error detection circuit of the present invention. After sampling the input signal, a square error calculation is performed, and after passing through a narrow band filter, it is resampled using a baud rate clock to obtain a phase error.

Here, when the sampling clock is eight times the baud rate, a digital filter as shown in FIG. 20 can be used. Furthermore, in the case of the filter in Fig. 20, 2
Since the two outputs are orthogonal, a circuit like the one shown in FIG. 21 can output a linear phase error.

In each of the above embodiments, it is meaningful to set the sampling clock to an integral multiple of the baud rate clock from the viewpoint of simplifying the signal processing procedure.

FIG. 22 shows a diagram for explaining another embodiment.

Assume a case after frame synchronization has already been achieved. At this time, since the insertion position of the training sequence, which is a known pattern, is already known, the first phase error detection circuit only needs to input this training sequence and the signals before and after it. In particular, for mobile communication terminals where it is essential to reduce power consumption, it is important to stop circuits when unnecessary to reduce power consumption. This will result in a significant reduction in power consumption. The window shown in FIG. 22 is for the occasional input, and only time t1 is input for each slot. Using the training sequence length t and the multipath arrival time difference predicted maximum value Δt, t1 is
Since is approximately t+2Δt, it is sufficient that it is approximately expressed.

FIG. 23 shows another embodiment of the present invention. The figure assumes that the received signal before detection is input. The received signal before detection includes a frequency offset, and if it is large, the correlator can detect the peak power. Therefore, a frequency offset of ±nΔf, n = 1, 2, 3, etc. is applied. It is also possible to provide a plurality of circuit units that are inputted to the correlator after the correlation, and to detect the maximum value of the outputs of all the units. Here, Δf is set so that Δf<1/NT. Here, N is the number of correlator taps, 1/T
is the transmission speed (baud rate).

FIG. 24 shows another embodiment. In this embodiment, the first
This aims to reduce power consumption by stopping the operation of the phase error detection circuit.

In order to check whether there is a multipath with a large amount of delay, the error rate of the delay detection result is measured here. In other words, it takes advantage of the fact that delayed detection does not show a good error rate where there are multipaths with large delays, and conversely, it uses the presence or absence of error rates to check for the presence or absence of multipaths with large delays. It is.

[0048] In the case where there is no multipath with a large amount of delay,
As mentioned above, normal operation can be performed even without the second phase error detection circuit, and the effectiveness of this embodiment can be understood.

By the way, the error rate of differential detection can be easily measured by using a training sequence which is a known signal. Furthermore, in combination with this embodiment, turning the equalizer ON/OFF according to the differential detection output error rate (presence or absence of multipaths including large delays) is extremely effective for reducing power consumption.

[0050] In the various embodiments described above, delay detection has been taken as an example, but all of these may also be frequency detection. The optimum detection method should be selected according to the modulation method.

As an example of a modulation method to which the present invention can be applied.

[0052] MPSK, DPSK, OQPSK, π/4
Shift QPSK, π/4 shift DQPSK, FSK, C
PM, GMSK, TFM, CCPSK, QAM, DQA
Examples include M, TCM, etc.

FIG. 25 shows a correlator used in the present invention. In this diagram, sampling clock = baud rate clock *
Case 4 is shown. Taps are provided once per symbol.

FIG. 26 shows an example of making the present invention more effective. That is, in this embodiment, the performance can be significantly improved until the signal after being subjected to AGC is input. This makes it possible to perform more accurate control while minimizing the influence of input power fluctuations due to fizzing and the like.

FIG. 27 shows another embodiment of the present invention. This is similar to the embodiment shown in FIG. 15, but FIFO,
RAM is used for the memory of the correlator, and correlation miscalculation is avoided by MA
This shows an example of a configuration for actual implementation, such as using a C circuit.

As another embodiment, when it seems that the reliability of the outputs of the first and second phase error detection circuits is not sufficient,
It is possible to further improve the reliability of the entire system until the output of that circuit is stopped.

[0057]

[Effects of the Invention] According to the timing synchronization circuit of the present invention, the phase error between the input signal and the reproduced clock is detected by two different phase error detection circuits, and the phase of the reproduced clock is controlled based on these detection results. Good clock timing can be obtained even in the presence of multipath.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the characteristics of a first phase comparator.

FIG. 2 is a diagram showing a configuration when a loop is formed using a phase comparison detection circuit.

[Figure 3] Attempt to establish synchronization using only the characteristics shown in Figure 4 for an initial fixed period of time when the phase is pulled in, and then switch to the characteristics shown in Figure 5 while ensuring that the synchronization position does not shift to achieve a good result. FIG. 3 is a diagram showing a configuration in which characteristics are obtained.

FIG. 4 is a diagram showing characteristics of a second timing phase error detection circuit.

FIG. 5 is a diagram showing characteristics of a first timing phase error detection circuit.

FIG. 6 is a diagram showing the configuration of a first timing phase error detection circuit for obtaining the detection characteristics shown in FIG. 7;

FIG. 7 is a diagram showing characteristics of a first timing phase error detection circuit.

FIG. 8 is a diagram showing that linear characteristics can be obtained in the vicinity of X=0 by linearly adding the outputs of the first and second phase error detection circuits.

9(a) is a diagram showing an example of a first phase error detection circuit for obtaining the phase comparison characteristic shown in FIG. 5, and FIG. 9(b) is a diagram showing a periodic FIG. 2 is a diagram showing an input signal including a training sequence.

FIG. 10 is a diagram showing the configuration of a first timing phase error detection circuit for obtaining the detection characteristics shown in FIG. 11;

FIG. 11 is a diagram showing characteristics of a first timing phase error detection circuit.

FIG. 12 is a diagram showing the configuration of another embodiment of the present invention.

FIG. 13 is a diagram showing the configuration of a random walk filter as a loop filter used in an embodiment of the present invention.

FIG. 14 is another embodiment of the present invention, and is a diagram showing a case where it is used in a 3-slot multiplex TDMA system.

FIG. 15 is a diagram illustrating another embodiment of the present invention in which a receiver including a timing synchronization circuit also includes an equalizer.

FIG. 16 is another embodiment of the present invention, and is a diagram showing a case where a VCO (VCXO) is used in the reproduced clock generation/control circuit.

FIG. 17 is a diagram showing another embodiment of the present invention.

FIG. 18 is a diagram illustrating another embodiment of the present invention, in which kick-off of a frame clock, baud rate clock, etc. is performed at the time of initial synchronization of timing phases, and thereafter a timing synchronization maintenance operation is performed via a loop filter. It is a diagram.

FIG. 19 is a diagram showing the configuration of a second phase error detection circuit.

FIG. 20 is a diagram showing the configuration of a digital filter used in an embodiment of the present invention.

FIG. 21 is a diagram showing a configuration for outputting a linear phase error.

FIG. 22 is a diagram showing a training sequence and a first phase error detection circuit input window in another embodiment of the present invention.

FIG. 23 is another embodiment of the present invention, and is a diagram showing a configuration assuming that a previously received signal is input.

FIG. 24 is a diagram showing an embodiment in which the operation of the first phase error detection circuit is stopped in a place where there is no multipath with a large amount of delay, thereby reducing power consumption.

FIG. 25 is a diagram showing the configuration of a correlator used in an embodiment of the present invention.

FIG. 26 is a diagram showing an example in which the embodiment of the present invention is made more effective.

FIG. 27 is a diagram showing another embodiment of the present invention.

FIG. 28 is a diagram showing a conventional timing phase error detection system.

FIG. 29 is a diagram showing the detection error distribution of the timing phase error detection system shown in FIG. 28 using the multipath arrival time difference as a parameter.

FIG. 30 is a diagram showing characteristics of a conventional phase comparator.

Claims (5)

[Claims] 1. A phase error detection circuit that detects a phase difference X between a clock component of an input signal and a reproduced clock using a known pattern included in an input signal, the detection characteristic being such that the absolute value of X > a constant a. a first phase error detection circuit that continuously or discontinuously becomes zero at one point; a loop filter that inputs the output of the first phase error detection circuit;
It is equipped with a reproduced clock generation/control device that adjusts the phase of the clock timing using the output of the loop filter, and the value of the constant a is set to the expected multipath direct wave of the input received signal subjected to multipath distortion. Using the arrival time difference τ of delayed waves and the reciprocal T of the transmission rate (symbol rate), 18
A timing synchronization circuit characterized in that 0+τ/T*180=a. 2. A first phase error detection circuit that detects a phase error between an input signal and a recovered clock; and a first phase error detection circuit that detects a phase error between the input signal and the recovered clock have detection characteristics. a different second phase error detection circuit;
A timing synchronization circuit comprising: a reproduced clock generation/control circuit that controls the phase of a reproduced clock from the output of the first phase error detection circuit and the output of the second phase error detection circuit. 3. The second phase error detection circuit
If the phase error can be detected by the first phase error detection circuit, the first phase error detection circuit detects the phase error for each symbol of the input signal, and the first phase error detection circuit detects the phase error only when the input signal has a known pattern. 3. The timing synchronization circuit according to claim 2. 4. The first phase error detection circuit includes at least a matched filter that matches a known pattern included in the input signal, and detects a time position at which the maximum output value of the matched filter is obtained. Claim 1
The timing synchronization circuit described. 5. The phase error detection characteristic of the second phase error detection circuit is such that a linear or approximately linear characteristic is realized at least in the vicinity of zero phase error, and the phase error detection characteristic of the second phase error detection circuit is such that a linear or approximately linear characteristic is realized at least in the vicinity of zero phase error, and The error detection characteristic is that the phase error is zero at least within ±δ, and the absolute value of δ < 1
3. The timing synchronization circuit according to claim 2, wherein the timing synchronization circuit is 80.