JPH04284083A - Smoothing processing circuit - Google Patents

Abstract

PURPOSE:To execute a smoothing processing without color slurring with circuit configuration reducing circuit scale. CONSTITUTION:Among outputs obtd. by parallelly/serially converting pattern data Y read out of an image memory 1, coloring data FG and BG, display attribute control data DA, pattern data SY for the smoothing processing and display attribute control data SD, the pattern data subjected to the display attribute control of the Y and DA is used as a switching signal, R, G, B and RI signals are decoded while switching the converted outputs FG and BG at a switching circuit 15, while using the data after executing the display attribute control of the converted outputs SY and SD, it is judged whether the smoothing processing is executed to a current display image or not by a smoothing judgement circuit 18, a current display line is recognized from the output of a line judgement circuit 17, it is judged whether smoothing is executed or not at half picture elements in the first half or the latter half of the current display line and when executing the smoothing processing afterwards, the half picture elements in the first half or the latter half are added to the above-mentioned R, G, B and RI signals as color data.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a smoothing processing circuit that displays a smooth image by interpolating pattern data stored in an image memory, and in particular, it also performs appropriate coloring with a simple circuit configuration. The present invention relates to a smoothing processing circuit.

0002

[Prior Art] In a teletext receiving system that displays character pattern data such as letters and figures on a display screen,
A code signal corresponding to character pattern data stored in a character generator or the like is received, and the character pattern data is read out using this code signal and written into the image memory. After the character pattern data is written, the character pattern data is read out from the image memory and displayed.

However, in recent years, as the image quality of television receivers such as EDTV has become higher, there has been an increasing demand for the above-mentioned system to display smooth characters. Therefore, smoothing processing has been performed to display a smooth image by interpolating the pattern data stored in the image memory.

An example of a display device that has undergone conventional smoothing processing will be described below with reference to the drawings. FIG. 9 is a block diagram of a smoothing processing circuit in an image display device that performs conventional smoothing processing, FIGS. 11 and 12
13 is a timing chart of each part of the smoothing processing circuit, and FIG. 13 is a diagram showing the smoothing processing results.

In FIG. 9, 101 is an image memory;
02 to 105 are latch circuits that latch the output of the image memory 101. 106 to 109 are pattern data (
This is a parallel/serial conversion circuit that converts 8-bit parallel data of Y), foreground color signal (FG), background color signal (BG), and attribute (DA) into serial data for each dot. Since smoothing determination is performed using pattern data, first, the pattern data and attributes read ahead of the foreground color signal and background color signal from the image memory are transferred to the latch circuits 102 and 1 using YLG and DALG.
05 (read timing is shown in FIG. 11), parallel/serial conversion is performed by parallel/serial conversion circuits 106 and 109, and display attribute control such as flashing and concealment is performed by display attribute control circuit 110. The pattern data after this display attribute control is then input to the smoothing determination circuit 111.

The image display device in this example is a double-density non-interlaced one, and the same data is displayed on every two lines. Therefore, it is determined by the line determination circuit 112 whether the currently displayed line is the upper or lower line of the two lines. The determination signal INDEX output from the line determination circuit 112 is input to the smoothing determination circuit 111 together with the pattern data after the display attribute control.

The smoothing determination circuit 111 (the detailed configuration is the same as, for example, the block diagram of FIG. 2 described later) includes line memories 20 to 24 and latch circuits 25 to 42 into which pattern data after display attribute control is input.
(Figure 2), extracts the smoothing discrimination data, inputs this data to the smoothing algorithm circuit 43 (Figure 2), and performs smoothing processing considering that the same data is displayed every two lines for the current display pixel. Determine whether or not to perform the process, and if so, decide whether to perform it in the first half of the pixel of the upper line or the second half of the line, or whether to perform it with the first half of the pixel or the second half of the lower line. Further, the current display line is recognized from the output of the line determination circuit 112, and it is determined whether to perform smoothing on the first half of the pixels or the second half of the current display line. As the output of the smoothing algorithm circuit 43 (FIG. 2), when smoothing is performed on the first half of the pixels, 1 is output to the LSM, and when smoothing is performed on the latter half of the pixels, 1 is output to the RSM.

Next, the pattern data (output of the circuit 110) before smoothing processing is passed through the latch circuit 113 that matches the timing with the smoothing pixel, the smoothing judgment circuit, the outputs RSM, LSM of the circuit 111, and the like. RSML and LSML that control the timing of adding smoothing pixels are input to the smoothing pixel addition processing circuit 114. circuit 1
The actual circuit of No. 14 is shown in FIG. 10, and its timing chart is shown in FIG. Finally, pattern data Y' (circuit 1
14 (output of OR gate 118), the foreground color (
(output of circuit 107), background color (output of circuit 108)
By switching the switching circuit 115, the
As shown in Figure 3, R' and G that have been smoothed
', B', and RI' can be obtained. FIG. 13 shows an example of smoothing processing results for diagonal lines.

[0009]

[Problem to be Solved by the Invention] However, in the above configuration, smoothing processing is performed by adding smoothing pixels to pattern data, and the foreground color and background color are switched using the pattern data as a switching signal. . Therefore, as shown in Figure 14, when smoothing processing is performed by adding smoothing pixels at the boundaries of mini-blocks, which are the smallest coloring units, half pixels are added in a color different from that of the unit pixel (original pattern data) (Figure 14). 14 (indicated as red), the above-mentioned half-pixel may be displayed, which has the problem of being visually very difficult to see.

[0010] Furthermore, in order to perform smoothing discrimination with high accuracy, a large amount of discrimination data is currently required around the display pixel, but in order to extract a large amount of discrimination data, the circuit configuration is also large in scale. The problem was that it became too large.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a smoothing processing circuit that can perform smoothing processing without color shift with a circuit configuration having a reduced circuit scale.

0012

[Means for Solving the Problems] In order to solve the above-mentioned problems, the smoothing processing circuit of the present invention is provided in an image display device configured to display a received teletext image in a double-density non-interlaced manner. An image memory that stores pattern data constituting matrices in row and column directions, and pattern data, coloring data, display attribute control data, pattern data for smoothing processing, and display attribute control data read from this image memory are stored in parallel. / Decoding the pattern data, coloring data, and display attribute control data obtained from the outputs of the first to sixth parallel/serial conversion circuits and the outputs of the first to fourth parallel/serial conversion circuits to perform R, G , B, RI, pattern data obtained from the fifth and sixth parallel/serial conversion circuit outputs, and display attribute control data obtained from the first and fourth parallel/serial conversion circuit outputs. A first line memory group delays data obtained by decoding pattern data for smoothing processing and display attribute control data read in advance compared to the data so that the data is in phase with the current display pixel in a gate circuit described later; The latch circuit group and this image display device are double-density non-interlaced, and the same data is displayed on every two lines, so it is necessary to determine whether the currently displayed line is the upper or lower line of the two lines. Considering that the same data is displayed every two lines for the current display pixel using data obtained from the outputs of the line determination circuit, the first line memory group, and the first latch circuit group. Determine whether or not to perform smoothing processing, and if so, perform smoothing processing on the first half of the upper line, the latter half of the pixels, or the lower half of the lower line. a smoothing determination circuit that determines whether to perform smoothing on the first half of the pixels or the second half of the current display line by recognizing the currently displayed line from the output of the line determination circuit; , R, G, B obtained from the above decoding circuit
, the third, second, and fourth latch circuits each latch the currently displayed pixel and the two pixels to the left and right of the current display pixel in the RI signal, and the output of the smoothing determination circuit provides a determination result that the first half of the pixel is to be used. When it is determined that smoothing is to be performed in the latter half of the pixels, the data of the second latch circuit is selected as color data, and smoothing is performed. The present invention is configured to include a gate circuit that selects the data of the third latch circuit as color data when a determination result indicating that it is not to be performed is obtained, so that smoothing processing without color shift can be performed.

[0013] Furthermore, the smoothing processing circuit of the present invention includes:
The first line memory group in an image display device that displays the same data every two lines as described above is configured with two line memory groups, and the smoothing judgment circuit can perform the same smoothing judgment with half the number of judgment data. It is configured as follows.

Furthermore, in the smoothing processing circuit of the present invention, the line determination circuit in the circuit configuration described above is configured with a field determination circuit for determining odd fields and even fields, and the received teletext image is displayed by single-density interlacing. Even in an image display device configured as follows,
The structure is such that smoothing processing without color shift can be performed.

[0015]

[Operation] With the above-described structure, the present invention does not add smoothing pixels to pattern data after smoothing determination, but R, G, B, RI decoded block coloring data. Smoothing processing is performed directly on the data of the smoothing pixel, and the colored data of the smoothing pixel is extracted from the unit pixel (original pattern data) to which the smoothing pixel is added using a shift register consisting of second and third latch circuits. This allows smoothing processing to be performed without deviation.

Furthermore, by utilizing the data format in which the same data is displayed on every two lines when the display method is double-density non-interlaced, the first line memory group is configured as a two-line memory group. , instead of extracting data for each line as described above as discrimination data for smoothing discrimination, data for every two lines is extracted, and smoothing discrimination can be performed with the same accuracy using half the number of discrimination data as in the above configuration. The configuration can be simplified.

Furthermore, in the case of a single-density interlaced display system, the same data is displayed shifted by one line in the odd and even fields, and when viewed in frame units, the data is displayed in two lines.
Since the same data will be displayed line by line, by using the above line judgment circuit as a field judgment circuit to recognize the field of the currently displayed line, it is possible to It is possible to perform smoothing processing without color shift even in the case of a single-density interlaced display system by determining whether it is a line or a line below.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a smoothing processing circuit according to an embodiment of the present invention, FIGS. 2 and 3 are block diagrams explaining main parts of the smoothing processing circuit, and FIGS. 4 and 5 are timing diagrams of each part of the smoothing processing circuit. chart,
FIG. 6 is a diagram showing the smoothing processing results.

In FIG. 1, reference numeral 1 denotes an image memory in which pattern data forming a matrix in the row and column directions is stored by unit pixels, and 2 to 7 are latch circuits for latching the output of the image memory 1. The latch timing is shown in FIG. 8 to 13 are pattern data (Y) output from the latch circuits 2 to 7, foreground color signal (FG), background color signal (BG), attribute (DA), pattern data for smoothing processing (SY), and attribute (
This is a parallel/serial conversion circuit that converts 8-bit parallel data (SD) into serial data for each dot.

First, block coloring data (Y, FG, B
A circuit block that decodes G, DA) into R, G, B, and RI signals will be described. In FIG. 1, a 1-bit Y signal and a 3-bit DA signal obtained from the outputs of the parallel/serial conversion circuits 8 and 11 are inputted to a display attribute control circuit 14, and this circuit 14 controls display attributes such as flashing and concealing. Take control. Then, using the pattern data after display attribute control as a switching signal, the switching circuit 15 switches the 4-bit FG and BG signals obtained from the outputs of the parallel/serial conversion circuits 9 and 10, and
, B, and RI signals.

Next, a smoothing judgment circuit block that processes in parallel with the block colored data decoding processing circuit block will be explained. Since smoothing judgment is performed using pattern data, pattern data (SY) and attribute (S) are used as data for smoothing judgment.
D) is read out. The read timing is shown in FIG. In addition, SY and SD are adjusted so that their phases match in the circuit that adds smoothing pixels to the R, G, B, and RI signals of the smoothing pixel addition processing circuit 19, including the phase delay in the smoothing determination circuit 18, which will be described later. Y,F
Read ahead compared to G, BG, and DA. After reading, it is latched by the latch circuits 6 and 7, and the parallel/serial conversion circuits 12 and 1
The 1-bit SY signal and the 3-bit SD signal, which have been parallel/serial converted in step 3, are input to a display attribute control circuit 16, and this circuit 16 performs display attribute control such as flashing and concealment. The pattern data obtained from this is applied to a smoothing judgment circuit together with a judgment signal INDEX which judges whether the current display line obtained from the line judgment circuit 17 is the upper line or the lower line of the two lines on which the same data is displayed. Enter 18.

FIG. 2 is a block diagram showing details of the smoothing determination circuit 18. In FIG. 2, the smoothing determination circuit 18 stores input pattern data from line memories 20 to 20.
24 and latch circuits 25 to 42, the currently displayed pixel and its surrounding pattern data are extracted as data for smoothing determination, and these data are input to the smoothing algorithm circuit 43 to perform smoothing processing on the currently displayed pixel. If so, the same data is displayed every two lines, so it can be done with the first half of the line, the second half of the line, or the first half of the line below. The current display line is recognized from the output of the line determination circuit 17, and it is determined whether to perform smoothing with the first half of the pixels or with the second half of the current display line. Determination is made by gates 44, 45, 47, 48 and OR gates 46, 49. As the output of this smoothing algorithm circuit 43, when smoothing is performed on the first half pixels, 1 is output to LSM, and when smoothing is performed on the latter half pixels, 1 is output to RSM.

Next, the outputs R, G, B of the switching circuit 15
, RI signal, output RSM of smoothing determination circuit 18,
The LSM and the RSML and LSML that control the timing of adding smoothing pixels are input to the smoothing pixel addition processing circuit 19. An actual circuit of the circuit 19 is shown in FIG. 3, and a timing chart thereof is shown in FIG.

In FIG. 5, C(n), C(n-1),
C(n+1) indicates the color data of the currently displayed pixel, the pixel to the left of the pixel, and the pixel to the right of the current display pixel, and in FIG.
It is extracted from the outputs of 52 and 50. Then, when the output of the smoothing determination circuit 18 yields a determination result (RSM=1) that the first half of the pixels are to be used, C(n+1)
(color data of the pixel to the right of the currently displayed pixel) is selected as color data by the AND gate 53, and when a determination result (LSM=1) is obtained that the process is performed using the latter half pixel, C
(n-1) (color data of the pixel to the left of the currently displayed pixel) is selected as color data by the AND gate 54, and the result of determination that smoothing is not performed (RSM=LSM=
0) is obtained, the AND gate 57 selects C(n) (color data of the currently displayed pixel) as the color data. Thereafter, the three outputs of the AND gates 53, 54, and 57 are passed through the OR gate 55 and then latched by the latch circuit 56, so that R', G' is smoothed without any color shift, as shown in FIG. , B', RI' signals are obtained. FIG. 6 shows an example of smoothing processing results for diagonal lines.

FIG. 7 shows a block diagram of a smoothing determination circuit in a smoothing processing circuit according to another embodiment of the present invention. In FIG. 7, 60 and 61 are line memories for two lines, and 62 to 70 are latch circuits. The pattern data of the currently displayed line can be extracted from the output of the line memory 60, thereby the pattern data two lines above it can be extracted from the output of the line memory 61, and the pattern data two lines below can be extracted from the input of the line memory 60. . Then, the pattern data of the currently displayed pixel is taken out from the output of the latch circuit 66, the pattern data of the pixels to the right and left thereof are taken out from the latch circuits 65 and 67, and similarly, the pattern data of the pixels on the right and left of the pixel are taken out from the output of the latch circuit 63, and similarly, the pattern data of the currently displayed pixel is two lines below the output of the latch circuit 63. The pattern data of the pixel on the right and left of the pixel is extracted from the latch circuits 62 and 64, and the pattern data of the pixel two lines above the currently displayed pixel is extracted from the output of the latch circuit 69. The pattern data of the pixels on the right and left are extracted from 70.

Next, these pattern data are input to the smoothing algorithm circuit 71 as judgment data for smoothing processing. Then, the circuit 71 determines whether or not to perform smoothing processing on the currently displayed pixels, and if so, since the same data is displayed every two lines, it may be performed on the first half of the pixels of the line above, or the second half. The current display line is recognized from the output of the line determination circuit 17, and the current display line is determined based on the output of the line determination circuit 17. AND gates 72, 73, 75, 76 and O
Judgment is made by R gates 74 and 77. As the output of this smoothing algorithm circuit 71, when smoothing is performed on the first half pixels, 1 is output to LSM, and when smoothing is performed on the latter half pixels, 1 is output to RSM. Using the RSM and LSM results obtained from this,
By performing the same subsequent processing as in FIG. 1, smooth smoothing processing with the same precision can be achieved with half the line memory of the conventional method.

FIG. 8 shows a block diagram of a smoothing processing circuit according to still another embodiment of the present invention. As for the circuit configuration, the line determination circuit 17 in FIG. 1 is replaced with a field determination circuit 80. Single density applied to this example,
In an image display device with interlaced display, data is displayed by skipping one line in one field. One image, called one frame, is created using odd and even fields. In the images of the odd and even fields, the same data is displayed shifted by one line from each other. Therefore, as a data format, the same data is not displayed in units of two lines as shown in Figure 1, but the same data is displayed in units of two screens, and the display line on each screen is shifted by one line. Viewed in frame units, the same data is displayed on two lines each, and by performing field determination in the field determination circuit 80, the upper or lower line of the two lines displaying the same data in one frame is determined. This makes it possible to perform smoothing processing without color shift even on single-density, interlaced image display devices.

[0028]

As described above, according to the present invention, instead of adding smoothing pixels to pattern data after smoothing discrimination as in the conventional method, R, G , B, and RI, it is possible to perform smoothing processing without color shift.

Furthermore, in an image display device in which the same data is displayed every two lines, by configuring the first line memory group as a two-line memory group, the smoothing judgment circuit can perform smoothing equivalent to half the number of judgment data. This enables determination and simplifies the configuration.

Furthermore, by configuring the line determination circuit with a field determination circuit that determines odd fields and even fields, even in an image display device configured to display a teletext received image by single-density interlacing, the color This enables smoothing processing without deviation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a smoothing processing circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a smoothing determination circuit in the smoothing processing circuit of FIG. 1;

FIG. 3 is a block diagram of a smoothing pixel addition processing circuit in the smoothing processing circuit of FIG. 1;

FIG. 4 is a diagram showing the timing of reading and latching the image memory output of FIG. 1;

FIG. 5 is a diagram showing the timing of the operation of the smoothing pixel addition processing circuit of FIG. 3;

FIG. 6 is a diagram illustrating the results of the smoothing process shown in FIG. 1;

7 is a block diagram showing another example of the smoothing determination circuit of FIG. 1. FIG.

FIG. 8 is a block diagram of a smoothing processing circuit according to another embodiment of the present invention.

FIG. 9 is a block diagram of a conventional smoothing processing circuit.

10 is a block diagram of a smoothing pixel addition processing circuit in the smoothing processing circuit of FIG. 9; FIG.

FIG. 11 is a diagram showing the timing of reading and latching the image memory output of FIG. 9;

12 is a diagram showing the timing of the operation of the smoothing pixel addition processing circuit of FIG. 10. FIG.

13 is a diagram illustrating the smoothing processing result of FIG. 9. FIG.

FIG. 14 is a diagram illustrating problems with the results of smoothing processing in a conventional example.

[Explanation of symbols]

1 Image memory 2-7 Latch circuit 8-13 Parallel/serial conversion circuit 14, 16
Display attribute control circuit 15
Switching circuit 17 Line judgment circuit 18 Smoothing judgment circuit 19
Smoothing pixel addition processing circuit 20
~24 Line memory 25-42 Latch circuit 43 Smoothing algorithm circuit 50-52, 56 Latch circuit 60, 61 Line memory 62-70
latch circuit

Claims (3)

[Claims] 1. A smoothing processing circuit in an image display device configured to display a received teletext image in a double-density non-interlaced manner, wherein pattern data forming a matrix in the row direction and column direction by unit pixels is The stored image memory, pattern data read from this image memory, coloring data, display attribute control data, pattern data for smoothing processing,
First to sixth parallel/serial conversion circuits that convert display attribute control data into parallel/serial, and pattern data, coloring data, and display attribute control data obtained from the outputs of the first to fourth parallel/serial conversion circuits. A decoding circuit that obtains R, G, B, and RI as decode, and pattern data obtained from the outputs of the fifth and sixth parallel/serial conversion circuits, and from the outputs of the first and fourth parallel/serial conversion circuits. , pattern data for smoothing processing read in advance compared to the display attribute control data, and a first line memory that delays data obtained by decoding the display attribute control data so that it is in phase with the current display pixel in a gate circuit described later. and the first latch circuit group, for determining whether the currently displayed line is the upper or lower line of the two lines when the same data is displayed two lines at a time in double-density non-interlace. Considering that the same data is displayed every two lines for the current display pixel using data obtained from the outputs of the line determination circuit, the first line memory group, and the first latch circuit group. Determine whether or not to perform smoothing processing, and if so, perform smoothing processing on the first half of the upper line, the latter half of the pixels, or the lower half of the lower line. a smoothing determination circuit that determines whether to perform smoothing on the first half of the pixels or the second half of the current display line by recognizing the currently displayed line from the output of the line determination circuit; , R, G, B obtained from the above decoding circuit,
Based on the output of the third, second, and fourth latch circuits that respectively latch the currently displayed pixel and the two pixels to the left and right of the current display pixel in the RI signal, and the smoothing determination circuit, a determination result that the first half of the pixel is to be used is obtained. When the smoothing is performed, the data of the fourth latch circuit is selected as the color data, and when the determination result that the smoothing is to be performed in the latter half of the pixels is obtained, the data of the second latch circuit is selected as the color data, and smoothing is performed. and a gate circuit that selects the data of the third latch circuit as color data when a determination result indicating that there is no color data is obtained. 2. Smoothing according to claim 1, characterized in that the first line memory group is composed of two line memory groups, and the smoothing judgment circuit is capable of making an equivalent smoothing judgment with half the number of judgment data. processing circuit. 3. The line determination circuit comprises a field determination circuit that determines odd fields and even fields,
2. The smoothing processing circuit according to claim 1, wherein the smoothing processing circuit is capable of smoothing a received teletext image displayed by single-density interlacing.