JPH04283833A - Instruction register - Google Patents

Abstract

PURPOSE:To increase instruction codes which can be specified by providing fields for the same instruction code at different positions according to the field length of a field required for address specification. CONSTITUTION:An instruction is fetched from a memory 27 to an instruction register 28. Then the contents of a register indicated by a source register number field 23 are set in a latch 30 and the value of an immediate value field 25 when the value of an instruction field 21 is not a specific value or the contents of a source register number field 24 when the field is the specific value are set in a latch 31. Then the value of the instruction code field 21 when the value of the instruction code field 21 is not the specific value or the value of an instruction code field 26 when so is decoded by a decoding circuit 37, an arithmetic circuit 32 performs arithmetic, and the result is stored in a latch 33. In this case, the value of the instruction field 26 and the value of the instruction code field 21 are equal, so only one decoding circuit 37 is required. Lastly, the contents of the latch 33 are written in a register indicated by a destination register number field 22.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fixed-length instruction format instruction register. 2. Description of the Related Art With the recent demand for faster computer systems, computers having fixed-length instruction format instruction registers are becoming more common, making it easier to simplify and speed up decoding circuits.

[0002] Therefore, it is necessary to increase the number of instruction codes without increasing the decoding hardware.

0003

2. Description of the Related Art An example of a conventional fixed-length instruction format instruction register is shown in FIG. Here, the instruction length is 32 bits, and the addressing method is 2.
Register + 1 immediate value (number directly specified in the instruction),
It is assumed that there are two types of 3 registers.

In FIG. 4, 1 is a 6-bit field that stores an instruction code indicating the content of the operation, 2 is a 6-bit field that stores a destination register number that indicates the register number where the operation result is stored, and 3, 4. is a 6-bit field that stores the source register number that indicates the operation input register number, 5 is the 13-bit field that stores the immediate value that indicates the operation input value, and 6 is the field that specifies the register or immediate value (value is 0). Immediate value when ,
When the value is 1, it is a register), and 7 is an unused field when the addressing method is 3 registers.

In this example, since the instruction code length is 6 bits, 2 to the 6th power=64 instruction codes can be specified. Next, an application example using the instruction register is shown in FIG. In this example, one instruction involves fetching, decoding,
It is executed in four stages: execution and write. In FIG. 5, 8 is an instruction register that holds instructions fetched from memory 9. In FIG. A register file 10 holds registers.

Numerals 11 and 12 are latches for inputting the arithmetic circuit. Further, 13 is an arithmetic circuit, 14 is a latch that holds the arithmetic result, 15 is a decode circuit that decodes the instruction code of the instruction register 8, and 16 is a multiplexer. Instruction processing is performed in the following sequence. First, an instruction is fetched from the memory 9 into the instruction register 8.

Next, the contents of the register indicated by field 3 in the instruction register 8 are set in the latch 11. At the same time, if field 6 indicates an immediate value (value is 0), the immediate value of field 5 is set, and if it indicates a register (immediate value 1), the contents of field 4 are set in latch 12 via multiplexer 16.

Next, the instruction code in field 1 in the instruction register 8 is decoded by the decoding circuit 15, arithmetic operations are performed, and the results are stored in the latch 14. Finally, latch 1
4 is written to the register indicated by field 2 of instruction register 8.

[0009]

[Problem to be Solved by the Invention] However, in such a conventional instruction register, if the field length required for address specification is short, an unused field occurs, which increases the number of instruction codes that can be specified. The problem was that it could not be done. The present invention has been made in view of such conventional problems, and an object of the present invention is to provide an instruction buffer that can increase the number of instruction codes that can be specified.

0010

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. As shown in FIG.
Fields 22 to 25 required for addressing
Field 2 of the same instruction code according to the field length of
6 are provided at different positions.

[0011]

[Operation] In the present invention, fields of the same instruction code are provided in different positions depending on the field length of the field required for address specification, and unused fields are reduced, so that the decoding hardware can be reduced without increasing the decoding hardware.
The field length of the instruction code can be increased, and the number of instruction codes that can be specified can be increased.

0012

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings. 2 and 3 show one embodiment of the invention. In this embodiment, as in the conventional example, the instruction length is 32 bits, and there are two addressing methods: 2 registers + 1 immediate value (a numerical value directly specified in the instruction) and 3 registers. .

In FIG. 2, reference numeral 21 is a 7-bit instruction code field for storing an instruction code indicating the operation content. If the instruction code is a specific value (here, all 1), it indicates that 3 registers are used for address specification, and if it is not a specific value, 2 registers + 1 are used for address specification.
Indicates that it takes an immediate value.

In the former case, the operation details are indicated in the instruction code field 26, and the value at this time is the same as the instruction code in the latter. 22 is a 6-bit destination register number field that stores a destination register number indicating the register number in which the operation result is stored. Reference numerals 23 and 24 are 6-bit source register number fields that store source register numbers indicating register numbers for operation input.

Reference numeral 25 is a 13-bit immediate value field for storing an immediate value indicating a value for operation input. 26 is a 7-bit instruction code field that stores an instruction code indicating the operation content. When the value of the instruction code field 21 is a specific value (all 1), it indicates that three registers are used for address specification, and the operation contents at this time are specified in the instruction code field 26.

In this embodiment, since the instruction code length is 7 bits, 2 to the 7th power - 1=127 instruction codes can be specified. Next, an application example using the instruction register is shown in FIG. In this example, it is assumed that one instruction is executed in four stages: fetch, decode, execute, and write, similar to the conventional example.

In FIG. 3, 27 is a memory in which an instruction string is stored, and 28 is the instruction register that holds instructions fetched from the memory 27. 29 is a register file that holds registers, 30 and 31 are arithmetic circuits 32
32 is an arithmetic circuit that operates on the register contents from the latches 30 and 31; 33 is a latch that holds the operation result; 34 is the immediate value of the immediate value field 25 or the source register number field 23; This is a multiplexer that selects the contents of .

35 is a determination circuit that determines whether the contents of the instruction code field 21 of the instruction register 28 are all 1;
6 a multiplexer 37 for selecting the contents of the instruction code field 21 or the contents of the instruction code field 26;
is a decoding circuit that decodes the selected instruction code. Next, instruction processing will be explained.

First, an instruction is fetched from memory 27 into instruction register 28 . Next, the contents of the register indicated by the source register number field 23 in the instruction register 28 are set in the latch 30. At the same time, if the value of the instruction code field 21 is not a specific value (all 1s here), the immediate value of the immediate value field 25 in the instruction is set to the latch 31, and if it is a specific value, the contents of the source register number field 24 are set to the latch 31. do.

Next, if the value of the instruction code field 21 in the instruction register 28 is not a specific value, the value of the instruction code field 21 is decoded by the decoding circuit 37, and if it is a specific value, the value of the instruction code field 26 is decoded by the decoding circuit 37. Then, the arithmetic circuit 32 performs the arithmetic operation, and the result is stored in the latch 33. In this case, since the value of the former instruction code field 26 and the value of the latter instruction code field 21 are the same value, only one decoding circuit 37 is required.

Finally, the contents of the latch 33 are transferred to the destination register number field 22 of the instruction register 28.
Write to the register indicated by . In this way, the number of instruction codes that can be specified can be increased without increasing the decoding hardware.

[0022]

As described above, according to the present invention, unused fields can be reduced and the instruction code length can be increased, so the number of instruction codes that can be specified can be increased.

[Brief explanation of the drawing]

[Fig. 1] Diagram explaining the principle of the present invention

[Fig. 2] A diagram showing an embodiment of the present invention.

[Figure 3] Diagram showing an example of application of the instruction register

[Figure 4] Diagram showing a conventional example

[Figure 5] Diagram showing an example of application of a conventional instruction register

[Explanation of symbols]

21: Instruction code field 22: Destination register number field 23
, 24: Source register number field 25: Immediate value field 26: Instruction code field 27: Memory 28: Instruction register 29: Register file 30, 31, 33: Latch 32: Arithmetic circuit 34, 36: Multiplexer 35: Judgment circuit 37: Decode circuit

Claims (1)

[Claims] Claim 1: In an instruction register (28) having multiple addressing methods and having a fixed length instruction format, a field (26) of the same instruction code is assigned according to the field length of the fields (22 to 25) required for address specification. An instruction register characterized by being provided at different positions.