JPH04283811A - Timer circuit - Google Patents

Abstract

PURPOSE:To offer the timer circuit which performs time control over many systems simultaneously with a relatively simple circuit scale as to a timer circuit for time control by a CPU which performs control by a stored program system. CONSTITUTION:The timer circuit controls plural timers which can be accessed from the CPU 50 and is equipped with a storage means 10 for storing the counted values of the timers, a timer processing means 12 which updates the respective counted values of the timers stored in the storage means 10 at specific periods and informs said CPU 50 of the number of a timer which finishes counting, and a selecting means 16 which connects the bus of the CPU 50 and the bus of the timer processing means 12 to the storage means 10 alternately.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer circuit for time management in a CPU.

0002

2. Description of the Related Art A CPU usually accomplishes certain processing using a so-called stored program method, in which processing programs stored in a storage device are sequentially read out and executed according to a program counter. In this case, there often arises a need for time management in which processing is executed after a predetermined period of time. As a time management method, firstly, there is a method of making a loop which requires a predetermined processing time repeat a predetermined number of times by utilizing the fact that the processing time of a CPU instruction is constant.

[0003] This method has the advantage that no special hardware is required for timer processing, but it is not practical when the software processing becomes complex and when it is necessary to manage the time of a large number of series at the same time. Not the point. Therefore, it is common to connect an external timer LSI and leave time management to this LSI.

0004

[Problem to be Solved by the Invention] However, in this method, there is usually a limit to the number of timers that one timer LSI can process. A problem arises in that a large number of timer LSIs are required, and the scale of the hardware as a whole becomes enormous.

[0005] Accordingly, an object of the present invention is to provide a timer circuit that can simultaneously manage the time of a large number of series with a relatively simple circuit scale.

[0006]

[Means for Solving the Problems] FIG. 1 is a block diagram showing the basic configuration of the present invention. In the figure, the timer circuit of the present invention is a timer circuit that manages a plurality of timers accessible from a CPU 50, and includes a storage means 10 that is accessible from the CPU 50 and stores count values of the plurality of timers; a timer processing means 1 for updating each of the count values of the plurality of timers stored in the storage means 10 at a predetermined cycle, and for notifying the CPU 50 of the number of any timer that has finished counting;
2.

Preferably, this timer circuit further includes selection means 16 for alternately connecting the bus of the CPU 50 and the bus of the timer processing means 12 to the storage means 10.

[0008]

[Operation] The CPU 50 can access the storage means 10. Therefore, the CPU 50 uses the storage means 1
Processing such as setting timer constants within 0 can be performed,
The timer processing means 12 performs writing and reading of count values, and also performs timer subtraction, termination determination, and C
Processing such as notification to PU can be performed, and L for timer
Almost the same processing as when the SI is externally attached is realized. Furthermore, since the capacity of the storage means 10 can be arbitrarily designed depending on the required number of timers, a timer circuit having a large number of timers can be realized with a relatively simple circuit.

[0009] Furthermore, the CPU 50 and the timer processing means 16
selection means 1 for alternately connecting the
6, contention between the CPU 50 and the timer processing means 16 for the storage means 10 is avoided.

0010

Embodiment FIG. 2 is a circuit diagram of a timer circuit according to an embodiment of the present invention. Selector 160 is a switching signal (input S)
The address bus, data bus, output enable signal *OE, write enable signal *WE, and chip select signal *CS are switched alternately between the CPU 500 and the timer circuit side according to the Connect to 100.

Clock oscillator 148 generates the basic clock for the operation of this timer circuit. address counter 1
20 sequentially generates timer addresses to be processed by this timer circuit based on this basic clock and supplies them to selector 160. The timing generation circuit 122 is based on the basic clock from the clock oscillator 148.
Switching signal for switching selector 160, storage element 1
chip select signal *CS to make use of 00, output enable signal *OE to control reading from the storage element 100, write enable signal *WE to control writing to the storage element 100, and buffer 126.
, 128 control signals, etc. are output at predetermined timing. The buffer 128 is a buffer for reading the count value of the timer specified by the address counter 120 from the storage element 100. The latch 130 holds the count value read from the storage element 100 under the control of a control signal (not shown) from the timing generator 122 until the next write timing. Subtraction circuit 134
decrements the count value held in the latch 130 by 1 and outputs the result. The buffer 126 is a subtraction circuit 134
This is a buffer for writing the output of 2 to the storage element 100.

The “0” comparison circuit 136 is a subtraction circuit 136
When the output of 140 is "0", the output indicating the end of the timer's count is enabled, and the output is connected to AND gate 140.
The signal is input to the interrupt processing circuit 146 through the gate and serves as a clock input to the flip-flop 142. Flip-flop 142 latches the output of address counter 120 by clock input. The value latched at this time corresponds to the timer number of the timer that has finished counting. The interrupt processing circuit 146 receives the count end signal from the “0” comparison circuit 136 and outputs the signal to the CPU 5.
At the same time as outputting the interrupt signal INT to 00,
In order to prevent other timers from finishing counting and rewriting the flip-flop 142 before the CPU 500 completes accepting the interrupt, a signal is output that closes the AND gate 140 until the CPU 500 accepts the interrupt.

When the CPU 500 receives an interrupt, it is programmed to execute an instruction to input data from a predetermined input port address, and by executing this instruction, the output of the address decoder 144 becomes valid.
The timer number is output from the flip-flop 142 to the data bus of the CPU 500 and taken into the CPU 500. When the count value of the timer is "1" and the output of the subtraction circuit 134 is "0", or when the timer value is "0" meaning that the timer is not used, the output of the OR gate 138 is valid. Therefore, the gate 124 is closed and the count value is not updated.

[0014] Therefore, when the count value of the timer is "0", the value is not updated, and when it is greater than "2", it is subtracted every time the processing cycle comes, and the value changes from "1" to "0". When an interrupt is generated, the CPU accepts the interrupt and continues to be "1" until it is rewritten to 0 by an instruction from the CPU. FIG. 3 is a timing chart for explaining the outline of the operation of the circuit shown in FIG. Column (a) shows the state of the selector 160, column (b) shows the state of data written to the memory element 100 from the buffer 126, and column (c) shows the state of data read from the memory element 100 via the buffer 128. The column (d) shows the state of the output of the address counter 120.

As shown in FIG. 3, data is read from the memory element 100 in the latter half of the period (column (a)) in which the selector 160 selects the timer circuit side (column (c)).
column), while the CPU side is selected, the count value subtraction and judgment processing are performed, and then in the first half of the period when the timer circuit side is selected (column (b)), the memory element 100 is
The updated value is written to the same address (column (d)).

Furthermore, by making one cycle of the operation of the selector 160 coincide with the time of one processing cycle of the CPU, and by allocating the period assigned to the timer circuit to a period in which the CPU does not access the outside, access from the CPU to the memory element is reduced. can be performed in exactly the same way as accessing other storage elements (not shown). In this way, since the hardware directly subtracts and judges the value written by the CPU 500 to the storage element 100, the timer can be managed at high speed, completely independent of software. C
The PU 500 only needs to use software to access the timeout buffer 142 after a timeout interrupt occurs.

This embodiment has the advantage that simultaneous processing of a large number of timers (determined by the capacity of the memory element 100) and no software are required.

[0018]

As described above, according to the present invention, time management of a large number of sequences can be realized simultaneously using a relatively simple circuit and software processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a circuit diagram representing one embodiment of the present invention.

FIG. 3 is a timing chart schematically showing the operation of the circuit in FIG. 2;

[Explanation of symbols]

10...Storage means 12...Timer processing means 16...Selection means 50...CPU

Claims (2)

[Claims] Claim 1: A timer circuit that manages a plurality of timers accessible from a CPU (50), wherein the CPU
storage means (10) that can be accessed from (50) and stores the count values of the plurality of timers; A timer circuit comprising: timer processing means (12) that updates the timer periodically and, if there is a timer that has finished counting, notifies the CPU (50) of the number of that timer. 2. A bus for the CPU (50) and a bus for the timer processing means (12) are alternately connected to the storage means (12).
2. A timer circuit according to claim 1, further comprising selection means (16) connected to the timer circuit (10).