JPH0428228A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0428228A JPH0428228A JP13293490A JP13293490A JPH0428228A JP H0428228 A JPH0428228 A JP H0428228A JP 13293490 A JP13293490 A JP 13293490A JP 13293490 A JP13293490 A JP 13293490A JP H0428228 A JPH0428228 A JP H0428228A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- silicon oxide
- semiconductor device
- manufacturing
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 230000015556 catabolic process Effects 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- -1 nitrogen ions Chemical class 0.000 claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 35
- 229910052814 silicon oxide Inorganic materials 0.000 description 35
- 230000005684 electric field Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要］
半導体装置の製造方法に関し、
シリコン酸化膜に高電界を加えても正孔蓄積による絶縁
破壊を生じ難くすることができる半導体装置及びその製
造方法を提供することを目的とし、少なくともシリコン
を含有する酸化膜に該酸化膜耐圧を向上させるために窒
素イオンを注入角度５度以上１０度以下の範囲でイオン
注入し、次いで熱処理する工程を含むように構成する。[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a semiconductor device, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can make it difficult to cause dielectric breakdown due to hole accumulation even when a high electric field is applied to a silicon oxide film. In order to improve the withstand voltage of the oxide film, the method includes the steps of implanting nitrogen ions into an oxide film containing at least silicon at an implantation angle of 5 degrees or more and 10 degrees or less, and then performing heat treatment.
本発明は、シリコン酸化膜を有する半導体装置の製造方
法において、電界を加えたときの歩留まりを向上させる
ためにシリコン酸化膜に窒素を注入した絶縁膜に関する
。The present invention relates to an insulating film in which nitrogen is implanted into a silicon oxide film in order to improve the yield when an electric field is applied in a method of manufacturing a semiconductor device having a silicon oxide film.
近年のＬＳＩの高集積化に伴い、ゲート酸化膜や蓄積キ
ャパシター酸化膜に用いられるシリコン酸化膜は増々薄
くなってきている。一方電源電圧はスケールダウンに比
べて下げることができず、シリコン酸化膜にかかる電界
強度は増加する傾向にある。高電界ではシリコン酸化膜
は絶縁破壊を起こし易く、歩留まりも低下する。このた
め、歩留まりを向上させるため、容易に絶縁破壊を起こ
さないシリコン酸化膜を形成する技術が要求されている
。With the recent trend toward higher integration of LSIs, silicon oxide films used for gate oxide films and storage capacitor oxide films are becoming increasingly thinner. On the other hand, the power supply voltage cannot be lowered compared to scaling down, and the electric field strength applied to the silicon oxide film tends to increase. In high electric fields, silicon oxide films are prone to dielectric breakdown, and yields are also reduced. Therefore, in order to improve yield, there is a need for a technique for forming a silicon oxide film that does not easily cause dielectric breakdown.
従来の半導体装置においては、ゲート酸化膜（シリコン
酸化膜）や蓄積キャパシター酸化膜（シリコン酸化膜）
を酸素雰囲気中で熱処理あるいはＣＶＤ法により形成し
、そのシリコン酸化膜上部にポリＳｉ等の電極を堆積す
る等してＭＯ３構造を得ていた。In conventional semiconductor devices, gate oxide film (silicon oxide film) and storage capacitor oxide film (silicon oxide film)
The MO3 structure was obtained by forming a silicon oxide film by heat treatment or CVD in an oxygen atmosphere, and depositing an electrode such as poly-Si on top of the silicon oxide film.
ところが、」二層した半導体装置の製造方法では、素子
が微細化されるとスケーリングの法則により設計上シリ
コン酸化膜の膜厚を薄くしなければならず、このため、
シリコン酸化膜に加わる電界強度が大きくなりトンネル
電流が流れ易くなる。以下、これについては第４図に示
すシリコン酸化膜のエネルギーバンドを用いて具体的に
説明する。However, in the manufacturing method of two-layer semiconductor devices, as the elements become smaller, the design of the silicon oxide film must be made thinner due to the law of scaling.
The electric field strength applied to the silicon oxide film increases, making it easier for tunnel current to flow. This will be specifically explained below using the energy band of the silicon oxide film shown in FIG.
まず、ポリＳｉから電子を注入する場合を考える。シリ
コン酸化膜膜厚が厚い場合は、第４図（ａ）に示すバリ
ア幅Ｈ１が大きくなり電界強度が小さいためトンネル電
流はほとんど流れない。First, consider the case where electrons are injected from poly-Si. When the silicon oxide film is thick, the barrier width H1 shown in FIG. 4(a) becomes large and the electric field strength is small, so that almost no tunnel current flows.
ところが、シリコン酸化膜膜厚が薄くなると、第４図（
ｂ）に示すバリア幅Ｈ２が小さくなり電界強度が大きく
なるため、シリコン酸化膜に注入された電子は高いエネ
ルギーを持つので、インパクト・アイオニゼーションを
引き起こし電子と正孔が発生ずる。この時、シリコン酸
化膜中の移動度が高い電子は抜けるが正孔は酸化膜中に
残る。そして、時間とともに正札は酸化膜中に蓄積され
、それに伴い電子のトンネル確率が増加してトンネル電
流が増加する（第４図（Ｃ））。トンネル電流が増加す
ると蓄積される正孔も増えて電流増加に加速がつき、遂
には絶縁破壊に到る。However, as the silicon oxide film becomes thinner, as shown in Figure 4 (
As the barrier width H2 shown in b) becomes smaller and the electric field strength becomes larger, the electrons injected into the silicon oxide film have high energy, causing impact ionization and generating electrons and holes. At this time, electrons with high mobility in the silicon oxide film escape, but holes remain in the oxide film. Then, over time, the genuine tags are accumulated in the oxide film, and accordingly, the probability of electron tunneling increases and the tunneling current increases (FIG. 4(C)). As the tunneling current increases, the number of accumulated holes also increases, accelerating the increase in current, and eventually leading to dielectric breakdown.
したがって、初期不良の少ない酸化膜が得られたとして
も、高電界を印加すると正孔が蓄積され絶縁破壊すると
いった問題を生じていた。Therefore, even if an oxide film with few initial defects is obtained, a problem arises in that holes are accumulated and dielectric breakdown occurs when a high electric field is applied.
そこで本発明は、シリコン酸化膜に高電界を加えても正
孔蓄積による絶縁破壊を生じ難くすることができる半導
体装置の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that makes it difficult to cause dielectric breakdown due to hole accumulation even when a high electric field is applied to a silicon oxide film.
本発明による半導体装置の製造方法は上記目的達成のた
め、少なくともシリコンを含有する酸化膜に該酸化膜耐
圧を向上させるために窒素イオンを注入角度５度以上１
０度以下の範囲でイオン注入し、次いで熱処理する工程
を含むものである。In order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention implants nitrogen ions into an oxide film containing at least silicon at an angle of 5 degrees or more to improve the breakdown voltage of the oxide film.
This process includes a step of implanting ions at a temperature of 0 degrees or less and then performing heat treatment.
本発明において、窒素イオンの注入角度の下限を５度と
したのは、注入角度が５度より小さくなると酸化膜表面
で反射され、イオン種が酸化膜中に取り込まれなくなっ
てしまうからである。また、注入角度の上限を１０度と
したのは、注入角度が１０度より大きくなると酸化膜を
突き抜けてＳｉノ＜ルクに達してしまうので、イオン種
が酸化膜中に取り込まれなくなり、また、注入加速電圧
を低く制御することが困難となってしまうからである。In the present invention, the lower limit of the implantation angle of nitrogen ions is set to 5 degrees because if the implantation angle is smaller than 5 degrees, the ion species will be reflected from the oxide film surface and will not be incorporated into the oxide film. In addition, the upper limit of the implantation angle was set to 10 degrees because if the implantation angle was greater than 10 degrees, the ion species would penetrate the oxide film and reach the Si nozzle, so the ion species would not be incorporated into the oxide film. This is because it becomes difficult to control the injection acceleration voltage to a low level.
本発明においては、前記酸化膜はリンが含有されている
ＰＳＧ膜、リン及びボロンが含有されているＢＰＳＧ膜
であってもよい。In the present invention, the oxide film may be a PSG film containing phosphorus or a BPSG film containing phosphorus and boron.
本発明では、第３図（ｂ）に示す如くシリコン酸化膜中
にＮを位置するようにし、シリコン酸化膜の禁制帯中に
１−ラップを形成する。このため、シリコン酸化膜に高
電界を印加して電子をトンネルさせても、キャリアはト
ラップを介してシリコン酸化膜から抜けるためシリコン
酸化膜中に電荷が溜まることはない（ｊ＋、ｊｚ）。そ
のため、従来の第３図（ａ）に示す何もイオン注入して
いない場合化じるようなエネルギー・バンドがベンディ
ングすることもなく 、］、ＯＭＶ ／ ｃｍ以上の高
電界がかかるまで容易に絶縁破壊しない。In the present invention, as shown in FIG. 3(b), N is located in the silicon oxide film to form a 1-wrap in the forbidden band of the silicon oxide film. Therefore, even if a high electric field is applied to the silicon oxide film to cause electrons to tunnel, carriers escape from the silicon oxide film via traps, so no charges are accumulated in the silicon oxide film (j+, jz). Therefore, there is no bending of the energy band, which would occur if no ions were implanted as shown in Fig. 3(a), and the insulation can be easily maintained until a high electric field of more than OMV/cm is applied. Do not destroy.
したがって、このシリコン酸化膜をＭＯＳゲトやキャパ
シターの絶縁膜に用いた場合には、高電界に対し絶縁破
壊し難くすることができるため、信顛性の高いＬＳＩを
構成することができる。Therefore, when this silicon oxide film is used as an insulating film for a MOS gate or a capacitor, it can be made difficult to cause dielectric breakdown in response to a high electric field, so that an LSI with high reliability can be constructed.
以下、本発明を図面に基づいて説明する。 Hereinafter, the present invention will be explained based on the drawings.
第１図及び第２図は本発明に係る半導体装置の製造方法
の一実施例を説明する図であり、第１図は一実施例の製
造方法を説明する図、第２図は一実施例の効果を説明す
る図である。図示例の製造方法はＭＯ３Ｉ−ランジスク
等の製造方法に適用することができる。第１図において
、ｌはＳｉ等からなる基板、２はＳ ｉ ０２等からな
るシリコン酸化膜、２ａ！ｉ′Ｎが含有されたシリコン
酸化膜である。1 and 2 are diagrams for explaining one embodiment of the method for manufacturing a semiconductor device according to the present invention, FIG. 1 is a diagram for explaining the method for manufacturing one embodiment, and FIG. 2 is a diagram for explaining one embodiment. It is a figure explaining the effect of. The manufacturing method of the illustrated example can be applied to a manufacturing method of MO3I-Landisc, etc. In FIG. 1, l is a substrate made of Si or the like, 2 is a silicon oxide film made of S i 02 or the like, and 2a! This is a silicon oxide film containing i'N.
次に、その製造方法について説明する。Next, the manufacturing method will be explained.
まず、第１図（ａ）に示す例えばｐ型Ｓ ｉ （１００
）からなる基板ｌを用い、第１図（ｂ）に示すように、
例えば１０００℃の乾燥酸素雰囲気中で基板１上にシリ
コン酸化膜２を膜厚が例えば２０ｎｍで形成する。First, for example, p-type Si (100
), as shown in FIG. 1(b),
For example, a silicon oxide film 2 having a thickness of 20 nm, for example, is formed on a substrate 1 in a dry oxygen atmosphere at 1000°C.
次に、第１図（Ｃ）に示すように、Ｎを７°の角度、エ
ネルギー１０ ＫｅＶでシリコン酸化膜２にイオン注入
することにより、第１図（ｄ）に示すような中央にＲＰ
（分布のピーク）を持つＮが含有されたシリコン酸
化膜２ａを得ることができる。Next, as shown in FIG. 1(C), N is ion-implanted into the silicon oxide film 2 at an angle of 7° with an energy of 10 KeV to form a RP in the center as shown in FIG. 1(d).
A silicon oxide film 2a containing N having a distribution peak can be obtained.
そして、このシリコン酸化膜２ａをゲート酸化膜や蓄積
キ、ドパジター酸化膜として用い、半導体装置を構成す
る。Then, a semiconductor device is constructed using this silicon oxide film 2a as a gate oxide film, a storage layer, and a dopant oxide film.
すなわち、」二層実施例では、第２図（ａ）、（ｂ）に
示すように、ＭＯＳダイオードの酸化膜耐圧が向上して
いるかどうかの効果を示すヒストグラムを調べたところ
、Ｎを注入した第２図（ｂ）に示す場合では何も注入し
ていない第２図（ａ）に示す従来の場合（レファレンス
）と比較して分布が高耐圧側に鋭いピークをもつように
なり、１０ＭＶ／ｃｍ以上の耐圧をもつ良品率は従来の
レファレンスでは６９％であるが、Ｎを注入すると９２
％になっているのが判った。In other words, in the two-layer embodiment, as shown in FIGS. 2(a) and 2(b), when examining the histogram showing the effect of improving the oxide film breakdown voltage of the MOS diode, it was found that N was implanted. In the case shown in Fig. 2(b), compared to the conventional case (reference) shown in Fig. 2(a) in which nothing is injected, the distribution has a sharp peak on the high breakdown voltage side, and 10 MV/ The rate of non-defective products with a breakdown voltage of cm or more is 69% with conventional references, but when N is injected, it increases to 92%.
I found that it was %.
なお、上記実施例ではシリコン酸化膜１にＮをイオン注
入して耐圧特性が優れている場合について説明したが、
本発明は、これに限定されるものではなく、イオン注入
後熱処理（例えば、１０００”１０分、Ｎガス雰囲中）
する場合であってもよく、この場合もＮをシリコン酸化
膜にイオン注入する場合と同様耐圧特性が優れている。Incidentally, in the above embodiment, a case was explained in which N was ion-implanted into the silicon oxide film 1 to obtain excellent breakdown voltage characteristics.
The present invention is not limited to this, and the heat treatment after ion implantation (for example, 1000" for 10 minutes in an N gas atmosphere)
In this case as well, the withstand voltage characteristics are excellent as in the case where N is ion-implanted into the silicon oxide film.
本発明によれば、シリコン酸化膜に高電界を加えても正
孔蓄積による絶縁破壊を生じ難くすることができるとい
う効果がある。According to the present invention, there is an effect that dielectric breakdown due to hole accumulation can be made difficult to occur even when a high electric field is applied to a silicon oxide film.
第１図及び第２図は本発明に係る半導体装置の製造方法
の一実施例を説明する図であり、第１図は一実施例の製
造方法を説明する図、第２図は一実施例の効果を説明す
る図、第３図は本発明の詳細な説明する図、
第４′図は従来例の課題を説明する図である。
１・・・・・・基板、
２．２ａ・・・・・・シリコン酸化膜。
班１
２／−−へ＼、
誼■1 and 2 are diagrams for explaining one embodiment of the method for manufacturing a semiconductor device according to the present invention, FIG. 1 is a diagram for explaining the method for manufacturing one embodiment, and FIG. 2 is a diagram for explaining one embodiment. FIG. 3 is a diagram explaining the present invention in detail, and FIG. 4' is a diagram explaining the problems of the conventional example. 1...Substrate, 2.2a...Silicon oxide film. Group 1 2/--to＼, 誼■
Claims (1)
を向上させるために窒素イオンを注入角度５度以上１０
度以下の範囲でイオン注入し、次いで熱処理する工程を
含むことを特徴とする半導体装置の製造方法。Nitrogen ions are implanted into an oxide film containing at least silicon at an angle of 5 degrees or more to improve the breakdown voltage of the oxide film.
1. A method for manufacturing a semiconductor device, the method comprising the steps of implanting ions at a temperature below 100° C. and then performing heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2132934A JP2831805B2 (en) | 1990-05-23 | 1990-05-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2132934A JP2831805B2 (en) | 1990-05-23 | 1990-05-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0428228A true JPH0428228A (en) | 1992-01-30 |
| JP2831805B2 JP2831805B2 (en) | 1998-12-02 |
Family
ID=15092917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2132934A Expired - Fee Related JP2831805B2 (en) | 1990-05-23 | 1990-05-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2831805B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11204793A (en) * | 1997-10-24 | 1999-07-30 | Lsi Logic Corp | Electronic device gate oxide hardening method and semiconductor device |
-
1990
- 1990-05-23 JP JP2132934A patent/JP2831805B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11204793A (en) * | 1997-10-24 | 1999-07-30 | Lsi Logic Corp | Electronic device gate oxide hardening method and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2831805B2 (en) | 1998-12-02 |
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