JPH04280622A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04280622A
JPH04280622A JP6883891A JP6883891A JPH04280622A JP H04280622 A JPH04280622 A JP H04280622A JP 6883891 A JP6883891 A JP 6883891A JP 6883891 A JP6883891 A JP 6883891A JP H04280622 A JPH04280622 A JP H04280622A
Authority
JP
Japan
Prior art keywords
doped
semiconductor
layer
diamond
carrier density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6883891A
Other languages
Japanese (ja)
Other versions
JP2985337B2 (en
Inventor
Yoshiki Nishibayashi
良樹 西林
Naoharu Fujimori
直治 藤森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
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Filing date
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Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP3068838A priority Critical patent/JP2985337B2/en
Publication of JPH04280622A publication Critical patent/JPH04280622A/en
Application granted granted Critical
Publication of JP2985337B2 publication Critical patent/JP2985337B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/122Single quantum well structures
    • H01L29/125Quantum wire structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1602Diamond

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To manufacture a semiconductor having less temperature dependent carrier density and specific resistance for a diamond semiconductor having a deep doping level of impurities. CONSTITUTION:A high density impurity doped two-dimensional layer or a one- dimensional linear film is encircled by a non-impurity doped layer or a low- impurity-doped layer. The high density impurity-doped layer has less temperature dependency of carrier density similar to the conductivity of metal. However, as there is a non-doped layer, the average carrier density can be brought to the desired value. As a result, carrier density and the temperature dependency of electric resistance is low.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はダイヤモンド半導体を用
いたダイオ−ド、トランジスタ、などのデバイスに関す
るものである。とくにキャリヤ濃度の温度変化が少ない
ダイヤモンド半導体に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to devices such as diodes and transistors using diamond semiconductors. In particular, it relates to diamond semiconductors whose carrier concentration changes little with temperature.

【0002】0002

【従来の技術】ダイヤモンド半導体は高温下、放射線下
などの環境下で安定に動作するデバイスとして或は高出
力での動作にも耐え得るデバイスとしてその応用が注目
されている。ダイヤモンド半導体が高温下でも動作可能
な理由として、バンドギャップが5.5eVと大きいこ
とが挙げられている。このことは、半導体のキャリアが
制御されなくなる温度範囲(真性領域)が1400℃以
下には存在しないことを示している。不純物のないダイ
ヤモンドは絶縁体であるが、適当な不純物を加えるとn
型またはp型の半導体になる。たとえばp型にするため
にはAl、Bを、n型にするためにはN、P、S等の不
純物を添加する。
2. Description of the Related Art Diamond semiconductors are attracting attention for their applications as devices that operate stably under environments such as high temperatures and radiation, or as devices that can withstand operation at high outputs. The reason why diamond semiconductors can operate even at high temperatures is that they have a large band gap of 5.5 eV. This shows that there is no temperature range (intrinsic region) below 1400° C. in which semiconductor carriers are no longer controlled. Diamond without impurities is an insulator, but when appropriate impurities are added, it becomes n
type or p-type semiconductor. For example, impurities such as Al and B are added to make the material p-type, and N, P, and S are added to make it n-type.

【0003】しかし、Al、B、N、P、Sなどをダイ
ヤモンドにド−ピングしても、これら不純物のド−ピン
グレベルが深くキャリアを飽和領域で用いることが困難
であった。この点はシリコンと比較すれば問題の所在が
明らかになろう。シリコンの場合、p型不純物はボロン
であるがこの不純物準位は価電子帯から0.045eV
にある。n型不純物はP、As、Sbであるがこれらの
準位は伝導帯端から0.045eV、0.049eV、
0.039eVでありバンド端の極近くに浅い不純物準
位を作る。これは室温のエネルギ−0.025eVと同
等であるから、これらの不純物がもたらした正孔、電子
はそれぞれ価電子帯、伝導帯に励起されていて、その数
が室温付近の温度ではあまり変化しない。このような温
度域を飽和領域と言っている。ところがド−ピングした
不純物の準位が深いと、これより励起されるのに大きな
エネルギ−が必要であるから温度によって励起されたキ
ャリヤ密度が大きく異なる。キャリヤ密度はexp(−
ΔE/kT)に比例するが、ΔEが不純物準位にほぼ該
当するので、不純物準位が深いと温度Tによるキャリヤ
密度変化が著しい。半導体の抵抗はキャリヤ密度と移動
度とに依存し移動度も温度によって変化するがここでは
キャリヤ濃度の変化を問題にする。
However, even when diamond is doped with Al, B, N, P, S, etc., the doping level of these impurities is deep, making it difficult to use carriers in the saturated region. A comparison with silicon will reveal where the problem lies. In the case of silicon, the p-type impurity is boron, and this impurity level is 0.045 eV from the valence band.
It is in. The n-type impurities are P, As, and Sb, and their levels are 0.045 eV, 0.049 eV, and 0.049 eV from the conduction band edge.
It is 0.039 eV and creates a shallow impurity level extremely close to the band edge. This is equivalent to the energy at room temperature -0.025eV, so the holes and electrons brought by these impurities are excited to the valence band and conduction band, respectively, and their numbers do not change much at temperatures around room temperature. . This temperature range is called the saturated region. However, if the level of the doped impurity is deep, more energy is required to excite it, so the density of excited carriers varies greatly depending on the temperature. The carrier density is exp(-
ΔE/kT), but since ΔE almost corresponds to the impurity level, when the impurity level is deep, the carrier density changes significantly depending on the temperature T. The resistance of a semiconductor depends on the carrier density and mobility, and the mobility also changes depending on the temperature, but here we will focus on changes in the carrier concentration.

【0004】半導体が飽和領域で用いられていないと温
度によってデバイスの特性が大きく変化する。温度変化
によってキャリヤ密度、抵抗率等が大きく変化するから
である。そして所望の特性を持った素子として機能する
温度範囲が狭くなる等問題が生じて来る。例えばボロン
をダイヤモンドにド−ピングした場合キャリアの活性化
エネルギ−は0.2〜0.4eVであり、室温から60
0℃の範囲でキャリアの濃度は2〜3桁変化する。ここ
で活性化エネルギ−というのは分布関数のexp(−Δ
E/kT)の中のΔEのエネルギ−のことである。これ
は、補償効果がない場合バンド端から不純物準位までの
エネルギ−の半分であり、補償効果がある場合はバンド
端から不純物準位までのエネルギ−と同じ値である。
[0004] If the semiconductor is not used in the saturated region, the characteristics of the device will change significantly depending on the temperature. This is because carrier density, resistivity, etc. change greatly due to temperature changes. Problems arise, such as a narrowing of the temperature range in which the device functions as an element with desired characteristics. For example, when diamond is doped with boron, the activation energy of the carriers is 0.2 to 0.4 eV, and the activation energy is 0.2 to 0.4 eV.
The carrier concentration changes by two to three orders of magnitude in the 0°C range. Here, the activation energy is the distribution function exp(-Δ
It is the energy of ΔE in E/kT). This is half the energy from the band edge to the impurity level when there is no compensation effect, and is the same value as the energy from the band edge to the impurity level when there is a compensation effect.

【0005】[0005]

【発明が解決しようとする課題】ダイヤモンドにおける
半導体としての利用価値を高めるためには動作温度領域
でキャリヤ密度が変化しないようにしなければならない
。そうするためには不純物を大量にド−ピングして不純
物レベルを縮退させるという方法が考えられる。しかし
そうするとキャリヤ密度が高くなり過ぎ金属と同じよう
になる。すると半導体に必要な性質、例えば電界によっ
てキャリヤの空乏層ができ電流を制御できるとか、pn
接合ができ整流性があるとかいった性質が失われてしま
う。こうなるのを避けて、キャリヤ密度は所望の範囲に
ありながらしかもキャリヤ密度の温度による変化を少な
くしたダイヤモンド半導体を提供することが本発明の目
的である。
Problems to be Solved by the Invention In order to increase the utility value of diamond as a semiconductor, it is necessary to prevent the carrier density from changing in the operating temperature range. In order to do this, a method of doping a large amount of impurities to degenerate the impurity level can be considered. However, if this is done, the carrier density becomes too high and becomes similar to that of metals. Then, the properties necessary for semiconductors, such as the ability to create a carrier depletion layer by an electric field and control the current,
Properties such as bondability and rectification properties are lost. It is an object of the present invention to avoid this and provide a diamond semiconductor in which the carrier density is within a desired range and the change in carrier density due to temperature is reduced.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
ド−ピングレベルが深く室温では飽和領域にないド−パ
ントを有しているダイヤモンド半導体であって、該ド−
パントを多量にド−ピングした2次元的な広がりを持つ
高ド−プ半導体層と、ノンド−プ層あるいは低ド−プ層
とを交互に積層し全体として所望のキャリヤ濃度にして
あることを特徴とする。或は、ド−ピングレベルが深く
室温では飽和領域にないド−パントを有しているダイヤ
モンド半導体であって、該ド−パントを多量にド−ピン
グした多数の平行な高ド−プ半導体線膜と、この高ド−
プ半導体線膜を1次元的に閉じ込めるノンド−プ層ある
いは低ド−プ層とよりなり全体として所望のキャリヤ濃
度にしてあることを特徴とする。つまり高ド−プ2次元
層あるいは高ド−プ1次元線を低ド−プ層、ノンド−プ
層で囲んだ構造である。前者を2次元構造、後者を1次
元構造と呼ぶ。例えば2次元構造についていうと、アク
セプターのレベルが縮腿するほどに高濃度にド−ピング
したp+ 層とノンドープ層とを交互に多数層積層した
p+ −i−p+ −i−p+ −i・・多層構造を用
いる。1次元構造についていえば高濃度にド−ピングし
たp+ 線膜を多数平行に設けこれを低ド−プ、ノンド
−プ層で囲む。つまりp+ 層、線膜をノンドープ層に
よって2次元的、1次元的に閉じ込めることにより、キ
ャリヤ密度の温度変化を少なくし、且つそのド−ピング
濃度を適当な範囲に制御しようと言うものである。ド−
ピング濃度はキャリヤ密度にほぼ比例するから、所望の
範囲のキャリヤ密度の半導体をうることができる。これ
はn型のダイヤモンドでも同様である。高密度にn型不
純物をド−ピングしたn+ 層とノンド−プ層とを交互
に多数層積層し、n+ −i−n+ −i−・・という
ような積層構造にする。こうすると平均のキャリヤ密度
は、それぞれの層でのキャリヤ密度を層の厚みを掛けて
平均したものであるから、層の厚みの比率を変えること
によって任意の平均キャリヤ密度を実現できる。
[Means for Solving the Problems] A semiconductor device of the present invention includes:
A diamond semiconductor having a deep doping level and a dopant that is not in the saturation region at room temperature;
Highly doped semiconductor layers doped with a large amount of punt and having a two-dimensional spread are alternately laminated with non-doped or lightly doped layers to achieve a desired carrier concentration as a whole. Features. Alternatively, a diamond semiconductor having a dopant with a deep doping level and not in the saturation region at room temperature, and a large number of parallel highly doped semiconductor lines heavily doped with the dopant. membrane and this high dose
It is characterized in that it consists of a non-doped layer or a lightly doped layer that one-dimensionally confines the doped semiconductor line film, and has a desired carrier concentration as a whole. In other words, it has a structure in which a highly doped two-dimensional layer or a highly doped one-dimensional line is surrounded by a lightly doped layer or a non-doped layer. The former is called a two-dimensional structure, and the latter is called a one-dimensional structure. For example, in the case of a two-dimensional structure, a p+ -i-p+ -i-p+ -i . Use a multilayer structure. Regarding the one-dimensional structure, a large number of highly doped p+ ray films are provided in parallel and surrounded by lightly doped, non-doped layers. In other words, by confining the p+ layer and line film two-dimensionally and one-dimensionally with a non-doped layer, temperature changes in carrier density are reduced and the doping concentration is controlled within an appropriate range. Do
Since the ping concentration is approximately proportional to the carrier density, a semiconductor having a desired range of carrier density can be obtained. This also applies to n-type diamond. A large number of n+ layers doped with n-type impurities and non-doped layers are alternately laminated to form a laminated structure of n+ -i-n+-i-.... In this way, the average carrier density is the average of the carrier densities in each layer multiplied by the layer thicknesses, so any average carrier density can be achieved by changing the ratio of the layer thicknesses.

【0007】単にp型不純物を大量にド−ピングしたp
+ 層のみの膜ならフェルミレベルは価電子帯に近づき
、あるいは価電子帯中に入り込む。或は単にn型不純物
を大量にド−ピングしたn+ 層のみの膜ならフェルミ
レベルは伝導帯に近付き或は伝導帯に入り込む。それぞ
れ自由正孔、自由電子が大量に存在することになって金
属的な電気伝導を示すようになる。このような膜の電気
伝導は温度依存性がほとんどないようにすることができ
る。 しかしこうすると、ダイオ−ドやトランジスタとするた
めの最適なド−ピング濃度より遥かに高い。そこで本発
明においては、、フェルミレベルを伝導帯に近づけた状
態でド−ピング濃度を下げるために、厚いノンドープ層
によってド−ピング層をはさみド−ピング層を2次元的
に閉じ込めた構造とする。ド−ピング層の厚みをd、ノ
ンド−プ層の厚みをDとし、ド−ピング層の正孔濃度を
p+ とすると、平均の正孔濃度pは、p=p+ d/
(d+D)となる。
[0007] Simply doped with a large amount of p-type impurities
For a film with only + layers, the Fermi level approaches the valence band or enters the valence band. Alternatively, if the film is simply an n+ layer doped with a large amount of n-type impurities, the Fermi level approaches or enters the conduction band. There are large amounts of free holes and free electrons, respectively, and they exhibit metallic electrical conductivity. The electrical conduction of such a membrane can be made to have almost no temperature dependence. However, this is far higher than the optimum doping concentration for diodes and transistors. Therefore, in the present invention, in order to lower the doping concentration while keeping the Fermi level close to the conduction band, a structure is used in which the doped layer is sandwiched between thick non-doped layers and the doped layer is confined two-dimensionally. . When the thickness of the doped layer is d, the thickness of the non-doped layer is D, and the hole concentration of the doped layer is p+, the average hole concentration p is p=p+ d/
(d+D).

【0008】[0008]

【作用】ダイヤモンドはバンドギャップが5.5eVと
大きいため、真性領域に相当する温度領域は、ダイヤモ
ンドが熱的に安定な1400℃以下には存在しない。ま
た化学的にも非常に安定である。又、ダイヤモンドの熱
伝導率は20(W/cm・K)とSiの10倍以上であ
り、放熱性にも優れている。さらに、ダイヤモンドは、
キャリアの移動度が大きい(電子移動度:2000(c
m2 /V・秒)、ホール移動度:2100(cm2 
/V・秒)、300K)、誘電率が小さい(K=5.5
)、破壊電界が大きい(E=5×106 V/cm)な
どの特徴を有しており、高周波で大電力用のデバイスを
作製することができる。
[Operation] Since diamond has a large band gap of 5.5 eV, a temperature region corresponding to the intrinsic region does not exist below 1400° C., where diamond is thermally stable. It is also chemically very stable. Furthermore, diamond has a thermal conductivity of 20 (W/cm·K), which is more than 10 times that of Si, and has excellent heat dissipation. Furthermore, the diamond
Carrier mobility is large (electron mobility: 2000 (c
m2 /V・sec), Hall mobility: 2100 (cm2
/V・sec), 300K), low dielectric constant (K=5.5
) and a large breakdown electric field (E=5×10 6 V/cm), making it possible to fabricate high-frequency, high-power devices.

【0009】さらに、ダイヤモンドは不純物を含まない
と絶縁体であるという特徴も有しているため、素子を作
製する際、基板として用いるダイヤモンドと動作層のダ
イヤモンドとを電気的に完全に分離できるという利点が
ある。本発明は、高温での動作や高出力・高周波での動
作の可能な耐環境性にも優れたダイヤモンドデバイスを
実現するために、室温から600℃の範囲で飽和領域を
もつ半導体ダイヤモンドを形成することである。本発明
においては、不純物を大量にド−プしたp+ またn+
 層をノンド−プ層で挟んだもので、平均のキャリヤ密
度は半導体に適当な範囲でありながら、ド−ピング層で
はキャリヤ密度が高く、温度によるキャリヤ密度の変化
が少ない。このため全体としてキャリヤ密度の温度によ
る変化が少ないものとなる。適用される半導体性ダイヤ
モンドは、天然あるいは人工(高圧合成)のバルク単結
晶であっても、気相合成による薄膜多結晶あるいは、薄
膜単結晶(エピタキシャル膜)であってもその効果は変
わらない。
Furthermore, diamond has the characteristic that it is an insulator unless it contains impurities, so when manufacturing devices, it is possible to completely electrically separate the diamond used as the substrate and the diamond in the active layer. There are advantages. The present invention aims to form semiconductor diamond that has a saturation region between room temperature and 600°C in order to realize a diamond device with excellent environmental resistance that can operate at high temperatures, high power, and high frequency. That's true. In the present invention, p+ doped with a large amount of impurities or n+
The layer is sandwiched between non-doped layers, and while the average carrier density is within a range suitable for semiconductors, the doped layer has a high carrier density and the carrier density does not change much with temperature. Therefore, as a whole, there is little change in carrier density due to temperature. The applied semiconductor diamond has the same effect whether it is a natural or artificial (high-pressure synthesis) bulk single crystal, a thin film polycrystal formed by vapor phase synthesis, or a thin film single crystal (epitaxial film).

【0010】気相合成ダイヤモンド膜において、形成す
る方法としては、(1)直流または交流電界により放電
を起こし、原料ガスを活性化する方法、(2)熱電子放
射材を加熱し、原料ガスを活性化する方法、(3)ダイ
ヤモンドを成長させる表面をイオンで衝撃する方法、(
4)レーザーや紫外線などの光で原料ガスを励起する方
法、及び(5)原料ガスを燃焼させる方法等各種の方法
があるが、いずれの方法も本発明に用いることができ、
発明の効果は変わらない。
[0010] Methods for forming a vapor phase synthesized diamond film include (1) a method in which discharge is caused by a DC or AC electric field to activate the raw material gas, and (2) a method in which a thermionic emitter is heated to activate the raw material gas. Activation method, (3) method of bombarding the surface on which diamond will grow with ions, (
There are various methods such as 4) a method of exciting the raw material gas with light such as a laser or ultraviolet light, and (5) a method of burning the raw material gas, and any of these methods can be used in the present invention.
The effect of the invention remains the same.

【0011】[0011]

【実施例】[実施例1]人工の単結晶ダイヤモンド基板
(Ib)の(100)面上にマイクロ波プラズマCVD
法によって次のような条件でノンド−プ層とp+ 層を
交互に成膜を行った。 (1)ノンドープ層の成膜条件は以下のとおりである。         ガス流量    H2 流量    
          100sccm        
              CH4 流量     
           6sccm        圧
力                        
        40Torr          パ
ワー                       
     200W          基板温度  
                        6
00℃(2)p+ 層(ボロンド−プ層)の成膜条件は
次のとおりである。         ガス流量    H2 流量    
          100sccm        
              CH4 流量     
           6sccm         
           B2 H6 流量      
        1sccm            
          (200ppm)       
                         
            圧力           
                     40To
rr          パワー          
                  200W   
       基板温度              
            600℃
[Example] [Example 1] Microwave plasma CVD on the (100) plane of an artificial single crystal diamond substrate (Ib)
A non-doped layer and a p+ layer were alternately formed by a method under the following conditions. (1) The conditions for forming the non-doped layer are as follows. Gas flow rate H2 flow rate
100sccm
CH4 flow rate
6sccm pressure
40Torr power
200W Substrate temperature
6
00°C (2) The conditions for forming the p+ layer (boron doped layer) are as follows. Gas flow rate H2 flow rate
100sccm
CH4 flow rate
6sccm
B2 H6 flow rate
1sccm
(200ppm)

pressure
40To
rr power
200W
Substrate temperature
600℃

【0012】単結晶
ダイヤモンドの(100)面にノンドープ層と高濃度層
とを交互に積層するのであるが、膜の厚さを異ならせた
以下の2種類の試料を作った。 試料(a)ノンドープ層5000Å、p+ 層50Å 
     5サイクル成長 試料(b)ノンドープ層500Å、p+ 層50Å  
    10サイクル成長 どちらも電子線回折により(100)方向にエピタキシ
ャル成長していることを確認できた。この試料のホール
効果を測定した結果を図1に示す。横軸は絶対温度の逆
数に1000を乗じた1000/Tである。縦軸はキャ
リヤ密度である(cm−3)。この結果から温度によっ
てキャリヤ密度が殆ど変わらないということが分かる。 つまり600℃〜室温の範囲で温度に依存しない飽和領
域の存在が確認された。また、(a)と(b)でキャリ
ア濃度の異なった試料を作製することができた。(a)
はp+ を50Å、ノンドープ層を5000Åずつ積層
したものであり、(b)はp+ 層を50Å、ノンドー
プ層を500Å積層したものであるから、平均のキャリ
ヤ密度は(a)が(b)の1/10になるはずであるが
実際の測定によってもそのようになっていることが分か
る。
[0012] Non-doped layers and high-concentration layers were alternately laminated on the (100) plane of single crystal diamond, and the following two types of samples were prepared with different film thicknesses. Sample (a) Non-doped layer 5000 Å, p+ layer 50 Å
5-cycle growth sample (b) Non-doped layer 500 Å, p+ layer 50 Å
In both cases of 10-cycle growth, it was confirmed by electron beam diffraction that epitaxial growth occurred in the (100) direction. Figure 1 shows the results of measuring the Hall effect of this sample. The horizontal axis is 1000/T, which is the reciprocal of the absolute temperature multiplied by 1000. The vertical axis is the carrier density (cm-3). This result shows that the carrier density hardly changes depending on the temperature. In other words, the existence of a temperature-independent saturated region in the range of 600° C. to room temperature was confirmed. In addition, samples with different carrier concentrations could be prepared in (a) and (b). (a)
(b) has a p+ layer of 50 Å and a non-doped layer of 500 Å, so the average carrier density in (a) is 1 in (b). /10, and actual measurements show that this is the case.

【0013】[実施例2]人工ダイヤモンド(高圧合成
、Ib、ボロン添加)を基板に用いて、実施例1と同じ
条件で試料(a)、(b)を作製した。試料(a)、(
b)の縦方向の電気抵抗の温度依存性を測定した。図2
にその結果を示す。横軸は絶対温度の逆数に1000を
乗じたものであり、縦軸は比抵抗(Ωcm)である。 この結果から比抵抗の温度依存性の小さいことが分かる
。実施例1と同様600℃〜室温の範囲で飽和領域の存
在を確認できた。さらに図1と図2の結果を比較してキ
ャリヤの移動度(キャリヤ密度と比抵抗の積の逆数に比
例)がキャリヤ密度に殆どよらないということがわかる
。通常半導体にキャリヤを高密度にド−ピングすると不
純物散乱が増えて移動度が減少するものであるがこれら
の結果から移動度が高密度ド−ピングにも拘らず減少し
ていない。
[Example 2] Samples (a) and (b) were prepared under the same conditions as in Example 1 using artificial diamond (high-pressure synthesis, Ib and boron added) as a substrate. Sample (a), (
The temperature dependence of the electrical resistance in the longitudinal direction of b) was measured. Figure 2
The results are shown below. The horizontal axis is the reciprocal of the absolute temperature multiplied by 1000, and the vertical axis is the specific resistance (Ωcm). This result shows that the temperature dependence of resistivity is small. As in Example 1, the existence of a saturated region was confirmed in the range of 600° C. to room temperature. Furthermore, by comparing the results in FIGS. 1 and 2, it can be seen that carrier mobility (proportional to the reciprocal of the product of carrier density and specific resistance) hardly depends on carrier density. Normally, when a semiconductor is doped with carriers at a high density, impurity scattering increases and the mobility decreases, but these results show that the mobility does not decrease despite the high density doping.

【0014】[実施例3]人工の単結晶ダイヤモンド基
板(Ib)の(100)面上にマイクロ波プラズマCV
D法によって次のような条件でノンド−プ層、p+ 層
の成長、p層のエッチングなどを交互に行い低ド−プ層
の中に、高ド−プ線膜を多数平行に形成した。 (1)ノンドープ層の成膜条件は以下のとおりである。         ガス流量    H2 流量    
          100sccm        
              CH4 流量     
           6sccm        圧
力                        
        40Torr          パ
ワー                       
     200W          基板温度  
                        6
00℃(2)p+ 層(ボロンド−プ層)の成膜条件は
次のとおりである。         ガス流量    H2 流量    
          100sccm        
              CH4 流量     
           6sccm         
       B2 H6 流量(200ppm)  
2sccm          圧力        
                        4
0Torr          パワー       
                     200W
        基板温度             
             600℃
[Example 3] Microwave plasma CV on the (100) plane of an artificial single crystal diamond substrate (Ib)
A large number of highly doped line films were formed in parallel in a lightly doped layer by alternately growing a non-doped layer, a p+ layer, and etching a p layer under the following conditions using method D. (1) The conditions for forming the non-doped layer are as follows. Gas flow rate H2 flow rate
100sccm
CH4 flow rate
6sccm pressure
40Torr power
200W Substrate temperature
6
00°C (2) The conditions for forming the p+ layer (boron doped layer) are as follows. Gas flow rate H2 flow rate
100sccm
CH4 flow rate
6sccm
B2 H6 flow rate (200ppm)
2sccm pressure
4
0Torr power
200W
Substrate temperature
600℃

【0015】試料
の作製方法を図3によって順に説明する。 (a)単結晶ダイヤモンド基板の(100)面にノンド
ープ膜を1000Å形成する。 (b)その上に高濃度ボロン膜を50Å程成長させる。 (c)さらにアルミを蒸着し、0.5μm 幅、4.5
μm 間隔でアルミをパタ−ニングした。平行なアルミ
マスクができたわけである。 (d)アルミマスクによって覆われていない部分を70
Å程エッチングする。その後アルミマスクを溶解除去す
る。 (e)さらにその上にノンド−プ層を1000Å成長さ
せた。 (f)この後、(b)〜(e)を3回繰り返した。多数
の平行な高濃度ボロンド−プ線膜が4層分形成できる。
A method for preparing a sample will be explained in order with reference to FIG. (a) A non-doped film of 1000 Å is formed on the (100) plane of a single crystal diamond substrate. (b) A high concentration boron film of about 50 Å is grown thereon. (c) Further evaporate aluminum, 0.5 μm width, 4.5
Aluminum was patterned at micrometer intervals. This resulted in a parallel aluminum mask. (d) The area not covered by the aluminum mask is 70
Etch approximately 300 yen. After that, the aluminum mask is dissolved and removed. (e) A non-doped layer of 1000 Å was further grown thereon. (f) After this, (b) to (e) were repeated three times. A large number of parallel high-concentration boron doped wire films can be formed in four layers.

【0016】こうして作られた試料は電子線回折により
(100)方向にエピタキシャル成長していることが確
認された。この試料のホール効果を測定した結果を図4
に示す。横軸は絶対温度の逆数に1000を乗じた10
00/Tである。縦軸はキャリヤ密度である(cm−3
)。この結果から温度によってこの試料のキャリヤ密度
が殆ど変わらないということが分かる。600℃〜室温
の範囲で温度に依存しない飽和領域の存在が確認される
。また、この方法で実施例1の(a)とキャリヤ濃度の
異なった試料を作製することができた。
It was confirmed by electron beam diffraction that the sample thus prepared was epitaxially grown in the (100) direction. Figure 4 shows the results of measuring the Hall effect of this sample.
Shown below. The horizontal axis is 10, which is the reciprocal of absolute temperature multiplied by 1000.
It is 00/T. The vertical axis is the carrier density (cm-3
). This result shows that the carrier density of this sample hardly changes with temperature. The existence of a temperature-independent saturated region is confirmed in the range of 600° C. to room temperature. Further, by this method, a sample having a different carrier concentration from Example 1 (a) could be prepared.

【0017】[0017]

【発明の効果】本発明の半導体装置は室温〜600℃の
範囲でキャリア密度にほとんど温度依存性がない。しか
もキャリアの密度を自在に制御することができる。また
、単独の膜では高濃度のド−ピングによってキャリアの
移動度が減少する問題点があったが、本発明の構造によ
っては顕著な減少がみられないという利点がある。従っ
て本発明の半導体装置は高温までの温度範囲で安定した
ダイオ−ドやトランジスタ特性を示すデバイスを実現す
る上に有効である。
Effects of the Invention In the semiconductor device of the present invention, the carrier density has almost no temperature dependence in the range from room temperature to 600°C. Moreover, the carrier density can be freely controlled. Further, although a single film has the problem that carrier mobility decreases due to high concentration of doping, the structure of the present invention has the advantage that no significant decrease is observed. Therefore, the semiconductor device of the present invention is effective in realizing a device that exhibits stable diode or transistor characteristics in a temperature range up to high temperatures.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の半導体装置の試料(a)(ノンドープ
5000Å、p+ 50Å、5サイクル積層)と試料(
b)(ノンドープ500Å、p+ 50Å、10サイク
ル積層)についてホ−ル測定を行いキャリヤ密度の温度
依存性を求めた結果を示すグラフ。
FIG. 1: Sample (a) of the semiconductor device of the present invention (non-doped 5000 Å, p+ 50 Å, 5-cycle lamination) and sample (
b) A graph showing the results of hole measurements for (non-doped 500 Å, p+ 50 Å, 10-cycle lamination) and the temperature dependence of carrier density.

【図2】本発明の半導体装置の試料(a)(ノンドープ
5000Å、p+ 50Å、5サイクル積層)と試料(
b)(ノンドープ500Å、p+ 50Å、10サイク
ル積層)について比抵抗の温度依存性を求めた結果を示
すグラフ。
FIG. 2: Sample (a) of the semiconductor device of the present invention (non-doped 5000 Å, p+ 50 Å, 5-cycle lamination) and sample (
Graph showing the results of determining the temperature dependence of resistivity for b) (non-doped 500 Å, p+ 50 Å, 10-cycle lamination).

【図3】本発明の実施例3に係る高濃度ド−プ線膜を有
するダイヤモンド半導体試料を作製するための工程を説
明する図。
FIG. 3 is a diagram illustrating a process for producing a diamond semiconductor sample having a highly doped line film according to Example 3 of the present invention.

【図4】本発明の実施例3に係る試料のキャリヤ濃度の
温度依存性を測定した結果を示すグラフ。
FIG. 4 is a graph showing the results of measuring the temperature dependence of the carrier concentration of a sample according to Example 3 of the present invention.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】  ド−ピングレベルが深く室温では飽和
領域にないド−パントを有しているダイヤモンド半導体
であって、該ド−パントを多量にド−ピングした2次元
的な広がりを持つ高ド−プ半導体層と、ノンド−プ層あ
るいは低ド−プ層とを交互に積層し全体として所望のキ
ャリヤ濃度にしてあることを特徴とする半導体装置。
1. A diamond semiconductor having a deep doping level and a dopant that is not in the saturation region at room temperature, which is a diamond semiconductor having a two-dimensional spread and doped with a large amount of the dopant. 1. A semiconductor device characterized in that doped semiconductor layers and non-doped or lightly doped layers are alternately laminated to provide a desired carrier concentration as a whole.
【請求項2】  ド−ピングレベルが深く室温では飽和
領域にないド−パントを有しているダイヤモンド半導体
であって、該ド−パントを多量にド−ピングした多数の
平行な高ド−プ半導体線膜と、この高ド−プ半導体線膜
を1次元的に閉じ込めるノンド−プ層あるいは低ド−プ
層とよりなり全体として所望のキャリヤ濃度にしてある
ことを特徴とする半導体装置。
2. A diamond semiconductor having a dopant having a deep doping level and not in the saturation region at room temperature, comprising a large number of parallel highly doped semiconductors heavily doped with the dopant. 1. A semiconductor device comprising a semiconductor line film and a non-doped layer or a lightly doped layer that one-dimensionally confines the highly doped semiconductor line film, and has a desired carrier concentration as a whole.
【請求項3】  高ド−プ半導体層、高ド−プ半導体線
膜のド−パント濃度が1019cm−3以上であり、ノ
ド−プ層あるいは低ド−プ層のド−パント濃度が101
7cm−3以下であることを特徴とする請求項1或は2
に記載の半導体装置。
3. The dopant concentration of the highly doped semiconductor layer or the highly doped semiconductor line film is 1019 cm-3 or more, and the dopant concentration of the no-doped layer or the lightly doped layer is 101 cm-3 or more.
Claim 1 or 2, characterized in that it is 7 cm-3 or less.
The semiconductor device described in .
【請求項4】  前記ド−ピングレベルが0.1eV以
上であることを特徴とする請求項1〜3のいずれかに記
載の半導体装置。
4. The semiconductor device according to claim 1, wherein the doping level is 0.1 eV or more.
JP3068838A 1991-03-08 1991-03-08 Semiconductor device Expired - Fee Related JP2985337B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3068838A JP2985337B2 (en) 1991-03-08 1991-03-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3068838A JP2985337B2 (en) 1991-03-08 1991-03-08 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH04280622A true JPH04280622A (en) 1992-10-06
JP2985337B2 JP2985337B2 (en) 1999-11-29

Family

ID=13385238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3068838A Expired - Fee Related JP2985337B2 (en) 1991-03-08 1991-03-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2985337B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670796A (en) * 1993-09-24 1997-09-23 Sumitomo Electric Industries, Ltd. Semiconductor device consisting of a semiconductor material having a deep impurity level
JP2012051768A (en) * 2010-09-02 2012-03-15 Toshimichi Ito Diamond semiconductor
CN109585643A (en) * 2017-09-28 2019-04-05 罗伯特·博世有限公司 Layer complex and its manufacturing method and equipment for electrostatically-doped two-dimentional doped layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5670796A (en) * 1993-09-24 1997-09-23 Sumitomo Electric Industries, Ltd. Semiconductor device consisting of a semiconductor material having a deep impurity level
JP2012051768A (en) * 2010-09-02 2012-03-15 Toshimichi Ito Diamond semiconductor
CN109585643A (en) * 2017-09-28 2019-04-05 罗伯特·博世有限公司 Layer complex and its manufacturing method and equipment for electrostatically-doped two-dimentional doped layer

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