JPH04280458A - Semiconductor integrated circuit device, and its manufacture and mounting structure - Google Patents

Abstract

PURPOSE:To provide an LSI package wherein the reliability on the connection during mounting on a board is high and which is suitable for multipin and high-density mounting. CONSTITUTION:This semiconductor integrated circuit device has such a package structure that the chip 4 is encapsulated in the package body 1 consisting of the rubber-shaped elastic body having a projection 2 at the surface, that one end of the lead wiring 3 made on the surface of the sand package body 1 is connected to the pad 7 of the said chip 4 through the connection hole 5 opened in the said package body 1, and that the other end of the said lead wiring 3 is extended to the apex of the said projection.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a package for sealing a semiconductor chip and a technique effective for mounting the package.

0002

[Prior Art] In recent years, memory LS such as RAM, ROM, etc.
As the area of semiconductor chips has increased significantly with the increase in memory capacity, chips have been
ll OutlinePackage), SOJ(S
mall Outline J-lead packa
ge) and other surface-mount packages, and by making these packages thinner and smaller, the packaging density is improved.

On the other hand, as logic LSIs such as gate arrays and microcomputers become more multifunctional and faster, the number of external terminals (input/output terminals, power supply terminals) increases significantly (increasing the number of pins). Therefore, QFP (Quad Fla
By making the package thinner, such as t Package), we aim to improve the packaging density.

[0004] As a logic LSI implementation method, the above-mentioned QF
In addition to P, a flip-chip method is known in which a chip is mounted on a substrate via a CCB bump bonded to the top layer wiring of the chip. Regarding this flip-chip method, for example, published by IBM, "IBM Journal of Research and Development, Volume 13, No. 3 (
IBM Journal of Research an
d Development, Vol. 13, No
．． 3)” is described on pages 239 to 250.

[0005] Also, as a mounting method for multi-pin LSI,
TAB (Tape Automated Bondin)
g) The method is known. This TAB method electrically connects an Au bump formed on a bonding pad of a chip via a barrier metal with one end of a Cu lead formed on an insulating film such as polyimide resin, and This is a mounting method in which the other end is electrically connected to the mounting board. In addition,
Regarding the TAB method, for example, Japanese Patent Application Laid-Open No. 62-20564
There is a description in Publication No. 8.

[0006]

[Problem to be solved by the invention] However, the above S
Surface mount packages such as OP, SOJ, QFP, etc.
Since the chip and the board are electrically connected through outer leads protruding outside the package body, there is a problem in that the packaging density is reduced by the area occupied by the outer leads. Furthermore, in order to prevent the leads from coming off from the package, it is necessary to ensure a certain length of the inner leads within the package, which is also a factor in reducing the packaging density.

Furthermore, since surface mount packages employ a wire bonding method in which chips and leads are connected via wires, there are limits to how the package can be made thinner, smaller, and have more pins. Furthermore, when the package body is made thinner, reliability degradation due to heat during mounting, such as cracks during reflow soldering, becomes a serious problem.

On the other hand, the flip-chip method can easily achieve a higher number of chip pins and higher density mounting than a surface mount package, but on the other hand, stress due to the difference in thermal expansion coefficient between the chip and the substrate is Since the structure is susceptible to damage, there are problems with connection reliability, such as breakage of CCB bumps and cracking of chips.

[0009] Also, regarding the TAB method, the S
Similar to surface mount packages such as OP, SOJ, and QFP, there is a problem in that the packaging density is reduced by the area occupied by the outer leads.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can improve the packaging density of chips.

Another object of the present invention is to provide a technique that allows a chip to have a large number of pins.

Another object of the present invention is to provide a technique that can improve the connection reliability between a chip and a substrate.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0014]

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention provides a plurality of protrusions made of a rubber-like elastic material on the main surface of a chip on which a plurality of circuit elements are formed, and leads formed on the main surface of the chip. It has a structure in which one end of the wiring is connected to a pad on the main surface of the chip, and the other end extends to the top of the protrusion.

[0015] Furthermore, in the semiconductor integrated circuit device,
It has a structure in which at least one of a pad and a protrusion is placed on a circuit element.

[0016]

[Operation] According to the above means, the chip and the board are electrically connected through the lead wiring formed on the surface of the package body, and the chip and the board are electrically connected through the leads protruding outside the package body. Packaging density can be improved compared to conventional surface mount packages that take more space.

According to the above-mentioned means, since the protrusion is made of a rubber-like elastic material, the stress caused by the difference in coefficient of thermal expansion between the chip and the substrate is absorbed and alleviated by the protrusion.
The reliability of the connection between the chip and the board is improved, and cracks in the package body and chip due to heat during soldering are prevented.

According to the above-mentioned means, the lead wires and the pads of the chip are directly connected through the connection holes formed in the package body, so that the package is more compact than the wire bonding method in which the chip and the leads are connected via wires. It becomes easier to make the device thinner and smaller.

According to the above-mentioned means, by arranging a pad on the circuit element and connecting one end of the lead wiring to this pad, the wiring length inside the chip can be shortened, which is suitable for high-speed LSI. package can be provided. Furthermore, the chip can be made smaller by the area in which the pads are formed.

According to the above-described means, by arranging the protrusions on the circuit elements, a semiconductor integrated circuit device having approximately the same dimensions as the chip can be obtained, so that the packaging density of the chips can be improved.

[0021] The present invention will be explained below with reference to Examples. In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0022]

Embodiment FIG. 3 is a perspective view of a semiconductor integrated circuit device according to this embodiment, FIG. 4 is a front view of the semiconductor integrated circuit device in the long side direction, and FIG. 5 is a front view of the semiconductor integrated circuit device in the short side direction.

The package body 1 of this semiconductor integrated circuit device is made of a rubber-like elastic body, and a predetermined number of protrusions 2 are arranged at regular intervals along the shorter side at both ends of the lower surface. These protrusions 2 are made of a rubber-like elastic body made of the same material as the package body 1, and are integrally molded with the package body 1.

One end of a lead wire 3 constituting an external terminal (input/output terminal and power supply terminal) of this semiconductor integrated circuit device extends to the top of each of the projections 2. The other end of the lead wire 3 extends toward the center of the lower surface of the package body 1 via the side wall of the protrusion 2 . The lead wiring 3 is made of a composite metal film including, for example, a lower layer of a deposited Cu film, an intermediate layer of a Cu plating film, and a surface of an Au plating film.

[0025] Inside the package body 1, there are
In FIG. 5, a semiconductor chip 4 (not shown) is sealed. The chip 4 is made of a silicon single crystal on which a memory LSI such as a DRAM or SRAM is formed, and is sealed with its main surface (circuit element surface) facing the surface on which the protrusions 2 of the package body 1 are formed. .

FIG. 1 is a cutaway perspective view showing an enlarged end portion of the lower surface of the package body 1, and FIG. 2 is a sectional view thereof.

[0027] The protrusion 2 provided on the package body 1 is
For example, the top part is rectangular, and the package body 1 has a truncated pyramid shape with an inclined side wall on the center side, and the length of the short side of the top part is, for example, about 200 μm, and the gap between adjacent protrusions 2, 2. is, for example, about 300 μm. That is, the protrusions 2 are arranged along the short side direction of the package body 1 at a pitch of about 500 μm.

Connection holes 5 are formed in the package body 1 near each of the projections 2, and the lead wires 3 are embedded inside the connection holes 5. Further, at the bottom of the connection hole 5, a pad 7 formed by opening a surface protection film (passivation film) 6 of the chip 4 is exposed, so that the pad 7 and the lead wiring 3 are electrically connected. It is connected to the. The pad 7 is made of Al wiring 8 connected to the circuit elements of the chip 4. Further, the main surface of the chip 4 is covered with a rubber-like elastic body made of the same material as the protrusion 2, and the main surface of the chip 4 is protected by this rubber-like elastic body.

As described above, in the semiconductor integrated circuit device of this embodiment, one end of the lead wire 3 constituting the external terminal is connected to the protrusion 2 provided on the lower surface of the package body 1 made of a rubber-like elastic material.
The other end of the lead wire 3 is connected to the pad 7 of the chip 4 through a connection hole 5 formed in the package body 1.

FIG. 6 is a sectional view of the vicinity of the pad 7. For example, on the main surface of the chip 4 made of p-type silicon single crystal, a resistor R, an n-channel MISFET Q1, a p
Circuit elements such as a channel type MISFETQ2 are formed. The above resistance R, n-channel MISFET Q1
and p-channel type MISFET Q2 constitute, for example, an input circuit of a memory LSI.

The resistance R is, for example, an n-type semiconductor region 9a.
Consisting of In addition, the n-channel MISFETQ1 is
A pair of n-type semiconductor regions 9b forming a source and a drain
and a gate electrode 10 made of polycrystalline silicon or the like, and the p-channel type MISFET Q2 consists of a pair of p-type semiconductor regions 11 forming a source and a drain, and a gate electrode 10. The resistor R and the pair of n-type semiconductor regions 9b of the n-channel MISFET Q1 are as follows:
A pair of p-type semiconductor regions 11 of the p-channel MISFETQ2 are formed on the main surface of p-type silicon, respectively, and are formed on the main surface of p-type silicon.
It is formed on the main surface of the shaped well 12.

A pair of Al wirings 8, 8 are connected to the resistor R through a connection hole 14 formed in the insulating film 13. One of the pair of Al wirings 8, 8 is connected to the input signal lead wiring 3 through the pad 7 and the connection hole 5, and the other Al wiring 8 is connected to the n-channel type M
ISFETQ1 and p-channel MISFETQ2
are connected to respective gate electrodes 10 of. That is, the lead wiring 3 is connected to the input circuit of the memory LSI through the connection hole 5, the pad 7, the Al wiring 8, and the resistor R.

Next, an example of a method for manufacturing the semiconductor integrated circuit device of this embodiment will be explained with reference to FIGS. 7 to 10.

First, as shown in FIG. 7, the chip 4 is sealed with a package body 1 made of rubber-like elastic material. The chip 4 is sealed by, for example, injection molding. As the rubber-like elastic body, for example, silicone rubber etc. has an elastic modulus of 100 MP.
Use one with a soft composition of A or less. The package body 1 is thicker at both ends than at the center, and the thickness of the thicker portions is, for example, about 1 mm. Further, a step portion between the thick portion and the center portion of the package body 1 is provided with an inclination.

Next, as shown in FIG. 8, a part of the package body 1 is opened to form a connection hole 5 that reaches the pad 7 of the chip 4. Subsequently, as shown in FIG. 9, a metal film 15 for lead wiring is deposited on the surface of the package body 1, and the metal film 15 is buried inside the connection hole 5 to connect the pad 7 of the chip 4 and the metal film 15. electrically connect the Metal film 15
is deposited so as to cover at least the area from both ends of the package body 1 to the connection hole 5. Since the stepped portion between the thick portion and the central portion of the package body 1 is sloped, the coverage of the metal film 15 does not deteriorate at this stepped portion.

The metal film 15 is, for example, a deposited Cu film with a thickness of about 1 μm, a plated Cu film with a thickness of about 10 μm,
It consists of a composite metal film in which Au plating films with a thickness of about 1 to 2 μm are sequentially deposited. The deposited Cu film serves as an electrode when depositing a Cu plating film by electroplating. The Cu plating film is for improving solder wettability when the package body 1 is soldered to the board, and the Au plating film is for preventing corrosion of the Cu plating film. . Note that a solder plating film may be used instead of the Au plating film.

Next, by machining such as dicing, a cut 16 as shown in FIG. 10 is made from the end of the package body 1 toward the center to form the protrusion 2 and the lead wiring 3. The example semiconductor integrated circuit device is completed.

FIG. 11 shows the semiconductor integrated circuit device of this embodiment mounted on a substrate 17. As shown in FIG. The substrate 17 is
For example, it is made of synthetic resin such as epoxy resin or polyimide resin, and has an electrode 18 made of Cu on its main surface. In order to mount the semiconductor integrated circuit device of this embodiment on this substrate 17, the solder reflow method is used as in the case of surface mount packages such as SOP and SOJ. That is, the substrate 17
After printing a cream-like solder 19 on the electrode 18, the top of the protrusion 2 of the package body 1 is positioned on the electrode 18, and the solder 19 is heated to above its melting point using infrared rays or the like.

In the semiconductor integrated circuit device described above, the protrusions 2 are arranged along the short side direction of the package body 1, but the protrusions 2 can also be arranged along the long side direction of the package body 1. Whether the protrusions 2 are arranged along the short side direction or the long side direction of the package body 1 depends on SO.
As with surface mount packages such as P and SOJ,
It is determined by the arrangement of the pads 7 of the chip 4 sealed in the package body 1.

As described above, according to this embodiment, the following effects can be obtained.

(1). Since the chip 4 and the substrate 17 are electrically connected through the lead wiring 3 formed on the surface of the package body 1, the chip 4 and the substrate 17 are electrically connected through the leads protruding outside the package body. Packaging density can be improved compared to surface mount packages.

(2). Since the package body 1 and the protrusions 2 are made of rubber-like elastic material, the chip 4 and the substrate 1
The stress due to the difference in thermal expansion coefficient between package body 1 and
and the protrusions 2 absorb and relax, so the chip 4 and the substrate 1
The reliability of the connection with 7 is improved.

Furthermore, it is also possible to prevent cracks in the package body 1 and the chip 4 caused by heat during soldering.

(3). By directly connecting the lead wiring 3 and the pad 7 of the chip 4 through the connection hole 5 formed in the package body 1, the package is thinner than the conventional wire bonding method, which connects the chip and the leads via wire. It can be made smaller and smaller.

FIG. 12 is a sectional view of the end of the package body 1 showing another embodiment of the semiconductor integrated circuit device of the present invention.

In the above embodiment, the package body 1 and the protrusion 2 are
This embodiment has a structure in which conductive protrusions 2 made of a rubber-like elastic body are connected to a package body 1 made of a rubber-like elastic body. It has become. The conductive protrusion 2 is adhered to the package body 1 via, for example, a conductive adhesive 20, thereby electrically connecting the lead wiring 3 formed on the surface of the package body 1 and the protrusion 2. In addition, the above protrusion 2
In this case, there is no need to provide an inclination to the side wall on the center side of the package body 1.

To mount the semiconductor integrated circuit device provided with the conductive protrusions 2 on a substrate, for example, a conductive adhesive is used. That is, after printing a conductive adhesive on the electrode of the substrate or the top of the protrusion 2, the top of the protrusion 2 is aligned on the electrode, and the conductive adhesive is cured by heating.

FIG. 13 is a perspective view of a package body 1 showing still another embodiment of the semiconductor integrated circuit device of the present invention.

In the above embodiment, the chip 4 on which a memory LSI was formed was sealed in the package body 1, but in this embodiment, a chip on which a logic LSI such as a gate array was formed was sealed in the package body 1. . In this case, by arranging the protrusions 2 along the four sides of the package body 1,
Like QFP, a multi-pin package can be provided.

Furthermore, according to the present invention, as shown in FIG. 14, the protrusions 2 and the wiring 3 can be formed not only at the ends of the package body 1 but also at its center.
It is possible to provide a package with even more pins than an FP. In this case, the pad 7 of the chip 4 is placed directly above the circuit element, the connection hole 5 is provided on the pad 7, and a projection is provided in the connection hole 5.

Furthermore, in this case, the internal wiring length of the chip 4 is shorter than in the case where the pads 7 are arranged at the periphery of the chip 4, so that a package suitable for high-speed LSI can be provided. In the present invention, the lead wires 3 are connected to the pads 7 of the chip 4 through the connection holes 5 formed in the package body 1, so even when the pads 7 are placed directly above the circuit elements, it is possible to There is no risk that the circuit elements directly under the pad will deteriorate due to shock loads or ultrasonic vibrations.

FIG. 15 is a front view in the long side direction of a package body 1 showing still another embodiment of the semiconductor integrated circuit device of the present invention, and FIG. 16 is a sectional view of a main part of this package body 1. .

In this embodiment, a second layer of Al wiring 21 is formed above the Al wiring 8, and the pads 7 are arranged on the circuit elements by multilayering the wiring. Additionally, along with this, a protrusion 2 is also arranged on the circuit element.

According to this embodiment, by arranging the pads 7 on the circuit elements, the pad area can be reduced, so that the chip 4 can be made smaller. Also,
By arranging the protrusion 2 on the circuit element, the outer diameter of the package body 1 can be reduced to approximately the same level as the outer diameter of the chip 4, so the packaging density of the chip 4 can be further improved. .

[0055] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

For example, the shape of the protrusion is not limited to the shape of the above embodiment. Furthermore, the rubber-like elastic bodies forming the package body and the protrusions are not limited to silicone rubber or the like.

[0057]

[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions will be briefly explained as follows.
It is as follows.

(1). Since the chip and the board are electrically connected through the lead wiring formed on the surface of the package body, it is different from the conventional surface mount package where the chip and the board are electrically connected through the leads that protrude outside the package body. It is possible to improve the packaging density.

(2). Since the package body and protrusions are made of rubber-like elastic material, the stress caused by the difference in thermal expansion coefficient between the chip and the substrate is absorbed and alleviated by the package body and the protrusions, improving the connection reliability between the chip and the substrate. improves. Furthermore, it is possible to prevent cracks in the package body and chip caused by heat during soldering.

(3). By directly connecting the lead wiring and the pads of the chip through the connection holes in the package body, it is easier to make the package thinner and smaller than with the wire bonding method, which connects the chip and leads via wire. Become.

(4). By arranging the pad directly above the circuit element and connecting one end of the lead wire to this pad, the length of the wire inside the chip can be shortened, so that a package suitable for high-speed LSI can be provided.

(5). By providing a connection hole on a pad placed directly above a circuit element and providing a protrusion near the connection hole, it becomes easy to increase the number of pins in the package.

[Brief explanation of the drawing]

FIG. 1 is a cutaway perspective view showing an enlarged main part of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing an enlarged main part of the semiconductor integrated circuit device.

FIG. 3 is a perspective view of this semiconductor integrated circuit device.

FIG. 4 is a front view of the semiconductor integrated circuit device in the long side direction.

FIG. 5 is a front view of the semiconductor integrated circuit device in the short side direction.

FIG. 6 is a partial cross-sectional view of this semiconductor integrated circuit device.

FIG. 7 is a perspective view showing a part of the method for manufacturing the semiconductor integrated circuit device.

FIG. 8 is a perspective view showing a part of the method for manufacturing the semiconductor integrated circuit device.

FIG. 9 is a perspective view showing a part of the method for manufacturing the semiconductor integrated circuit device.

FIG. 10 is a perspective view showing a part of the method for manufacturing the semiconductor integrated circuit device.

FIG. 11 is a front view showing the mounting structure of this semiconductor integrated circuit device.

FIG. 12 is a cross-sectional view showing an enlarged main part of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 13 is a perspective view of a semiconductor integrated circuit device which is still another embodiment of the present invention.

FIG. 14 is a front view in the long side direction of a semiconductor integrated circuit device that is still another embodiment of the present invention.

FIG. 15 is a front view in the long side direction of a semiconductor integrated circuit device which is still another embodiment of the present invention.

FIG. 16 is a cross-sectional view showing an enlarged main part of this semiconductor integrated circuit device.

[Explanation of symbols]

1　Package body 2.Protrusion 3 Lead wiring 4 Semiconductor chip 5 Connection hole 6 Surface protection film (passivation film) 7 Pad 8 Al wiring 9a N-type semiconductor region 9b N-type semiconductor region 10 Gate electrode 11 p-type semiconductor region 12 N-type well 13 Insulating film 14 Connection hole 15 Metal film 16 Notch 17 Board 18 Electrode 19 Solder 20 Conductive adhesive 21 Al wiring Q1 n-channel MISFET Q2 p-channel MISFET R resistance

Claims (9)

[Claims] 1. A semiconductor chip having a plurality of circuit elements formed on its main surface, a protrusion made of a rubber-like elastic body provided on the main surface of the semiconductor chip, and a protrusion formed on the main surface of the semiconductor chip. A semiconductor integrated circuit device comprising a lead wire having one end connected to a pad of the semiconductor chip and the other end extending to the top of the protrusion. 2. The elastic modulus of the rubber-like elastic body is 100
Claim 1 characterized in that the pressure is MPa or less.
The semiconductor integrated circuit device described above. 3. The semiconductor integrated circuit device according to claim 1, wherein the protrusion is provided on a circuit element. 4. The semiconductor integrated circuit device according to claim 1, wherein the pad is provided on a circuit element. 5. A semiconductor chip is sealed in a package body made of a rubber-like elastic material, and one end of a lead wire formed on the surface of the package body is connected to a pad of the semiconductor chip through a connection hole formed in the package body. and the other end of the lead wiring is connected to a conductive protrusion made of a rubber-like elastic body provided on the surface of the package body. 6. A step of sealing a semiconductor chip in a package body made of a rubber-like elastic body with protrusions on the surface;
a step of opening a part of the package body to form a connection hole reaching a pad of the semiconductor chip; a step of depositing a conductive film for lead wiring on the surface of the package body; and a step of forming the package body and its surface. forming a lead wiring whose one end is connected to the pad of the semiconductor chip through the connection hole and whose other end extends to the top of the protrusion by forming a predetermined number of cuts in the conductive film. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, 2, 3, or 4. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein a sloped portion is provided on a side wall of the protrusion. 8. The lead wiring on the top of the protrusion and the electrode on the substrate are connected by solder.
A mounting structure for a semiconductor integrated circuit device according to , 2, 3 or 4. 9. The mounting structure for a semiconductor integrated circuit device according to claim 5, wherein the conductive protrusion made of the rubber-like elastic body and the electrode of the substrate are connected by a conductive adhesive.