JPH04280327A - Microprocessor - Google Patents

Abstract

PURPOSE:To offer a micro processor which can measure the internal processing performance of the microprocessor from an external part. CONSTITUTION:An information storage part 4 analyzing a prescribed input instruction inputted through an external bus 8 and storing processing information based on an analysis result, an instruction analysis means 2 fetching necessary information from an external memory 7 and outputting various control signals and an operation means 3 executing an operation based on information concerned by the control signals from the instruction analysis means 2 are provided. The various control signals of the instruction analysis means 2 are outputted to the external part.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor whose internal processing performance can be easily measured.

[0002] In recent years, the performance of microprocessors has been increasing, and some have built-in large-capacity cache memories, and others have large memory spaces by increasing the number of address signals output from the microprocessors. has appeared.

[0003] Such microprocessors are configured so that users can use them without being aware of the existence of cache memory or vast memory space within the processor. Regarding space, the amount of memory that can actually be implemented in the total memory space of a microprocessor is generally small, and in order to use this memory without the programmer being aware of it, there are devices that have a logical/physical address translation mechanism. When creating a microprocessor, the capacity of the built-in cache memory and the configuration of the address translation mechanism are determined by estimating the actual performance to some extent, for example, through simulation.

However, as mentioned above, microprocessors are constructed in such a way that the existence of built-in cache memory and address translation mechanism is not directly visible from the outside.
When an LSI equipped with a microprocessor is actually used, it is difficult to measure the performance of each function of the microprocessor.

Therefore, the internal processing performance of the microprocessor is measured in order to confirm whether the performance estimated at the time of creation is actually obtained and to measure and collect data in order to consider more advanced configurations. It is necessary to do so.

[0006]

2. Description of the Related Art A conventional microprocessor of this type is shown in FIG. 3, for example. FIG. 3 is a block diagram showing the overall configuration of the conventional microprocessor.

[0007] This microprocessor 1 can be roughly divided into:
It is comprised of an instruction analysis processing circuit 2 which is an instruction analysis means, an arithmetic processing circuit 3 which is an arithmetic means, a built-in cache memory 4 which is an information storage section, and a bus operation control circuit 5.

Note that 6 is an external circuit for monitoring bus operation, 7 is an external memory which is one of the information storage units, 8 is an external bus, and ■ is an instruction sent from the instruction analysis processing circuit 2 to the built-in cache memory 4. Request signal, ■ is a registration/unregistration response signal from the built-in cache memory 4 to the instruction analysis processing circuit 2, ■ is an operation request signal from the instruction analysis processing circuit 2 to the bus operation control circuit 5, and ■ is the bus operation control circuit 5. The external access operation signal 2 is a processing request signal sent from the instruction analysis processing circuit 2 to the arithmetic processing circuit 3.

FIG. 4 is a waveform diagram for explaining an operation example of the conventional example, and in the figure, CLOCK is the microprocessor 1.
A0 to A31 are the access address signals output by the microprocessor 1, BS is the STROBE signal indicating that the microprocessor 1 has started an external access, and SDC is the input clock supplied to the microprocessor 1.
D0 to D31 indicate input signals indicating access completion, and D0 to D31 indicate data signals input and output to the microprocessor 1.

In the above configuration, first, when a predetermined instruction is input via the external bus 8, the instruction is analyzed by the instruction analysis processing circuit 2, and based on the analyzed instruction, the instruction analysis processing circuit 2 An instruction request signal ■ is outputted onto the cache memory 4, and it is searched whether the built-in cache memory 4 has an instruction to be executed.

As a result of the search, a registered/unregistered response signal ■ is output from the built-in cache memory 4 to the instruction analysis processing circuit 2, and if the above-mentioned instruction does not exist in the built-in cache memory 4, it is fetched from the external memory 7. Therefore, the instruction analysis processing circuit 2 to the bus operation control circuit 5
An operation request signal (2) is output to the bus operation control circuit 5, and an operation request is made to the bus operation control circuit 5.

Next, the bus operation control circuit 5 outputs the external access operation signal (2), and the requested instruction on the external memory 7 is fetched, passed to the instruction analysis processing circuit 2, and registered in the built-in cache memory 4. be done.

Then, a processing request signal (2) is output from the instruction analysis processing circuit 2 to the arithmetic processing circuit 3, and the arithmetic processing circuit 3 executes the arithmetic operation.

That is, the instructions or data fetched from the external memory 7 are first registered on the built-in cache memory 4, and the internal processing of the microprocessor 1 is performed as follows.
This is done using the information on the built-in cache memory 4.

[0015] The access up to this point is based on the external bus 8.
Since this can be seen as the above memory access, it can be monitored by the external bus operation monitoring circuit 6.

[0016]

[Problems to be Solved by the Invention] However, in such a conventional microprocessor 1, for example,
If it becomes necessary to access again the instruction previously registered in the internal cache memory 4 due to a loop instruction or the like, the external memory 7 will not be accessed since it has already been registered in the internal cache memory 4. Therefore, as shown in FIG. 4, information once accessed to the external memory 7 does not appear outside the microprocessor 1, such as a change signal indicating a fetch operation, and is used for bus operation monitoring. There was a problem in that the instruction execution performance of the microprocessor 1 could not be measured using the external circuit 6.

In addition to the built-in cache memory, the microprocessor 1 which has an address translation mechanism for a table storing translated pairs of logical and physical addresses has a table for translation on the external memory 7, and When converting to , the table is accessed, but from the second time onwards, similar to the cache memory described above, access operations of the conversion table for addresses that have already been registered do not appear externally, so the conversion vs. registration buffer There was a problem in that it was not possible to measure the rate of improvement in processing performance.

[Objective] Accordingly, it is an object of the present invention to provide a microprocessor whose internal processing performance can be measured from the outside.

[0019]

[Means for Solving the Problems] In order to achieve the above object, a microprocessor according to the present invention analyzes a predetermined input command input via an external bus 8, and stores processing information based on the analysis result. a command analysis means 2 that takes in necessary information from the sections 4 and 7 and outputs various control signals;
The apparatus includes a calculation means 3 that performs calculations based on the information in response to control signals from the command analysis means 2, and is configured to output the various control signals of the command analysis means 2 to the outside.

In this case, the information storage section is a built-in cache memory, and the various control signals are an instruction fetch transfer signal, an operand read transfer signal, an operand store transfer signal, and an instruction completion signal for the built-in cache memory. Furthermore, it is conceivable that the information storage section is an address translation mechanism for a table that converts logical address information into physical address information, and that the various control signals are access signals for the address translation mechanism for the table.

[0021]

[Operation] In the present invention, various control signals of the instruction analysis means, such as an instruction fetch transfer signal, an operand read transfer signal, an operand store transfer signal, and an instruction completion signal, are output to the outside of the microprocessor, and The internal processing state of the microprocessor is referenced from the outside, such as when instructions and data are supplied from the microprocessor.

That is, the internal processing performance of the microprocessor can be measured.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. 1 and 2 are diagrams showing one embodiment of a microprocessor according to the present invention, and FIG. 1 is a block diagram showing the overall configuration of the microprocessor of this embodiment.

First, the configuration will be explained.

In FIG. 1, the same numbers as those given to the conventional example shown in FIG. 3 indicate the same parts. The microprocessor 1 of the present embodiment outputs control signals such as request commands, operand requests, command completion, etc. from the command analysis unit to the bus operation control circuit 5 from the command analysis processing circuit 2, which is a command analysis means. It is configured as follows.

FIG. 2 is a waveform diagram for explaining an example of the operation of this embodiment, and the signals shown in the conventional example of FIG. Command request, data request, and command completion corresponding to signal ■ have been added.

Note that the instruction request is an instruction request that the instruction analysis processing circuit 2 requests to the built-in cache memory 4, and the data request is a data request that the instruction analysis processing circuit 2 requests to the built-in cache memory 4. Completion is an instruction operation completion signal output by the instruction analysis processing circuit 2.

In the above configuration, first, when a predetermined instruction is input via the external bus 8, the instruction is analyzed by the instruction analysis processing circuit 2, and an instruction request signal is sent from the instruction analysis processing circuit 2 onto the built-in cache memory 4. A registered/unregistered response signal ■ is outputted from the built-in cache memory 4 to the instruction analysis processing circuit 2 as a response to determine whether the instruction to be executed is in the built-in cache memory 4.

If the above-mentioned instruction does not exist on the built-in cache memory 4, the instruction analysis processing circuit 2 outputs an operation request signal ■ to the bus operation control circuit 5, and the bus operation control circuit 5 outputs an external access operation signal ■. The requested instruction on the external memory 7 is fetched and passed to the instruction analysis processing circuit 2, and is also sent to the built-in cache memory 4.
will be registered.

The above operation is similar to that of the conventional example, and the processing request signal (2) is outputted from the instruction analysis processing circuit 2 to the arithmetic processing circuit 3, and the arithmetic processing circuit 3 executes the arithmetic operation. Here, if the above-mentioned instruction exists on the built-in cache memory 4, the instruction (or data) fetched from the external memory 7 is registered on the built-in cache memory,
Hereinafter, the information in this built-in cache memory 4 will be used for processing inside the microprocessor 1.

In this case, the instruction analysis processing circuit 2 sends a command request which is a signal indicating that it requests an instruction, a data request which is a signal which indicates that it requests data, and a signal which indicates that one instruction has been completed. Since the completion of a certain instruction is output as an external signal to the external bus 8, the processing status of the instruction and data can be known even without a fetch operation to the external memory 7 via the external bus 8.

That is, L including the microprocessor 1
It becomes possible to measure the internal processing performance, etc. of the entire SI. In this way, in this embodiment, various control signals of the instruction analysis means, such as an instruction fetch transfer signal, an operand read transfer signal, an operand store transfer signal, and an instruction completion signal, can be output to the external bus. For example, the internal processing state of the microprocessor can be output when instructions and data are supplied from the built-in cache memory.

Therefore, it is possible to easily measure internal processing performance, etc., which has been difficult to measure in the past, and it is also possible to easily collect performance data of the microprocessor and data for determining the processing method.

[0034] Although the above embodiment has been described using an example of a microprocessor using an external memory and a built-in cache memory as an information storage section, the present invention is not limited to this. The same is true for a microprocessor having a conversion/registration buffer), and by outputting access information to the conversion/registration buffer as an external signal, information such as the processing performance improvement rate due to the conversion/registration buffer can be measured, for example.

[0035]

According to the present invention, various control signals of the instruction analysis means, such as an instruction fetch transfer signal, an operand read transfer signal, an operand store transfer signal, and an instruction completion signal, can be output to an external bus. For example, the internal processing state of the microprocessor can be output when instructions and data are supplied from the built-in cache memory.

Therefore, the internal processing performance of the microprocessor can be measured, and data for evaluating the performance of the microprocessor can be collected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining an example of operation of an embodiment of the present invention.

FIG. 3 is a block diagram showing the overall configuration of a conventional microprocessor.

FIG. 4 is a waveform diagram for explaining an operation example of a conventional example.

[Explanation of symbols]

1 Microprocessor 2 Instruction analysis processing circuit (instruction analysis means) 3
Arithmetic processing circuit (arithmetic means) 4 Built-in cache memory (information storage section) 5
Bus operation control circuit 6 External circuit for bus operation monitoring 7 External memory (information storage section) 8 External bus

Claims (3)

[Claims] 1. Command analysis means that analyzes a predetermined input command input via an external bus, takes in necessary information from an information storage unit that stores processing information based on the analysis result, and outputs various control signals. and an arithmetic means that performs an arithmetic operation based on the information using a control signal from the instruction analysis means;
A microprocessor, characterized in that the microprocessor is configured to output the various control signals of the instruction analysis means to the outside. 2. The information storage section is a built-in cache memory, and the various control signals are an instruction fetch transfer signal, an operand read transfer signal, an operand store transfer signal, and an instruction completion signal for the built-in cache memory. The microprocessor according to claim 1, characterized in that: 3. The information storage unit is an address translation mechanism for a table that converts logical address information into physical address information, and the various control signals are access signals for the address translation mechanism for the table. The microprocessor according to claim 1 or 2.