JPH04277922A - Reset circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a malfunction of a digital circuit when a power supply is applied, i.e., to surely output the initialization state setting signal at an optional, level. CONSTITUTION:Two time constant circuits consisting of the resistances and capacities are inputted to the plus and minus sides of an amplifier 7 respectively. A difference is produced between a time constant receiving the substrate effect and a time constant receiving no substrate effect at each rise when a power supply is applied owing to application of the low density ion injection resistance with which a well is floated. Then the difference of time constants is detected by the amplifier 7. Thus one of time constant circuit can surely output a reset signal to a digital circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit, and more particularly to a reset circuit for an LSI incorporating a digital circuit.

0002

2. Description of the Related Art Generally, when a digital circuit or the like starts operating before the power supply voltage becomes stable when the power is turned on, the internal state becomes uncertain and a meaningless and uncertain signal is output. In order to solve these drawbacks, a reset circuit is used to output a signal for setting the initial state of the digital circuit.

FIG. 3 is a circuit diagram showing an example of a conventional reset circuit. In FIG. 3, a resistor 3 and a capacitor 4 are connected in series between one power supply terminal 1 and the other power supply terminal 2, and their common connection point 9 is inputted to an inverter 11. After applying voltage between power supply terminals 1 and 2, point 9 is connected to inverter 11.
The inverter 11 outputs a reset signal while the threshold voltage is reached. When the voltage exceeds the threshold potential, the output 8 of the inverter 11 is inverted and the reset signal is released. In this way, a signal for setting the initial state of the digital circuit can be obtained.

0004

Such a conventional reset circuit is constructed using an inverter, but the inverter has poor temperature characteristics and cannot maintain a constant threshold potential. Therefore, in a reset circuit configured with an inverter, variations occur in the pulse width of the reset signal. If such a signal is used as a reset signal for a digital circuit, and the pulse width becomes long, the reset release will be delayed and the startup of the entire system will be delayed. In addition, if the pulse width becomes short, the reset function becomes insufficient, resulting in a serious drawback that the system as a whole may malfunction.

SUMMARY OF THE INVENTION An object of the present invention is to provide a reset circuit which solves the above-mentioned drawbacks and prevents variations in the pulse width of a reset signal.

[0006]

[Means for Solving the Problems] The reset circuit of the present invention has a first resistor and a first capacitor connected in series between a first power supply terminal and a second power supply terminal, and a well potential that is floating. A first low-concentration ion-implanted resistor of the same size as the resistor and a second capacitor having the same capacitance value as the first capacitor are connected in series, and the first resistor and the first capacitor are connected in series. The connection point and the connection point between the first low-concentration ion-implanted resistor and the second capacitor with the potential of the well floating are defined as first and second connection points, respectively, and the first and second connection points are used as the second connection point. It is characterized in that it is used as an input of a voltage comparator connected between the first power supply terminal and the second power supply terminal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing a reset circuit according to an embodiment of the present invention.

In FIG. 1, the reset circuit of this embodiment has a first power supply terminal connected between a first power supply terminal 1 and a second power supply terminal 2.
resistor 3 (hereinafter referred to as R1) and first capacitor 4 (hereinafter referred to as C1
) connected in series, a first low-concentration ion implanted resistor 5 (hereinafter referred to as R2) of the same size as the resistor with the potential of the well floating, and a first capacitor having the same capacitance value. A second capacitor 6 (hereinafter referred to as C2) is connected in series, and a connection point 9 between R1 and C1 is connected to the R
The connection point 10 between 2 and C2 is connected to the input of the voltage comparator 7. Further, the first power supply terminal 1 is set to a high potential, and the second power supply terminal 2 is set to a ground potential.

Next, the operation of this embodiment will be explained using FIG. 2. In FIG. 2, waveform A represents the first resistor 3 of the above embodiment.
, the voltage at the connection point 9 of the first capacitor 4, the waveform B is the voltage at the connection point 10 between the first low concentration ion implantation resistor 5 and the second capacitor 6, and the waveform (level) C is the detection voltage of power supply level fluctuation. Show points. Since R2 is not affected by the substrate effect, the potential V at the connection point 10
Like waveform B, C2 rises with the time constant of R2 and C2. R1 is affected by the substrate voltage and the depletion layer expands, which effectively reduces the depth of diffusion and increases the sheet resistance, so the resistance value R1' = αR1 (α is the difference between the substrate voltage and the potential of R1. (rate of change in resistance value of R1 due to potential difference). As shown in waveform A, the potential VC1 at the connection point 9 is R1,
It rises with the time constant of C1, and later becomes the time constant of R1' and C1. Therefore, as shown in FIG. 2, VC1>VC2 later becomes VC1=VC2. This is detected by the voltage comparator 7 and a reset signal can be obtained at the output terminal 8.

According to this embodiment, since the difference in the rise time constants at power-on of two time constant circuits having the same resistance size and the same capacitance value is detected, there is little variation in pulse width with respect to temperature and voltage. , a stable reset signal can be obtained.

[0011]

[Effects of the Invention] As explained above, the present invention detects the difference in the rise time constant when the power is turned on using, for example, an OP amplifier (operational amplifier) and outputs a reset signal, so that the power supply voltage is turned on and stabilized. Until then, it has the effect of reliably outputting a signal for setting a so-called initial state that prevents malfunctions in the digital circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a reset circuit according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing the operation of FIG. 1;

FIG. 3 is a circuit diagram showing a conventional reset circuit.

[Explanation of symbols]

1, 2 Power terminal 3 Resistance 4,6 Capacity 5 Low concentration ion implantation resistance 7 Voltage comparator 8 Output terminal 11 Inverter

Claims (1)

[Claims] 1. A reset circuit in which a voltage comparator is connected between a first power supply terminal and a second power supply terminal, and an output of the voltage comparator is used as a reset signal, wherein the first power supply terminal and the second power supply terminal are connected to each other. A first resistor and a first capacitor connected in series between terminals, a first low-concentration ion implanted resistor of the same size as the resistor with the potential of the well floating, and a capacitance value the same as the first capacitor. A connection point between the first resistor and the first capacitor by connecting a second capacitor connected in series, and a connection point between the first low-concentration ion implantation resistor and the second capacitor with the potential of the well floating. are first and second connection points, and the first and second connection points are connected to an input of the voltage comparator.