JPH04277690A - Surface treatment of printed wiring board - Google Patents
Surface treatment of printed wiring boardInfo
- Publication number
- JPH04277690A JPH04277690A JP3971291A JP3971291A JPH04277690A JP H04277690 A JPH04277690 A JP H04277690A JP 3971291 A JP3971291 A JP 3971291A JP 3971291 A JP3971291 A JP 3971291A JP H04277690 A JPH04277690 A JP H04277690A
- Authority
- JP
- Japan
- Prior art keywords
- copper layer
- printed wiring
- wiring board
- polishing
- dry film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004381 surface treatment Methods 0.000 title claims description 7
- 238000005498 polishing Methods 0.000 claims abstract description 18
- 239000004593 Epoxy Substances 0.000 claims abstract description 6
- 239000011521 glass Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 26
- 229910052802 copper Inorganic materials 0.000 abstract description 24
- 239000010949 copper Substances 0.000 abstract description 24
- 238000005530 etching Methods 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は印刷配線基板の表面処理
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for surface treatment of printed wiring boards.
【０００２】0002
【従来の技術】従来の印刷配線基板は図２（ａ）に示す
ように、表面に銅箔を設けたガラスエポキシ基板２にス
ルーホール９を設け、スルーホール９を含む表面に銅め
っき層を形成する。2. Description of the Related Art As shown in FIG. 2(a), a conventional printed wiring board has through holes 9 formed on a glass epoxy substrate 2 whose surface is coated with copper foil, and a copper plating layer is formed on the surface including the through holes 9. Form.
【０００３】次に、図２（ｂ）に示すように、銅層３の
表面の汚れや錆又は凸部４と凹部４ａからなる起状を除
去し、ドライフィルムと銅層３との安定した密着力を得
るために、印刷配線基板を表面処理する。Next, as shown in FIG. 2(b), dirt and rust on the surface of the copper layer 3 or the irregularities consisting of the protrusions 4 and recesses 4a are removed to stabilize the bond between the dry film and the copper layer 3. The surface of the printed wiring board is treated to improve adhesion.
【０００４】表面処理の方法には、化学的な研磨処理法
と機械的な研磨処理法とがあり、この両者の処理方法は
、処理対象となる印刷配線基板の板厚，銅層の表面状態
により選択されるが、次に銅層３の表面にドライフィル
ム５をラミネートする場合には、銅層３の表面は、中性
である事が必要であるため機械的な研磨処理法が適し、
バフ研磨法、又はベルト研磨法が採られていた。[0004] Surface treatment methods include chemical polishing and mechanical polishing. Both treatment methods depend on the thickness of the printed wiring board to be treated and the surface condition of the copper layer. However, when laminating the dry film 5 on the surface of the copper layer 3, the surface of the copper layer 3 needs to be neutral, so a mechanical polishing method is suitable.
A buffing method or a belt polishing method was used.
【０００５】次に、銅層３の表面にドライフィルム５を
貼付けて印刷配線基板を構成する。Next, a dry film 5 is attached to the surface of the copper layer 3 to form a printed wiring board.
【０００６】[0006]
【発明が解決しようとする課題】従来の印刷配線基板の
表面処理方法は、バフ研磨法では印刷配線基板の銅層３
の表面の凹凸が研磨しきれず平坦な面が得られないため
ドライフィルムをラミネートした場合、図２（ｂ）の凹
部４ａにドライフィルム５と銅層３の表面の間の隙間６
が発生しドライフィルム５を安定密着する事ができず、
配線を形成するための銅層３のパターンニングの際にこ
の隙間６にエッチング液がしみ込み配線の断線や欠損の
原因となっていた。[Problems to be Solved by the Invention] In the conventional surface treatment method for a printed wiring board, the buffing method is used to treat the surface of the printed wiring board.
When the dry film is laminated because the surface irregularities cannot be polished completely and a flat surface cannot be obtained, a gap 6 between the dry film 5 and the surface of the copper layer 3 is formed in the recess 4a in FIG. 2(b).
occurs, making it impossible to stably adhere the dry film 5.
During patterning of the copper layer 3 for forming wiring, an etching solution seeps into the gap 6, causing disconnection or damage to the wiring.
【０００７】また、ベルト研磨法では、銅層３の表面に
平坦な面は得られるが、微細な凹凸が形成されないため
、銅層３の表面とドライフィルム５は密着安定化する事
ができなかった。[0007]Also, in the belt polishing method, although a flat surface can be obtained on the surface of the copper layer 3, fine irregularities are not formed, so that the surface of the copper layer 3 and the dry film 5 cannot be stabilized in adhesion. Ta.
【０００８】[0008]
【課題を解決するための手段】本発明の印刷配線基板の
表面処理方法は、ガラスエポキシ基板上に設けた金属層
の表面に生じた凹凸をベルト研磨法により研磨して平坦
化する工程と、前記金属層の表面を前記ベルト研磨の方
向と直交する方向にバフ研磨法で研磨し前記金属層の表
面に微細な凹凸を形成する工程とを含んで構成される。[Means for Solving the Problems] The surface treatment method for a printed wiring board of the present invention includes the steps of polishing and flattening the irregularities generated on the surface of a metal layer provided on a glass epoxy substrate using a belt polishing method; The method includes the step of polishing the surface of the metal layer by a buffing method in a direction perpendicular to the belt polishing direction to form fine irregularities on the surface of the metal layer.
【０００９】[0009]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【００１０】図１（ａ）〜（ｃ）は本発明の一実施例を
説明するための工程順に示した断面図である。FIGS. 1(a) to 1(c) are sectional views showing an embodiment of the present invention in order of steps.
【００１１】まず、図１（ａ）に示すように、表面に厚
さ１８μｍの銅箔を設けたガラスエポキシ基板２に直径
１．０ｍｍのスルーホール９を設け、スルーホールの側
壁を含む表面に銅めっき層を３０μｍの厚さに形成して
銅層３を形成する。First, as shown in FIG. 1(a), a through hole 9 with a diameter of 1.0 mm is provided in a glass epoxy substrate 2 whose surface is coated with a copper foil having a thickness of 18 μm. A copper layer 3 is formed by forming a copper plating layer to a thickness of 30 μm.
【００１２】次に、図１（ｂ）に示すように、凸部４と
凹部４ａとの高低差３〜８μｍの起伏を有する銅層３の
表面を粗さ６００番のベルト研磨布により研磨して高低
差１〜２μｍの平坦面を形成した後、硬度７０のバフ研
磨材によりベルト研磨布の研磨方向に対して直交する方
向に研磨し、銅層３の表面に表面粗さ０．１〜１．０μ
ｍの微細凹凸部８を形成した印刷配線基板を形成する。Next, as shown in FIG. 1(b), the surface of the copper layer 3, which has an uneven height difference of 3 to 8 μm between the convex portions 4 and the concave portions 4a, is polished using a belt polishing cloth with a roughness of No. 600. After forming a flat surface with a height difference of 1 to 2 μm, the surface of the copper layer 3 is polished with a buffing material having a hardness of 70 in a direction perpendicular to the polishing direction of the belt polishing cloth, so that the surface of the copper layer 3 has a surface roughness of 0.1 to 2 μm. 1.0μ
A printed wiring board on which microscopic unevenness 8 of m is formed is formed.
【００１３】次に、図１（ｃ）に示すようにこの印刷配
線基板の表面にドライフィルム５を貼付けることにより
、ドライフィルム５と銅層３の表面との間に隙間を生ず
ることなくドライフィルム５を銅層３の表面に密着させ
ることができる。Next, as shown in FIG. 1(c), by pasting a dry film 5 on the surface of this printed wiring board, the dry film 5 can be dried without creating a gap between the dry film 5 and the surface of the copper layer 3. The film 5 can be brought into close contact with the surface of the copper layer 3.
【００１４】[0014]
【発明の効果】以上説明した様に本発明は、銅層の表面
を平坦にし、なおかつ、その平坦面に０．１〜１．０μ
ｍの微細な凹凸を形成する事ができるため、ドライフィ
ルムと銅層の表面との間に隙間を生じることなくドライ
フィルムを密着でき、安定した耐エッチング性が得られ
エッチング液のしみ込みによる配線の断線や欠損を防止
できるという効果を有する。Effects of the Invention As explained above, the present invention makes the surface of the copper layer flat and has a thickness of 0.1 to 1.0 μm on the flat surface.
Since it is possible to form fine irregularities of m, the dry film can be closely attached to the surface of the copper layer without creating any gaps, and stable etching resistance can be obtained, making it possible to prevent wiring from seeping into the etching solution. This has the effect of preventing wire breakage and damage.
【図１】本発明の一実施例を説明するための工程順に示
した断面図である。FIG. 1 is a cross-sectional view showing the order of steps for explaining an embodiment of the present invention.
【図２】従来の印刷配線基板の表面処理方法を説明する
ための工程順に示した断面図である。FIG. 2 is a cross-sectional view showing the order of steps for explaining a conventional surface treatment method for a printed wiring board.
２ ガラスエポキシ基板 ３ 銅層 ４ 凸部 ４ａ 凹部 ５ ドライフィルム ６ 隙間 ８ 微細凹凸部 ９ スルーホール 2 Glass epoxy substrate 3 Copper layer 4 Convex part 4a Recessed part 5 Dry film 6 Gap 8 Fine unevenness 9 Through hole
Claims (1)
の表面に生じた凹凸をベルト研磨法により研磨して平坦
化する工程と、前記金属層の表面を前記ベルト研磨の方
向と直交する方向にバフ研磨法で研磨し前記金属層の表
面に微細な凹凸を形成する工程とを含むことを特徴とす
る印刷配線基板の表面処理方法。1. A step of polishing and flattening irregularities generated on the surface of a metal layer provided on a glass epoxy substrate by a belt polishing method, and polishing the surface of the metal layer in a direction perpendicular to the direction of the belt polishing. A method for surface treatment of a printed wiring board, comprising the step of polishing by buffing to form fine irregularities on the surface of the metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3971291A JPH04277690A (en) | 1991-03-06 | 1991-03-06 | Surface treatment of printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3971291A JPH04277690A (en) | 1991-03-06 | 1991-03-06 | Surface treatment of printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04277690A true JPH04277690A (en) | 1992-10-02 |
Family
ID=12560607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3971291A Pending JPH04277690A (en) | 1991-03-06 | 1991-03-06 | Surface treatment of printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04277690A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6242079B1 (en) | 1997-07-08 | 2001-06-05 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
-
1991
- 1991-03-06 JP JP3971291A patent/JPH04277690A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6242079B1 (en) | 1997-07-08 | 2001-06-05 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3137186B2 (en) | Interlayer connection structure, multilayer wiring board, and method for forming them | |
| TWI422297B (en) | A printed circuit board manufacturing method and use of the printed circuit board has this | |
| JPH04277690A (en) | Surface treatment of printed wiring board | |
| JP2000236145A (en) | Wiring board and its manufacturing method | |
| JP2633366B2 (en) | Leadless chip carrier for computer module | |
| JPS6447053A (en) | Formation of multilayer interconnection | |
| JP3622219B2 (en) | Multilayer wiring board manufacturing method | |
| JP4153422B2 (en) | Method for manufacturing printed wiring board | |
| JP2000101231A (en) | Manufacture of printed wiring board | |
| JPH06260772A (en) | Lessening method of mechanical polish flaw | |
| JPS5918858B2 (en) | How to embed photoresist film | |
| JPS60167306A (en) | Manufacture of printed coil | |
| JPS60244091A (en) | Method of removing burr | |
| JPH04264728A (en) | Semiconductor device and production thereof | |
| JP2787247B2 (en) | Method for manufacturing double-sided film carrier | |
| JP2007242659A (en) | Printed wiring board and its manufacturing process | |
| JPH06112199A (en) | Manufacture of wiring board | |
| JPH0142518B2 (en) | ||
| JPH0513927A (en) | Manufacture of printed-wiring substrate | |
| JPH04188791A (en) | Manufacture of thin film multilayer substrate | |
| JPH04162796A (en) | Thin film multi-layer substrate | |
| JPH09225831A (en) | Machining method for thin plate | |
| JPH10313172A (en) | Multilayer printed circuit board and its manufacture | |
| JPH0961997A (en) | Photosensitive member for production of circuit board and its production | |
| JP2003242619A (en) | Method of cleaning metallic surface after polyimide etching |