JPH04275663A - System for deciding fault processor - Google Patents

Abstract

PURPOSE:To improve the accuracy for deciding the fault processor by accumulating the number of information as an abnormal processor for each processor and deciding it as the fault one when the number of accumulated information exceeds a threshold value. CONSTITUTION:Processors 21 to 2n detect the abnormality of the opposite processor in communication and inform it to a master processor 30 each other. This abnormality information is accumulated in an accumulation processing part 61 of the master processor, and stores it in information number storage memories 71 to 7n for each processor. An information frequency check processing part 62 checks the information number storage memories 71 to 7n for each abnormality information, and decides the processor as a fault one when the accumulation number exceeds the prescribed threshold value.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system in which a plurality of processors are connected via a bus and communicate with each other, and more particularly to a method for determining a faulty processor.

0002

2. Description of the Related Art Conventionally, in this type of faulty processor determination method, an abnormality in the other processor is detected during communication between the processors, and when a master processor with a fault determination function is informed of the other processor's abnormality, the master processor It was reported that the other party's processor had been determined to be at fault.

Next, a conventional example will be explained with reference to the drawings. FIG. 2 is a block diagram showing a conventional example, in which n processors 21 to 2n and a master processor 30 are connected via a bus 10, and the processors 10 to 2n and the master processor 30 communicate with each other. A multiprocessor system is shown that carries out predetermined processing. The master processor 30 has a central processing unit 60 and a bus 1
The receiving unit 40 receives data on the bus 10 and transmits the data to the central processing unit 60, and the transmitting unit 50 transmits data from the central processing unit 60 onto the bus 10. The central processing unit 60 has a faulty processor determination processing unit 61 that determines the notified processor to be faulty.

For example, if processor 22 detects an abnormality in processor 21 while processor 21 and processor 22 are communicating via bus 10, processor 22 notifies master processor 30 of the abnormality in processor 21 via bus 10. The master processor 30 receives the secret information from the processor 22 through the receiving unit 40 and sends it to the central processing unit 60.
An abnormality in the processor 21 is notified to the processor 21. Upon receiving the abnormality notification, the faulty processor determination processing unit 61 of the central processing unit 60 determines that the processor 21 is faulty.

[0005]

[Problems to be Solved by the Invention] In the above-mentioned conventional method for determining faulty processors, the master processor with the fault determination function immediately determines the notified processor as faulty. Even if a master processor with a faulty function is notified when the processor itself is abnormal, it has the disadvantage that the master processor with the faulty function will judge a processor that is actually normal to be faulty.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for determining a faulty processor, which accumulates the number of fault notifications for each processor and determines a processor whose fault exceeds a predetermined threshold to be faulty.

[0007]

[Means for Solving the Problems] A method for determining a faulty processor according to the present invention is a multiprocessor system in which a plurality of processors are connected via a bus and communicate with each other, and a faulty processor is detected during communication between the processors. In a failure processor determination method in which an abnormality is detected, the detected abnormality in a partner processor is notified to a master processor having a failure determination function, and a failure of the processor is determined, the master processor calculates the number of times the notification has been made to the plurality of times. and means for determining the processor as having a failure when the cumulative number of notifications exceeds a predetermined threshold.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, n processors 21 to 2n and a master processor 30 are connected via a bus 10.
2n and a master processor 30, a multiprocessor system is shown in which predetermined processing is carried out while communicating with each other. The master processor 30 includes a central processing unit 60, a receiving unit 40 that takes in data on the bus 10 and transmits it to the central processing unit 60, a transmitting unit 50 that transmits data from the central processing unit 60 onto the bus 10, and a central processing The storage device 70 is connected to the device 60. The central processing unit 60 has a cumulative processing unit 61 that totals the number of times that a person has been notified, and a person who has been informed of a number of times. Memory 71-7
It has n.

Next, the determination operation of a faulty processor will be explained. Here, it is assumed that the processor 21 is an abnormal processor, the processors 22 to 2n are normal processors, the number n of processors is nine, and the predetermined threshold for failure determination is five. When the processor 22 detects an abnormality in the processor 21 while the processors 21 and 22 are communicating via the bus 10, the processor 22 notifies the master processor 30 of the abnormality in the processor 21 via the bus 10 in a predetermined manner. In addition, the processor 21 mistakenly
is detected as an abnormality and notified to the master processor 30 via the bus 10.

[0010] The master processor 30 receives the secret information from the processors 21 and 22 through the receiving section 40 and notifies the central processing unit 60 of the information. Cumulative processing unit 6 of central processing unit 60
1 adds 1 to the informing number storage memories 71 and 72 of the corresponding processor in the storage device 70. Next, the informing frequency check processing unit 62 checks whether the cumulative number of informings in the informing frequency storage memories 71 and 72 of the corresponding processor of the storage device 70 exceeds the threshold value 5. Currently, the cumulative number of times in the informing number storage memories 71 and 72 of both processors 21 and 22 is 1, so the master processor 30 does not determine that there is a failure. In this way, for example, if the processor 21 and the processors 23 to 29 communicate and notify each other, the number of notifications 71 of the processor 21 is 9, and the cumulative circuit of the number of notification storage memories 73 to 79 of the processors 23 to 29 is 1, respectively. It will be times.

[0011] Here, in the notification frequency check process 62, the central processing unit 60 determines as a failure when the notification frequency storage memories 71 to 79 exceed a predetermined threshold value of 5, and therefore determines that the processor 21 is a failure. and other processor 2
2 to 29 are determined to be normal.

0012

[Effects of the Invention] As explained above, the present invention accumulates the number of times each processor is notified of an abnormal processor by a master processor having a fault determination function, and when the cumulative number of notifications exceeds a predetermined threshold. By determining that the processor in question is at fault, it is possible to prevent a normal processor from being determined to be at fault due to just one erroneous fault report.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example of a faulty processor determination method.

[Explanation of symbols]

10 Bus 21~2n Processor 30 Master processor 40 Receiving section 50 Transmission section 60 Central processing unit 61 Cumulative processing section 62. Snitch frequency check processing unit 70 Storage device

Claims (1)

[Claims] Claim 1: A multiprocessor system in which a plurality of processors are connected via a bus to perform communication between the processors, in which an abnormality in a partner processor is detected during communication between the processors, and the detected abnormality in the partner processor is detected as a fault. In the failure processor determination method, the master processor has a means for accumulating the number of times of notification for each of the plurality of processors; 1. A method for determining a faulty processor, comprising means for determining the processor to be faulty when the number of notifications exceeds a predetermined threshold.