JPH04275435A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having well-controlled dimensions without etching a refractory metal film. CONSTITUTION:An electron-donating thin film 3 is formed on a semiconductor substrate 1 coated with an insulating film 2. An insulating film 4 on the thin film 3 is patterned to expose the film 3. Refractory metal 5 is deposited on the surface, and it is used as a mask to implant impurity into the semiconductor substrate 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

0002

2. Description of the Related Art A conventional method for manufacturing a semiconductor device is shown in FIG. A gate oxide film 2 is formed on a semiconductor substrate 1, and a polycrystalline Si film 3 is deposited on this gate oxide film 2. Next, a high melting point metal (W) is applied by sputtering or CVD.
, Mo, Ta, Ti, Co, etc.) is deposited, and resist patterning is performed by photolithography to form a resist pattern 11 in units of 1 micron (
Figure 2(a)). Next, when the high melting point metal film 5 and the polycrystalline Si film 3 are etched by a dry etching method,
A gate electrode of a MOS transistor is formed. Further, ion implantation is performed to form the source/drain portion 12 (FIG. 2(b)). Furthermore, an insulating film 9 is deposited and RIE (Reactive Ion Etchi) is applied.
This insulating film 9 is etched by anisotropic etching using .ng) to form a contact hole for taking out the electrode (FIG. 2(c)). At present, a MOS transistor is manufactured by finally forming source/drain electrode wiring 10 (FIG. 2(d)).

0003

SUMMARY OF THE INVENTION The conventional semiconductor device manufacturing method described above has the following problems.

(1) When etching the high melting point metal film 5 and polycrystalline Si film 3 shown in FIG. 2, if the gate length is less than 1 μm, that is, in the submicron order, the amount of side etching that occurs during etching will be larger than the gate length. 20~
As a result, the gate length of the gate electrode formed after etching becomes small, and dimensional controllability becomes extremely poor.

(2) Refractory metals are generally F-based gases,
Etching is possible with Cl-based gas, etc.
Wet etching is possible for materials such as O, Mo, etc. However, this method has poor dimensional controllability, and it has been almost impossible to form patterns in the submicron region at a commercial level. Furthermore, in dry etching,
Currently, there is no ideal gas for etching high melting point metals in submicron patterns.

An object of the present invention is to provide a method for manufacturing a semiconductor device with good dimensional control without etching a high melting point metal film.

[0007]

[Means for Solving the Problems] A method for manufacturing a semiconductor according to the present invention is a method for manufacturing a semiconductor device having a main electrode region and a control electrode provided through an insulating film. forming an electron-donating thin film for forming the control electrode, and forming a non-electron-donating thin film in a desired pattern shape on the electron-donating thin film to expose the surface of the electron-donating thin film. a step of forming an opening, a step of selectively depositing a refractory metal in the opening to form a refractory metal film for forming the control electrode, and a step of depositing the refractory metal for forming the main electrode region. The method is characterized by including a step of ion-implanting impurities into the semiconductor substrate using a film as a mask.

[0008]

According to the present invention, a gate electrode made of a high melting point metal can be formed with good dimensional controllability without etching.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In a preferred embodiment of the present invention, the refractory metal is M
A gate electrode consisting of a plurality of layers is formed by selectively depositing it in the shape of a gate electrode on a sublayer of a gate electrode, which serves as a control electrode that determines the threshold value of an OS transistor.

Specifically, M
Form an OS transistor.

A silicon oxide film with a thickness of 50 to 100 Å is formed on the semiconductor substrate by thermal oxidation, and a polycrystalline silicon film is formed on it with a thickness of 1000 to 2000 Å by CVD or sputtering.
Å form. Furthermore, an insulating film such as a silicon oxide film or a silicon nitride film is formed using a CVD method or a sputtering method.
A thickness of 5000 Å is formed. Apply photoresist on top of it.
．． A resist pattern for a gate electrode with a width of 5 μm is formed. At this time, it is preferable to use electron beam exposure or the like.

The silicon oxide film is then etched by dry etching. The etching conditions at this time are, for example, C2 F4 gas at 20 to 100 SCCM and CHF3 at 20 to 100 SC in a reduced pressure etching furnace.
CM is flowed, the pressure is maintained at about 60 to 120 pa, and the RF power is about 200 to 500 W.

Next, a high melting point metal is selectively deposited in the gate electrode opening of the silicon oxide by selective CVD. At this time, for example, (1) a deposition method using WF6 through a reduction reaction with underlying polycrystalline Si, (2) a selective deposition method using W(CH3)6 and hydrogen,
Furthermore, as in the case of W above, (3) a deposition method using a reduction reaction of MoF6 with Si,
(4) Selective deposition method using Mo(CO)6 and hydrogen, (
5) A selective deposition method using Mo(CH3)6 and hydrogen is used. In particular, do not etch the underlying Si (
2), (4), and (5) are preferable. The base material on which the W or Mo film is selectively formed is an electron-donating material.

The base material on which the W film or Mo film is selectively formed is an electron-donating material. An electron-donating material is one in which free electrons exist in the substrate or free electrons are intentionally generated.For example, a chemical reaction occurs through electron transfer with raw material gas molecules attached to the surface of the substrate. A material with a surface that is promoted. For example, metals and semiconductors generally correspond to this. It also includes those in which a thin oxide film exists on the surface of a metal or semiconductor. This is because a chemical reaction occurs between the substrate and the attached raw material molecules due to electron exchange.

Specifically, single crystal silicon, polycrystalline silicon. P-type, I-type, N-type semiconductors such as amorphous silicon,
Binary, ternary, or quaternary III-V compound semiconductors consisting of a combination of Ga, In, and Al as Group III elements and P, As, and N as Group V elements, tungsten, molybdenum, tantalum, Tungsten silicide, titanium silicide, aluminum, aluminum silicon, titanium aluminum, titanium nitland,
Includes metals, alloys, and their silicides, such as copper, aluminum silicon copper, aluminum palladium, titanium, molybdenum silicide, and tantalum silicide.

On the other hand, as a material forming a surface on which W and Mo are not selectively deposited, that is, a non-electron donating material, silicon oxide, BSG, etc.
, glass or oxide film such as PSG, BPSG, silicon thermal nitride film, plasma CVD, low pressure CVD, ECR-C
It is a silicon nitride film or the like made by VD method or the like.

Next, after wet etching the silicon oxide film, the underlying polycrystalline silicon is etched using the upper refractory metal as a mask. At this time, use ECR plasma etching equipment to apply HBr at 20 to 100 SC.
CM, SF6 is flowed at 20-100 SCCM and the pressure is 1-100 SCCM.
Maintain the pressure at 10 Pa and increase the microwave power to 200 to 500.
It is desirable to carry out the experiment with the RF power set to 30 to 100 W.

After a plurality of layers of gate electrodes are formed in the self-aligned manner in this manner, ions are implanted using the gate electrodes as masks to form source/drain regions as main electrode regions. Here, the MOS transistor is
When forming the D structure, the dose of P ions is 1×1012
After forming an n- region by implanting at ~5 x 1013/cm2, a silicon oxide film is deposited at ~3000 m2 by CVD, etc.
After 8000 Å deposition, 5-20 SCC of CHF3
M, CF4 10~30SCCM, Ar 400~7
Etch back with 00 SCCM flow, pressure maintained at 1.0 to 2.0 Tor, and RF power of 200 to 400 W. After that, As ions are applied at a dose of 1×1015 to 1×
It is implanted at 1016/cm2 and heat treated to form an n+ region.

After forming the main region in this way, the BPSG film is deposited to a thickness of 3000 to 6000 Å by CVD method or the like.
Then, contact holes for source and drain are formed.

[0021] Thereafter, Al is selectively deposited in the contact hole. Here, it is preferable to use a CVD method using an alkyl aluminum hydride and hydrogen. This selective CVD method uses hydrogen gas and dimethylaluminum hydride as an alkyl aluminum hydride to deposit Al on an electron-donating substrate.
When forming a film, the surface of this substrate is directly heated by resistance heating or a lamp, and a deposited metal film is formed by thermal CVD.

[0022] During Al selective deposition, the surface temperature of the electron-donating substrate is preferably higher than the decomposition temperature of the alkyl aluminum hydride and lower than 450°C, more preferably higher than 260°C and lower than 440°C.

In particular, if monomethylaluminum hydride (MMAH) or dimethylaluminum hydride (DMAH) is used as the raw material gas, H2 gas is used as the reaction gas, and the substrate surface is heated with a lamp under a mixed gas of these, A high quality Al film can be formed at a high deposition rate.

In this case, by setting the substrate surface temperature at the time of forming the Al film to a more preferable range of 260° C. to 440° C., the temperature can be reduced by 3000 to 5000 Å/
High quality films can be obtained at high deposition rates of minutes.

Although the present invention has been described above with respect to a MOS transistor, it can be applied to any semiconductor device requiring a similar electrode structure.

In this embodiment, the gate electrode has a length of 0.5 μm, and an LDD (Lightly
An example of forming a MOS device having a doped drain structure will be described.

A thickness of 75 mm is formed on the semiconductor substrate 1 by thermal oxidation.
A gate oxide film 2 with a thickness of 1,500 Å was formed on the gate oxide film 2 by the LP-CVD method. Next, a SiO2 film 4 with a thickness of 3500 Å is formed by the CVD method, and a 0.5
A resist space pattern with a width of μm is formed, and then C
2F6: 60SCCM, CHF3: 20SCCM,
Dry etching was performed under conditions of a pressure of 90 Pa and RF power of 350 W to form a space pattern (opening) so that the surface of polycrystalline silicon 3 was exposed (Figure 1
(a)).

Next, W (symbol 5), which is a high melting point metal, was selectively deposited inside the opening by selective CVD (FIG. 1(b)). W selection CVD method uses W(CH3)6, which is organic tungsten, as a source gas containing W, which is a component of the deposited film, and H2, as a reaction gas.
A W film was selectively formed on the substrate by vapor phase growth using a mixed gas of these.

In this embodiment, the electron-donating material is polycrystalline silicon, and the non-electron-donating material is silicon oxide produced by CVD or the like. As a result, W was selectively deposited only on the polycrystalline Si film 3, but not on the SiO2 film 4.

Next, SiO2 formed by CVD method
The membrane was removed by wet etching with fluoric acid buffer. Furthermore, using the gate electrode made of W as a mask, polycrystalline Si was etched under the etching conditions HBr: 60SCCM, S
Etching was performed anisotropically using an ECR (electron cyclotron resonance) etching device under F6: 60 SCCM, pressure: 5 Pa, microwave power: 350 W, and RF power: 60 W. Next, to form the LDD structure,
Implantation conditions for P ion implantation: 1×1013/cm2
An implanted N- layer 6 was formed on the semiconductor substrate 1 (see FIG. 1(
c)).

Next, in order to form spacers 8 having an LDD structure, a 6000 Å thick SiO 2 film was deposited on the substrate by the CVD method. Next, etch back was performed to form spacers. The etch back conditions at this time are CF4: 70SCCM, CHF3: 5SCC
M, Ar: 500SCCM, pressure: 1.5 Torr and power RF: 300W. In order to form the highly concentrated source/drain regions 7, As was ion-implanted under conditions of 5 x 1016/cm2 (Fig. 1(d)
)).

Finally, BPSG (Bor
on-phospho silicate gla
ss) Deposit the film 9 to a thickness of 4000 Å, pattern the contact hole for taking out the electrode, and select the Al electrode 10 using hydrogen gas and dimethylaluminum hydride as the raw material gas by CVD method. (Fig. 1(e)).

In the case of this example, the electron-donating material is silicon and the non-electron-donating materials are BPSG and silicon oxide, so Al is selectively deposited only on silicon and is deposited on BPSG and silicon oxide. No Al was deposited on the surface.

Thereafter, Al was deposited by sputtering and patterned to form wiring 13.

By the semiconductor manufacturing method of this embodiment, the LD
A MOS with a gate length of 0.5 μm having a D structure could be formed with good dimensional control. Further, the variation in Vth (threshold voltage of MOS) of the MOS transistor using the manufacturing method of this embodiment can be reduced to 1/3 of the variation in Vth of the conventional MOS transistor.

In this embodiment, W was selectively deposited within the space pattern, but Mo may also be deposited within the space pattern. In this case, an organic Mo compound and H2 gas are used as source gases in the Mo film deposition method. As an organic Mo compound, Mo(CO) is solid at room temperature.
A Mo film is deposited by sublimating 6 or Mo (CH3) in a carrier gas such as H2 gas or Ar, and reacting it on a heated substrate. Although the detailed mechanism of the reaction is not necessarily clear, Mo(CO)6 and others react with H2 on the surface of a heated electron-donating substrate such as a metal or semiconductor.
It is thought that Mo is generated by reacting with the gas. Since this reaction is difficult to proceed unless the substrate surface is electron-donating, it is thought that film deposition on the non-electron-donating surface is difficult to occur. Thermal decomposition of Mo(CO)6 alone occurs at around 400°C, and partial decomposition occurs even at 300°C. If the pressure is high and there is no H2, these decomposition products will deposit on the substrate without selectivity. Moreover, at this time, a considerable amount of carbon and oxygen are incorporated into the Mo film, resulting in an increase in electrical resistance. Therefore, H2 gas is essential during the reaction to prevent impurities from entering the film. When the substrate temperature is 300° C. or higher and the pressure of the reaction gas is high, film deposition also occurs on non-electron-donating surfaces such as SiO2 and Al2 O3, reducing the selectivity of deposition. Selective deposition will not occur unless the reaction pressure is 100 Torr or less, and in practice it is preferably 10 Torr or less. If the temperature of the substrate is too high, Mo(CO)6
Since the film is actively decomposed without the aid of H2 or an electron-donating surface, impurities in the film increase again and the selectivity of the deposition is lost. A substrate temperature of 800°C or higher cannot be used, and preferably 60°C or higher.
A temperature of 0°C or lower is appropriate. The most desirable temperature range is 450
~550°C. MoCl5, MoF6, etc.
Methods of reduction using 2 or Si are known, but these methods cause damage such as mixing of halogen elements into the film and etching of the Si substrate or SiO2 film, deteriorating the characteristics of the substrate. Therefore, the characteristics of devices using this may deteriorate. According to the method of the present invention, since no halogen element is used, it is possible to selectively deposit a Mo film without any of the above problems. The source gas may be Mo(CH3)6 in addition to Mo(CO)6. Mo(CH3)6 is more desirable than Mo(CO3)6 in obtaining a high purity film. The organic compounds of Mo are not limited to these.

[0037]

[Effects of the Invention] As explained above, according to the present invention,
Forming the gate electrode by the selective CVD method has the following effects.

(1) Submicron gate electrodes can be formed with good dimensional control.

(2) Even gate materials that are difficult to dry-etch can be used as gate electrodes by using this method.

(3) Since the dimensional accuracy of this gate electrode is extremely high, it is possible to suppress the variation in Vth to about 1/3 of that of the conventional type.

[Brief explanation of the drawing]

FIG. 1 is a process diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process diagram for explaining a conventional method for manufacturing a semiconductor device. 1 Semiconductor substrate 2 Gate oxide film 3 Polycrystalline Si film 4 SiO2 film 5 High melting point metal film 6 N- layer 7 High concentration source/drain 8 Spacer 9 BPSG film 10 Electrode 11 Resist pattern 12 Source/drain part 13 Wiring

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor device having a main electrode region and a control electrode provided through an insulating film, comprising:
forming an electron-donating thin film for forming the control electrode on a semiconductor substrate via an insulating film; forming a non-electron-donating thin film in a desired pattern shape on the electron-donating thin film;
a step of forming an opening through which the surface of the electron-donating thin film is exposed; a step of selectively depositing a refractory metal in the opening to form a refractory metal film for forming the control electrode; and a step of forming a refractory metal film for forming the control electrode. A method for manufacturing a semiconductor device, comprising the step of ion-implanting impurities into the semiconductor substrate using the high melting point metal film as a mask to form an electrode region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the high melting point metal is W or Mo.