JPH04273723A - Method and circuit for data conversion - Google Patents

Abstract

PURPOSE:To offer a data conversion system and a data conversion circuit from which high fidelity can be obtained with simple configuration in data in which the amplitude and frequency distribution of an acoustic signal, etc., are comparatively moderated. CONSTITUTION:Difference D3 between input data D1 outputted from an ADC and one preceding sampling data stored in a register is found at a subtraction circuit and subtraction output is compared with data D4 in which the maximum value of a code to be compressed i.e., all the low-order eight bits are 1s by a comparator, and a selector is controlled by comparison output, and when the subtraction output is larger than the above maximum value D4, the maximum value data d 4(11...1) of the code to be compressed is outputted, and when the subtraction output is less than the maximum value D4, data d 3 of low-order eight bits of the subtraction output is outputted. The one preceding sampling data is updated by an adder and the register.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion system and a data conversion circuit, and relates to a technique effective for use in, for example, digital audio circuits.

0002

2. Description of the Related Art In digital audio, codes are compressed in order to lengthen the recording time. The amplitude and frequency distribution of acoustic signals change relatively gently but significantly over time. Therefore, adaptive PC is used as an encoding method that changes the quantization step width according to the properties of nearby signals.
There is M (APCM). In this adaptive PCM, the quantization step width is changed depending on the amplitude of the quantized value of the immediately preceding sample. In addition, adaptive differential PCM is a differential PCM in which an adaptive step width is introduced, and instead of directly quantizing the signal, the difference between the signal and the predicted value is quantized. ΔM is an encoding method that quantizes a signal using 1 bit. This method results in large distortions when the signal changes rapidly. On the other hand, the adaptive ΔM increases the quantization step width when the same sign continues, and decreases it when the sign is reversed. Regarding such code conversion technology, please refer to the Japan Audio Association, ed., Ohmsha, July 25, 1987.
``Digital Audio Dictionary'' published by Japan, pages 26 to 28.

0003

[Problems to be Solved by the Invention] The above-mentioned adaptive PCM, adaptive differential PCM, and adaptive ΔM all require a multiplication circuit to change the step width. This has the disadvantage that a complicated circuit is required and the circuit scale becomes large. Further, ΔM has the disadvantage that quantization distortion is large and fidelity is lacking. An object of the present invention is to provide a data conversion method and data conversion circuit that can obtain high fidelity with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

0004

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. In other words, the difference between the previous sampling data and the input data is calculated, and if the difference is larger than the maximum value of the code to be compressed, the maximum value is output, and if it is smaller, the subtraction result is output and compressed. Obtain the data. In addition, the difference between the input data and the previous sampling data stored in the register is calculated using a subtraction circuit,
The subtraction output is compared with the maximum value of the code to be compressed by a comparator, and the selector is controlled by the comparison output to output the maximum value when the subtraction output is larger than the above maximum value. When it is smaller than the value, a circuit is used that outputs a subtracted output.

[0005]

[Operation] According to the above-mentioned means, the amplitude and frequency distribution of the acoustic signal are relatively stable over time, and data compression and expansion with higher fidelity can be achieved by using the data conversion method as described above. can. This data compression and expansion can be realized by a combination of simple logic circuits such as a subtraction circuit, an addition circuit, a comparator, and a register.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of an embodiment of a data conversion circuit constructed using a data conversion method according to the present invention. Although not particularly limited, the data conversion circuit of this embodiment is intended for a circuit that converts an analog signal into 16-bit digital data, compresses it into 8-bit digital data, and outputs it. The analog signal Vin is input to the analog/digital conversion circuit ADC, where it is converted into digital data consisting of n bits (for example, 16 bits as described above). In this embodiment, the digitally converted 16-bit data is converted into m (for example, 8 bits)
In order to compress the data into , the following circuit is used.

The digitally converted 16-bit data D1 is input to one input of the subtracter. The 16-bit data D2 stored in the register is input to the other input of the subtracter. 16 stored in this register
The bit data D2 is the previous sampling data, as will be described later. The subtracter extracts 1 stored in the register from the digitally converted input data D1.
The previous sampling data D2 is subtracted and the difference (
D1-D2) data D3 is output. This difference data C is supplied to one input B of the comparator. The other input A of the comparator is supplied with data D4 corresponding to the maximum value of the 8-bit data to be compressed. This data D4 is 0000000011 as shown in the same figure.
It consists of 16 bits of 111111, and the lower 8 bits (m
) is all 1 data (255 in decimal notation).

The comparator compares the magnitude of data D3 and D4 supplied to input terminals A and B, and B>A(D3
>D4), a high level output signal is formed, and A
>B, a low level output signal is formed. The output signal of this comparator is used as a selector selection signal. The maximum value data d4 (11111111) consisting of 8 bits to be compressed is input to one input A of the selector, and the data d3 for the lower 8 bits of the difference data D3 is input to the input B. It has been entered. In other words, if the output signal of the comparator is at a high level, this selector selects that the subtraction data D3 is D4.
When the value is larger than that, the maximum value data d4 of the input A is selected and outputted, and if the output signal of the comparator is at a low level, in other words, the subtraction data D3 is equal to D4.
When it is smaller, data d3 of the lower 8 bits of the subtraction output supplied to input B is output.

The output signal d5 of the selector is, although not particularly limited to, 8-bit digital data Dou that is once stored in a memory circuit and then read out and compressed.
It is output as t. Output signal d5 of the above selector
is fed to one input of the adder. The output data D2 of the register is supplied to the other input of this adder. As a result, the adder adds the compressed data d5 output from the selector to the previous sampling data D2 stored in the register, and adds the compressed data d5 outputted from the selector to the previous sampling data D2 stored in the register. The updated sampling data D2' is generated and stored in the register. In this way, by generating the next sampling data using the register and the adder, cumulative errors can be prevented. Hereafter, by repeating the same as above, 16
The input data D1 of bits (n bits) is converted into 8 bits (m
This is to convert the data into data d5 compressed into bits).

FIG. 2 shows a waveform diagram for explaining the analog/digital conversion operation accompanied by the above data compression operation. At the start of data compression, the data in the register is cleared (0000000000000000). Therefore, when the analog signal suddenly decreases and rises as shown in the figure, it cannot be followed by the progressive addition operation of the maximum value of the lower 8 bits, but once the difference between the input digital signal and the previous sampling data When the value becomes less than the maximum value of the compressed data, compressed data that faithfully corresponds to changes in the input signal can be obtained. The amplitude and frequency distribution of acoustic signals is relatively stable over time, making it possible to compress data with a level of fidelity that is acceptable for practical use.

FIG. 3 shows a block diagram of another embodiment of a data conversion circuit using the data conversion method according to the present invention. In this embodiment, m
It is intended for a circuit that expands data compressed into bits (for example, 8 bits) into n-bit (16 bits) data, converts it into an analog signal, and outputs it. The data Din compressed by the data compression circuit shown in FIG. 1 is temporarily stored in a memory circuit, although this is not particularly limited. Data d5 read from this memory circuit is supplied to one input of the adder. The other input of the adder is supplied with n-bit data D6 stored in the register. The adder adds the data d5 and data D6 to form data D7. This data D7 is input data to the register, although it is not particularly limited. The data D6 outputted from the register is inputted as expanded data to the digital/analog conversion circuit DAC to form a demodulated analog signal Vout.

The operation of the data expansion circuit is as follows. At the start of the data expansion operation, the register is cleared in the same manner as described above. Compressed data d5 read from the memory circuit
is added to data D6 of the register consisting of the previous n bits each time it is read, and is stored in the register as expanded data. Therefore, it is possible to restore decompressed data that changes stepwise in accordance with the amount of change caused by the compressed data d5 as shown in FIG.

FIG. 4 shows a block diagram of essential parts of an embodiment of a digital signal transfer system using the data conversion circuit according to the present invention. Although not particularly limited, the digital signal delivery system is intended for systems intended to commercialize and sell digital signals. That is, one form of digital signal delivery is the sale of digital signals. This figure shows a block diagram of a terminal device in the digital signal sales system. This terminal device corresponds to a vending machine for soft drinks such as cigarettes and juice. This terminal device plays the role of an information server, is connected to a digital signal vendor via a broadband digital communication line B-ISDN, and receives digital signals as products, although this is not particularly limited. By adopting such a system, digital signals are transmitted only to specified terminal devices through communication lines, similar to the above-mentioned products such as cigarettes and juice. In this case, digital signals can transfer data in large quantities at high speed without causing traffic congestion or air pollution unlike the above-mentioned general transportation of products. The above-mentioned terminal device is installed, for example, in front of a store such as a station store, a tobacco shop, or a bookstore. A terminal device is broadly divided into an input section, a storage section, and an output section, and each circuit block is connected by a VME bus to exchange digital signals and various control signals. A player indicated by a dotted line in the figure is connected to this terminal device, and a specific digital signal as a product is delivered in the form of an electric signal.

FIG. 5 shows a block diagram of the input section of the terminal device. The input section of the terminal device includes a digital input interface INF compatible with the broadband digital communication line B-ISDN, and an analog input interface (INF) that receives input signals in the form of analog signals.
right analog input, left analog input). The analog input interface is provided with low-pass filters LPF corresponding to right input Rin and left input Lin, respectively.
Extra frequency band components included in the analog input signals Rin and Lin are removed in advance. These input signals Rin and Lin are temporally alternately selected via the multiplexer MPX and sent to the sample & hold circuit S/H.
and converted into a digital signal by an analog/digital conversion circuit ADC. At this time, two-channel (stereo) digital signals, ie, a right channel signal and a left channel signal, are output in a time-division manner from the analog/digital conversion circuit ADC in a time-divisional manner, and are taken into the digital input interface INF. This input interface INF has a built-in data conversion circuit as described above, and performs data compression. Such an analog input interface is used, for example, to convert music programs sent by broadcasting, regular news programs, stock information, various commodity market conditions, etc. into digital signals and store them in a storage circuit. Note that the monaural signal is input using the right or left input signal. For input signals with a wide band such as music programs, the band of the low-pass filter LPF is widened, and for input signals with a narrow band such as news programs, the low-pass filter LPF is used.
A function such as switching the band to a narrower one may be added. I
NCT is an input controller, and NCT is indicated by a dotted line.
IF is a network interface compatible with the above B-ISDN.

The analog input interface may be connected to a telephone line to receive messages from an answering machine. In this case, a telephone function may be added to the terminal device, and the terminal device may be connected to the above-mentioned answering machine to receive recorded messages. Using an analog input interface in this manner increases message transfer time. Therefore, for subscribers with digital lines, if the messages are converted into digital signals and stored using a digital answering machine, and the data is compressed using the data conversion circuit as described above, multiple recorded messages can be can be received in a very short time. In this way, it is possible to listen to the message on the answering machine at any time, such as when the user is traveling by means of transportation or the like.

FIG. 6 shows a block diagram of an embodiment of the storage section in the terminal device. This storage section is
Data exchange between external storage devices such as hard disk memory HDD, RAM (Random Access Memory) as buffer memory, information processing program for digital input or analog input as mentioned above, and hard disk memory HDD. , a ROM (read only memory) that stores various programs such as display operations of the liquid crystal display device LCD and data transfer operations with the player connected to the output section, and performs information processing and control operations according to the above programs. Contains a microprocessor CPU. The RAM has a storage capacity of approximately 1 MB, although it is not particularly limited, and the ROM has a storage capacity of approximately 512 KB (kilobytes, hereinafter the same). Hard disk memory HDD is
Although not particularly limited, it has a storage capacity of approximately 250 MB (megabytes, the same hereinafter), functions as a backup memory when the power is cut off, and also plays a role like a warehouse by storing many types of digital signals. . This hard disk memory HDD is connected to an internal bus via a hard disk controller HDDC, and writes and reads data according to instructions from a microprocessor CPU. In this case, if you store data compressed using the data conversion method described above,
For example, since high-quality audio data consisting of 16 bits can be stored as 8-bit data, the storage capacity can be doubled.

[0017] The LCD is a liquid crystal display device, and is used to display information menus, operation instructions, and the like. Its surface has a touch key function for selecting display menus, switching displays, etc. For example, when you insert a player, the first information menu displayed on the display screen is 1. Music, 2. News, 3. Weather forecast, 4.
Stock market conditions, 5. Recitation etc. will be displayed. And one of them, for example 2. When you specify news, the screen changes and 1. NHK, 2. FEN, 3. Traffic information, 4. Sports news etc. are displayed. By specifying a desired news program, the player receives the corresponding digital signal. For example, 1. In the case of music, music genres such as classical, popular, popular songs, and jazz are displayed, and when a music genre is selected, the titles of songs that can be sold are displayed. This music information is not particularly limited, but it is assumed that it is stored in a specific area of the ROM or hard disk memory. When there is no corresponding song in the hard disk memory HDD, the music program is connected to the digital signal vendor via the communication line B-ISDN, and the desired music program is transmitted and delivered to the player. The LCD is connected to an internal bus via an LCD controller LCDC, and the above-described display and corresponding touch key input are performed. The bus interface VMEINF connects the above internal bus to the VM
This is a VME bus interface that connects with the E bus.

Information that needs to be replaced with the latest information as time passes, such as the above-mentioned news and stock market conditions, is stored in a buffer memory BM provided in the output unit, which will be described later. Thereby, the data can be immediately transferred to the player without accessing the hard disk memory HDD one by one. Also, music programs that are sold in large quantities may be stored in the buffer memory BM. In this case, the display menu may display top ten music genres with the highest sales volume to facilitate the user's selection.

The output section of the terminal device has an output interface OUT connected to the VME bus as shown in FIG.
INF, a player control circuit PCTL, a buffer memory BM, a monitor control circuit MOCTL, a monitor circuit MONT, and the like. The output section has a connector for connection to the player, and is connected to the player via the connector to exchange digital signals as a product. The buffer memory BM has a relatively large storage capacity of approximately 96 MB, which is approximately 10 times the maximum storage capacity of a player, which will be described later, of 8 MB. Although not particularly limited, the monitor circuit MONT is equipped with a speaker or headphone output, and is used for, for example, allowing the listener to listen to the "sawari" part when selecting a music program. This monitor circuit MONT and its controller MOCTL are
A reproduction circuit similar to the player's reproduction circuit described later is used.

[0020] As mentioned above, products such as cigarettes and juices sold by vending machines are put into packages or containers and sold integrally with the packages or containers. In addition, conventional commercialized information and the like are sold as printed matter using paper as a medium, or as media such as floppies or IC memory, which serve as packaging or containers. Music programs are also sold together with storage media such as magnetic tapes and compact discs. These media have no commercial value by themselves. When combined with terminal devices such as electronic notebooks and personal computers,
Information is extracted and processed as a product. Also,
The value of the product is demonstrated by combining music programs with cassette tape recorders and playback devices. In contrast, in the digital signal delivery test system of the present application, a digital signal as a product is delivered in the form of an electrical signal without intervening a storage medium that functions as a container as described above. . A storage circuit RAM is mounted on the player to exchange digital signals in the form of electrical signals. The digital signal captured in this RAM is
The playback circuit of the player allows the player to play by itself. In other words, the delivered product immediately exhibits its value as a product. These two features are very different from conventional product transactions. Further, in the system described above in which a player is connected to a terminal device and digital signals as a product are exchanged, it is possible to specify and sell only the necessary information when necessary. When adopting a data conversion method such as the one according to the present invention, it is possible to use an RA that has a relatively small storage capacity without impairing the fidelity of the reproduced audio signal.
M allows long-term or multiple types of programs to be stored.

In FIG. 7, POW is a power supply circuit;
Although not particularly limited, operating power is supplied from the terminal device in order to transmit high-speed digital signals to the player. Furthermore, when a rechargeable secondary battery is used as a power source for the player, it is also used for rapid charging. Examples of signals exchanged between the output section and the player include the operating voltage V, digital signal D, address signal A, control signal C, and status signal S.

FIG. 8 shows a block diagram of an embodiment of the above player. Broadly speaking, a player is composed of a storage circuit RAM for storing digital signals, a large-scale integrated circuit LSI composed of a gate array, etc., and a reproduction circuit. Although the memory circuit RAM is not particularly limited,
It consists of a pseudo-static RAM with a storage capacity of approximately 8MB. For example, as will be described later, 16 pseudo-static RAMs (PSRAMs) of about 4 Mbit are installed to realize the above-mentioned storage capacity of about 8 MB. The LSI is equipped with a control circuit CTL, an address counter AC, a multiplexer MPX, and a data conversion circuit DC. The control circuit generates various control signals for reproducing digital signals stored in the memory circuit RAM, as well as control signals for inputting data to the memory circuit RAM. The address counter AC generates an address signal when reading a digital signal stored in the storage circuit RAM. The multiplexer MPX is used when the storage circuit RAM is accessed from the server (terminal device) and when the storage circuit RAM is accessed from the server (terminal device).
Performs address switching when accessing M internally. That is, writing of a digital signal into the memory circuit RAM is performed using an address from the server side, and reading during a reproduction operation of the digital signal is performed using an address generated by the address counter AC.

Since the digital data stored in the storage circuit RAM as described above has been compressed as described above, the data conversion circuit expands it to the original data or performs processing as described below. The bit length can also be changed. The LPF is a low-pass filter, which is composed of a digital filter circuit, and inputs only band components necessary for reproduction to the digital/analog conversion circuit. In this embodiment, digital signals with a plurality of sampling rates are handled depending on information and programs, as will be described later. The passband of the digital filter is also switched according to these sampling rates. The digital/analog conversion circuit has a function of outputting analog signals of left and right channels separated into left and right channels in response to a stereo signal input in a time-sharing manner. Note that if the digital signal is a monaural signal,
The same analog signal is output from both channels. In order to reduce the size and weight of the player, audio output is performed through headphones. Outputs R and L are headphone terminals for this purpose.

FIG. 9 shows a plan view of an embodiment of the mounting board constituting the player. The player consists of a control board and a memory board. The control board has a power supply part into which a button battery is inserted and a connector part separated at both longitudinal ends, and the above-mentioned LSI, amplifiers AMP1 and AMP2, low-pass filter LPF, and digital/analog conversion circuit are installed on the surface of the board between them. D.A.
Each semiconductor integrated circuit device constituting C is mounted. The connector used is one that complies with the JEIDA standard (standard for memory cards, etc.). The power supply section is composed of a button battery holder, and for example, four alkaline button batteries (LR44) can be mounted therein. The size of this control board is
Although not particularly limited, the length is 52 mm and the width is 82 mm so that it can be stored in an existing IC card case. The memory board corresponds to the size of the control board excluding the relatively thick connector part and the part corresponding to the power supply part, and eight PSRAMs are mounted on each side of the control board. The memory board and the control board are connected by a flexible wiring board. In other words, the two substrates are arranged so that they can be spread out in order to facilitate inspection, repair, and the like.

FIG. 10 shows a side view of the mounting board housed in the case. A memory board is folded and superimposed on the surface of the control board excluding the power supply section and the connector section via a flexible wiring board. This makes it possible to store the card in a case similar to that of an existing IC card (RAM card), making it possible to realize a small and thin player.

FIG. 11 shows a block diagram of an embodiment of a power supply system for a player. As mentioned above, the player includes a storage circuit RAM, a control circuit CTL composed of a digital circuit, and a digital filter LP.
F and a digital/analog conversion circuit D as described below.
It is divided into CA and an amplifier circuit AMP that outputs an analog signal. Each of these circuit blocks has a different operating voltage. For example, the storage circuit RAM requires a relatively high operating voltage of about 4 V when using the above-mentioned pseudo-static RAM. On the other hand, digital circuits operate at a relatively low voltage of about 3V by using CMOS circuit gate arrays and the like. and,
The operating voltage of the amplifier circuit AMP that drives the headphones is even lower, at about 1.5V. From this,
Batteries E1, E2, and E3 are used to match the operating voltage of each circuit. Except for battery E1, which constantly supplies voltage for RAM information retention operation, batteries E2 and E3 are connected to power switches S2 and S3. It is supplied to each corresponding circuit via.

[0027] By using a plurality of types of batteries having different voltage values to directly supply power to the corresponding circuits, the battery life can be extended. For example, when the internal power supply is set to the highest level of 4V, wasteful current flows in the digital circuit and analog circuit AMP, increasing current consumption. Therefore, if the voltage of 4V is stepped down by an internal voltage down converter, the voltage down circuit also consumes current, which ultimately shortens the battery life. On the other hand, in this embodiment, since the minimum battery required for each circuit is selected and power is supplied to it, unnecessary current consumption can be suppressed and the actual battery life can be extended.

Furthermore, in order to write/read digital signals into/from the memory circuit RAM at high speed, the operating current of the memory circuit becomes large. Therefore, a power supply connector is provided in the server (terminal device), and an operating voltage of about 5 V, which is higher than the above-mentioned internal voltage, is supplied from there. In this case, in order to automatically switch the power between the battery side and the server side, the connector and battery
1 are connected to the memory circuit R via diodes D1 and D2, respectively.
This is to supply voltage to the AM power supply terminal. In this configuration, when the player is connected to the server, the diode D1 is turned on because the operating voltage on the server side is approximately 5V, which is higher than the approximately 4V of the battery E1, and the storage circuit R
AM is operated by operating voltage from the server side. At this time, the diode D2 on the battery E1 side is reverse biased and turned off, and no reverse current flows from the server connector to the battery E1. Then, when the player is removed from the server, the connector is opened, so that the diode D2 is turned on, and the voltage of the battery E1 is supplied to the memory circuit RAM. By adopting such a power supply system, data can be transferred to the storage circuit RAM at high speed, and the battery life of the player can be extended.

FIG. 12 shows the memory circuit RAM of the player.
A conceptual diagram of an embodiment of the storage area management method is shown. In this embodiment, a table of contents memory and a data memory are used to manage the storage of digital signals. The table of contents memory is capable of storing up to four types of digital signals (programs) such as table of contents 1 to table of contents 4. The table of contents memory contains the first address,
In addition to the ID code specifying the end address and reproduction conditions, table of contents information is also stored. Although this table of contents information is not particularly limited, it consists of character information, and the player is provided with a liquid crystal display device so that the contents of the program can be displayed in characters. Each table of contents in the table of contents memory and the data area in the data memory are arranged arbitrarily such as data 2, data 1, data 4, and data 3 from the start address side of the data memory depending on the storage order. That is, the digital signals are stored in the data memory in the order specified first.

FIG. 13 shows a block diagram of a main part of an embodiment of a player in which the table of contents function described above is added. The controller CTL is provided with a switch SW1 for specifying a table of contents (program specification) in addition to the switch SW2 for controlling the operation as described above. Although not particularly limited,
When this switch SW1 is turned on, a +1 pulse is supplied to the table of contents AC (address counter), and the table of contents memory is accessed. The table of contents information read from the table of contents memory is stored in a table of contents register, and characters such as titles are displayed on the LCD.

The start address read from the table of contents memory is set in the address counter AC of the data memory, and the end address and ID code are loaded into the register REG. The ID code is transmitted to the controller CTL, which decodes it and determines the sampling frequency,
Reproduction conditions such as data length and stereo/monaural reproduction are automatically set. The address signal output by the address counter AC is not only used for accessing the data memory but also supplied to the comparator CP. The other input of this comparator CP is connected to the register R.
The final address loaded into the EG is communicated. As a result, when the readout of the digital signals (data) corresponding to the specified table of contents is completed, the comparator CP detects this and inputs the end signal to the controller CTL, thereby completing the series of readout operations of the digital signals. It turns out.

In the table of contents function described above, the number of tables of contents can be any number other than 4, but if it is 2 to the N power, the selection becomes easier because the binary address counter can be used as is. Furthermore, if the table of contents memory is provided separately from the data memory, each can be accessed independently and in parallel, which simplifies the control of the address counter. It goes without saying that the table of contents memory described above may be constructed using a certain storage area of the data memory. For example, in the digital signal delivery system as described above, when a player is connected to a server, the server accesses the table of contents memory and reads the enabled block addresses. This allows the server to know the free space in the memory circuit RAM in the player. When a new digital signal to be transferred is designated, the block address is stored in the empty table of contents and the digital signal is stored in the empty area.

[0033] If the table of contents is insufficient or if there is not enough free storage capacity for the digital signals to be transferred, a message to that effect is displayed and the stored digital signal that can be erased is selected, and then it is erased. to input a new digital signal. At this time, the stored digital signals stored in the player are also read out, and address allocation is performed anew to match the storage capacity of the new digital signal so that there is no free space in the storage capacity. By having the server side manage the storage area of the player's memory circuit RAM in this manner, a relatively small storage capacity can be used efficiently, and control operations on the player side can be greatly simplified.

The effects obtained from the above examples are as follows. That is, (1) Find the difference between the previous sampling data and the input data, and if the difference is larger than the maximum value of the code to be compressed, output the maximum value, and if it is smaller, output the subtraction result. The compressed data is output and data compression is performed. This method has the advantage that data compression with high fidelity can be achieved using simple configurations such as subtraction and addition for data whose amplitude and frequency distribution are relatively gentle over time, such as acoustic signals. (2) According to (1) above, the data compression and expansion circuit can be realized by simple circuits such as subtracters, adders, registers, and comparators, and the power consumption thereof can also be kept low. (3) By using the data conversion method and circuit as described above, it is possible to achieve the effect that the player that reproduces the audio signals stored in the memory circuit can be made smaller and lighter.

Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say. For example, Figure 1
, instead of using a comparator to compare the subtracted output data D3 and the maximum value D4 of the data to be compressed,
An OR gate circuit or the like may be used to equivalently form a magnitude comparison output with the maximum value when any one of the upper bits of the subtracted output data D3 is 1. The difference data may be obtained by subtracting the input data D1 from the register data D2. The input signal to be data compressed may be one that uses the output signal of an analog/digital conversion circuit as in the embodiment shown in Figure 1, or one that uses digitally converted data that is once stored on a memory circuit, magnetic tape, or compact disk. Needless to say, it is possible. The compressed data may be converted into serial data and output via a communication line or the like. The data conversion method and data conversion circuit according to the present invention can be widely used in circuits and devices that handle digital data that changes over time.

[0036]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the difference between the previous sampling data and the input data is calculated, and if the difference is larger than the maximum value of the code to be compressed, the maximum value is output, and if it is smaller, the subtraction result is output and compressed. Output the data and perform data compression. With this method, for data whose amplitude and frequency distribution are relatively stable over time, such as acoustic signals, high-fidelity data compression can be performed using simple configurations such as subtraction and addition. , can be realized using simple circuits such as registers and comparators.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data conversion circuit configured using a data conversion method according to the present invention.

FIG. 2 is a waveform diagram for explaining an example of an analog/digital conversion operation accompanied by a data compression operation in the embodiment of FIG. 1;

FIG. 3 is a block diagram showing another embodiment of a data conversion circuit configured using the data conversion method according to the present invention.

FIG. 4 is a block diagram of main parts showing an embodiment of a digital signal delivery system using the data conversion method and data conversion circuit according to the present invention.

FIG. 5 is a block diagram of an input unit of the terminal device in FIG. 4;

FIG. 6 is a block diagram of a storage unit of the terminal device in FIG. 4;

FIG. 7 is a block diagram of an output unit of the terminal device in FIG. 4;

FIG. 8 is a block diagram showing an embodiment of a player used in the digital signal delivery system.

FIG. 9 is a plan view showing an example of a mounting board constituting the player.

FIG. 10 is a side view showing an embodiment of the mounting board in a state covered by a case.

FIG. 11 is a block diagram showing an embodiment of a power supply system for a player.

FIG. 12 is a conceptual diagram of an embodiment of a storage area management system of a memory circuit RAM built into the player.

FIG. 13 is a block diagram of main parts showing an embodiment of a player in which the table of contents function of FIG. 12 is added.

[Explanation of symbols]

LPF...low pass filter, MPX...multiplexer,
S/H...sample & hold circuit, ADC...analog/
Digital conversion circuit, INCT...input controller,
NIF...Network interface, CPU...Microprocessor, ROM...Read-only memory,
RAM...Random access memory (memory circuit),
HDDC...hard disk controller, LCDC...L
CD controller, VMEINF...VME bus interface, HDD...hard disk memory, LCD...liquid crystal display device, OUTINF...output interface, P
CTL...Player control circuit, BM...Buffer memory, M
OCTL...monitor control circuit, MONT...monitor circuit, DC...data conversion circuit, AC...address counter, CTL...controller, LSI...large-scale integrated circuit (gate array), DAC...digital/analog conversion circuit, AMP, AMP1, AMP2 ...Amplification circuit, BAT
...Power supply circuit, S2, S3...Power switch, E1-E3...
Battery, SEL...selector.

Claims (5)

[Claims] [Claim 1] Calculate the difference between the previous sampling data and the input data, and if the result is larger than the maximum value of the code to be compressed, output the maximum value of the data to be compressed, and if it is smaller, the difference is calculated. A data conversion method characterized in that a subtraction result is output based on the compressed data. 2. The data conversion method according to claim 1, wherein the compressed data is expanded to the original data by being added to the previous sampling data. [Claim 3] Input data and 1 stored in the register
A subtraction circuit that calculates the difference from the previous sampling data, a comparator that compares this subtraction output with the maximum value of the data to be compressed, and when the subtraction output is larger than the maximum value based on the output of this comparator, the maximum value and a selector that outputs the subtracted output based on compressed data when the subtracted output is smaller than the maximum value. 4. The register takes in the output signal of an adder circuit that adds the compressed data output from the selector and the previous data stored in the register as the previous sampling data. 4. The data conversion circuit according to claim 3, characterized in that: [Claim 5] Calculate the difference between the previous sampling value and the input sampling data, and if the result is larger than the maximum value of the data to be compressed, it is taken as the maximum value, and if it is smaller, it is not compressed. As a decompression circuit for compressed data that is the result of subtraction using data, a register with a bit length corresponding to the original data is added, and the output signal of this register is added to the compressed data, and the new data in the register is added. an addition circuit that forms data,
A data conversion circuit characterized in that it obtains decompressed data from the output of the adder circuit or register.