JPH04273721A - High-speed frequency synthesizer - Google Patents

Abstract

PURPOSE:To accelerate the pull-in speed of a PLL system and to shorten a time required for the selective switching of a channel by adding a voltage of pulse width set in advance to a low-pass filter at the time of selectively switching the channel, then returning to a stationary loop. CONSTITUTION:A variable pulse generator 7 on which an input voltage in accordance with the output frequency of a voltage controlled oscillator 5 to be selectively switched is set in advance, and which generates a voltage of pulse width in accordance with the above prescribed voltage when a change-over switch 3 is connected synchronizing with channel switching is provided at the PLL system, thereby, lock-up time can be shortened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer with reduced lock-up time, which can be used in frequency synthesizers for car-mounted telephones, mobile radios, etc.

Generally, a frequency phase locked (PLL) circuit is
If a 1/N frequency divider (N is the frequency division number) is inserted between the voltage controlled oscillator (VCO) and the phase comparator (P/C), the above V
The oscillation frequency of CO is N times the output frequency (reference frequency) of the reference oscillation source, but the above P/C is equal to the reference frequency and the above V
The phase difference with the frequency obtained by dividing the CO output frequency by N is detected, the smoothed DC voltage is passed through a low-pass filter (LPF), and the smoothed DC voltage is added as a control voltage for the VCO output frequency. is operated so that it matches the phase of the reference frequency.

By the way, when selecting and switching between multiple channels,
In the LL synthesizer, the switching time between channels becomes longer in proportion to the number of channels. In addition, if the channel spacing is narrow, the reference frequency cannot be set too high in order to minutely change the VCO output frequency, and the PLL
In order to maintain the stability of , it is necessary to set a large time constant of the LPF.

However, it takes a long time for the frequency to become stable when switching channels, and it becomes difficult to switch the output frequency of the VCO at minute frequency intervals. become an obstacle.

[0005]

[Problems to be Solved by the Invention] In view of the above-mentioned conventional problems, the present invention aims to control the frequency of multiple channels stably and at high speed with fine channel spacing using extremely small parts in the configuration of an ultra-compact radio device. It is possible to obtain a frequency synthesizer.

[0006]

[Means for solving the problem] A changeover switch provided on the output side of a phase comparator is connected to a pulse width voltage wave corresponding to the DC voltage of an LPF that changes the output frequency of a voltage controlled oscillator in synchronization with frequency switching. , is added to the input side of the low-pass filter.

[0007]

[Embodiment] Fig. 1 is a block diagram of a high-speed frequency synthesizer according to the present invention, in which 1 is a fixed oscillator that oscillates the reference frequency fr, 2 is a phase comparator (P/C), and 3 is a stationary loop and a high-speed loop. For each period, a changeover switch switches between a and b contacts, 4 is a low-pass filter (LPF), 5 is a voltage controlled oscillator (VCO), 6 is a variable frequency divider with a frequency division number N (1
/N), 7 is a variable pulse width generator (VPWC), and 8 is a CPU for controlling.

With the circuit configuration described above, when the output frequency fD of the VCO is to be switched at each channel switching point as shown in FIG. 3, and the contact of the changeover switch 3 is switched from b to a at point P1, The variable pulse width generator 7 as shown in FIG. 3 outputs an output pulse as shown in FIG. 3(B), and the DC voltage (C) smoothed by the low-pass filter 4 is applied to the input terminal of the VCO 5. Therefore, it is rapidly pulled into the lock range during the high-speed lock-up period shown in Figure 3(A), and when the changeover switch is connected to the a contact at this point, it is returned to the steady loop shown in Figure 3(A), and the above-mentioned The input voltage of the VCO 5 reaches the target output frequency and the PLL system is locked. A voltage waveform as shown in FIG. 3(D) is applied to the input terminal of the VCO in a conventional PLL.

Next, the variable pulse generator will be explained with reference to FIG. 2. Each part of the wireless transceiver (not shown) and P
A digital signal is sent from a control unit such as the CPU that sends commands to each part in the LL system to the clock, load, and data terminals via a gate or directly, and in synchronization with the changeover switch 3 in the PLL system. By applying a command to a switch that can be changed over, a pulse wave as shown in Fig. 3 (B) is generated at t1 to the b contact of the changeover switch.
and t2 period, V through the low-pass filter LPF
Added to CO5.

The pulse height and width of the pulse width voltage wave output from the variable pulse width generator are determined from volt-seconds which is equal to the DC voltage to be applied during the high-speed lock operation of the VCO.

[0011]

Effects of the Invention Thus, the present invention allows the input voltage corresponding to the VCO output frequency to be varied to be changed from the output of the preset variable pulse width generator to the changeover switch provided in the PLL system in synchronization with channel switching. As soon as the predetermined voltage is reached, the circuit is immediately disconnected and returned to the steady lock-up state, making it possible to achieve frequency phase synchronization that quickly responds to selective switching of multi-channel frequencies. PL by mutual switching from state to state or fast state.
It does not cause any disturbance to the L system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a high-speed frequency synthesizer according to the present invention.

[Figure 2] Variable pulse width generator (VPWC) in Figure 1
Detailed circuit diagram.

FIG. 3 (A) is a time-series time chart of the PLL system in steady state and high speed state. (B) is an output pulse waveform graph of the variable pulse width generator. (C) is a graph of the output voltage waveform of the low-pass filter. (D) is the conventional P without adding the output of the variable pulse width generator.
LL low-pass filter output voltage waveform graph.

[Explanation of symbols]

1 Fixed oscillator 2 Phase comparator (P/C) 3
Selector switch 4 Low pass filter (LPF) 5
Voltage controlled oscillator (VCO) 6
Variable frequency divider (1/N) 7
Variable pulse width generator (VPWC) 8
CPU

Claims (1)

[Claims] Claim 1: A PLL circuit configured such that the output frequency of a voltage controlled oscillator matches the phase of a reference frequency,
A changeover switch that turns on and off the phase comparison output between the reference frequency and the feedback frequency of the voltage-controlled oscillator in synchronization with the variable timing of the output frequency of the voltage-controlled oscillator, and another contact of the changeover switch. and a variable pulse width generator that applies a pulse width voltage wave to the input side of the low-pass filter so as to be equal to the control voltage corresponding to the target output frequency of the voltage controlled oscillator to be varied. A high speed frequency synthesizer.