JPH04273461A - Burn-in testing method - Google Patents

Abstract

PURPOSE:To provide a burn-in testing method which unnecessitates a burn-in board, enables increase of the number of accommodated devices to be tested within a burn-in apparatus container more than that required in the conventional method, eliminates generation of damages on packages, etc., and improves quality and reliability of products. CONSTITUTION:The burn-in test can be realized by applying temperature and electrical stresses under the wafer condition.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention can be applied to a burn-in test method commonly used in testing semiconductor elements and integrated circuit devices in order to eliminate early failures of semiconductor elements and integrated circuits. In particular, the present invention relates to a burn-in test method that can eliminate the need for a burn-in board.

[0002] Burn-in tests are intended to remove early failures by applying temperature and electrical stress to the device under test to accelerate progressive failures. Conventionally, this test was performed on the final product form after the device package assembly process, so it was necessary to prepare a socket for storing the device according to the package type and pin arrangement. It is necessary to create This test is performed by mounting the device under test on a burn-in board, storing it in a burn-in equipment tank, and supplying an electrical signal. In this case, the fewer the types of burn-in boards, the better, and the greater the number of devices under test mounted on one burn-in board, the more advantageous it is in terms of cost and operation. In addition, the work of mounting the device under test on the burn-in board (refilling it to the burn-in board) before and after the burn-in test, and the work of extracting the device under test from the burn-in board (removal) have become extremely man-hour-intensive due to the diversification of packages in recent years. At this time, package damage such as lead bending is likely to occur and frequently occurs.

[0003] Therefore, there is a need for a burn-in test method that does not require a burn-in board, can increase the number of packages stored in a burn-in device tank than in the past, and can reduce the likelihood of package damage.

0004

2. Description of the Related Art First, a conventional burn-in test device will be explained. FIG. 5 is a schematic diagram showing the configuration of a conventional burn-in test device. In FIG. 5, 31 is the main body of the apparatus, and 32 is a door for taking the burn-in board 33 into and out of the thermostatic chamber 34. Bar in board 33 here
is connected to a connector 35 inside the constant temperature bath 34. 36
37 is a socket for mounting a device to be measured on the bar-in board 33; 37 is a power source for a heater 38 in a thermostatic oven 34; a fan 39 sends hot air into the thermostatic oven 34; Electrical stress is applied to the device under test on the burn-in board 33 from a power source 40, a pattern generator 41, and a driver 42 via a connector 35. The power supplies 37, 40, pattern generator 41, and other general functions within the device are controlled by a host computer 44 via a control bus 43.

Next, a conventional burn-in test method will be explained. FIG. 6 is a diagram showing a conventional burn-in test and the steps before and after it. In conventional burn-in testing, first, the package type, form, and
We develop and manufacture sockets and burn-in boards for each different power/GND pin arrangement. Next, after the device under test is packed into the socket on the burn-in board using an automatic machine or manually (A2), the burn-in board is placed into the burn-in equipment tank to apply temperature and electrical stress, and the electrical signal is applied. The burn-in board is connected to the supply connector section, and after applying a specified temperature and electrical stress for a specified period of time (A3), the burn-in board is taken out from the burn-in device tank. next,
The device under test is removed from the socket on the burn-in board using an automatic machine or manually (A4) and transferred to a container such as a tray or container for processing in the next process (post-burn-in test; normal pre-burn-in or higher test). ). The A3 burn-in test is a test to eliminate early failures by accelerating progressive failure by applying temperature and electrical stress, and the A5 post-burn-in test is to reconfirm non-defective products and eliminate defective products. This is the test.

[0006]

[Problems to be Solved by the Invention] However, in the conventional burn-in test method described above, it is necessary to develop and manufacture sockets and burn-in boards for each device under test that has a different package type, form, and power/GND pin arrangement. This requires a huge amount of man-hours and costs for preparation and management during operation, and since the device under test is in the form of a final product after the package assembly process, it is necessary to mount large components such as sockets on the burn-in board. Therefore, the number of devices under test mounted on one burn-in board was small.

For this reason, when burning in a large number of devices under test, a large number of burn-in boards and a large number of burn-in devices are required, which requires an enormous amount of installation space. This had a particularly large effect on large packaged products.

[0008] In addition, it takes a lot of man-hours to insert and remove the device under test into the socket on the burn-in board, and furthermore, the package and leads may be damaged due to mechanical stress during insertion and removal, and the circuit of the device under test may be destroyed due to static electricity, resulting in product quality problems. , which caused a decrease in reliability.

Accordingly, the present invention makes it possible to eliminate the need for a burn-in board, increase the number of devices under test stored in the burn-in equipment tank than before, and prevent damage to packages, etc. can,
The purpose is to provide a burn-in test method that can improve product quality and reliability.

0010

Means for Solving the Problems In order to achieve the above object, the burn-in test method according to the present invention performs a burn-in test in a wafer state by applying temperature and electrical stress.

[0011]

[Operation] In the present invention, as shown in FIG. 1, a burn-in test (A4
), it is possible to eliminate the need for a burn-in board, and it is possible to increase the number of devices under test stored in the burn-in device tank compared to the conventional case. Moreover, since a burn-in board is not required, it is possible to prevent damage to the package etc. due to mechanical stress when inserting and removing the device under test from the socket on the burn-in board when using a conventional burn-in board. can.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. FIG. 1 is a diagram illustrating a burn-in test method according to an embodiment of the present invention. The burn-in test method will be explained using this figure. Note that the case of static burn-in will be explained here.

First, after the wafer test (a1), burn-in wiring is performed on the wafer in order to re-metal wire the valid chips and form burn-inable electrodes in the wafer state (a2). The burn-in wiring here is shown in FIG. In FIG. 2, 21 is a ground potential, 22 is a ground electrode for contacting the burn-in device, 23 is a power supply potential, 24 is a power supply electrode for contacting the burn-in device, and 25 is an orientation flat portion 26
(abbreviation for orientation flat) is the intersection of the wafer tangent and serves as a positioning reference when arranging wafers on the burn-in tray. 27 is a peripheral ground.

FIG. 2 shows an example in which the ground electrode, power supply electrode wiring, and contact pad of each chip are formed of metal wiring for burn-in. Wiring is performed in a dedicated wiring area using conventional sputtering or vapor deposition techniques. However, in order to ensure the effective number of chips, the original chip area may be avoided and the wiring may be placed in the scribe line area or in the non-effective area around the wafer. The ground electrode of the burn-in wiring is connected to all chips and is common, but the power supply section is wired independently for each chip, and the contact pads are also separated from each other to enable electrical isolation. The total number of power supply electrodes 24 is required to be equal to or greater than the effective number of chips on the wafer, but by making the total number of electrodes the same for each wafer size, the contact board on the burn-in device side can be shared for each wafer size. or,
By concentrating contact pads and burn-in wiring at an appropriate position in the center instead of at the periphery of the wafer, it is possible to use a common contact board on the burn-in device side even if the wafer sizes are different. Here, the physical position of the electrode is determined based on the intersection 25 between the orientation flat portion 26 and the wafer tangent.

By the way, a chip determined to be defective in a wafer test may have an electrical short mode in its internal circuit, and when a burn-in test is performed, an overcurrent flows to the defective chip, causing device destruction or chip burnout. To prevent this, during the burn-in test, defective chips are electrically isolated by opening their corresponding power supply electrodes. The open/connection of individual electrodes is controlled by relays within the burn-in device.

Further, although the wiring portion shown in FIG. 2 needs to be removed after the burn-in test is completed, it is automatically removed during scribing and chip separation in the chip processing step a6 shown in FIG. Transferring to the burn-in board a5 shown in FIG. 1 is performed by placing m wafers on a special tray with the same direction, and by fixing the orientation flat part 26 and the wafer connection to a positioning guide provided in advance. Unlike packages, transfer can be done easily and in a short time because it is done on a wafer basis.

That is, in this embodiment, as shown in FIG. 1, the burn-in test is performed in the wafer state before the chip processing or assembly process, so the burn-in board can be eliminated, and the burn-in equipment can be used more easily than before. The number of devices under test stored in the tank can be increased. Moreover, since a burn-in board is not required, it is possible to prevent damage to the package etc. due to mechanical stress when inserting and removing the device under test from the socket on the burn-in board when using a conventional burn-in board. It is possible to improve product quality and reliability.

Next, the burn-in test device used in the above-described burn-in test method will be explained. FIG. 3 is a schematic diagram showing the configuration of a burn-in test device according to an embodiment of the present invention. In FIG. 3, 1 is a burn-in module; 2 is a burn-in module;
3 and 4 are the control bus and host computer that control each function within the apparatus.

The burn-in test device here is based on a burn-in module, and consists of a plurality of burn-in modules 1, each of which is controlled by a host computer 4. Then, the tray carrying the wafer to be measured is placed in a thermostatic chamber within the burn-in module 1, and a burn-in test is performed.

Next, the principle of the burn-in module will be explained. FIG. 4 is a diagram illustrating the principle of a burn-in module and the entire device according to an embodiment of the present invention. In FIG. 4, the same reference numerals as those in FIG. 3 indicate the same or equivalent parts, and the burn-in module 1 consists of Bj (j=l to k) pieces, each of which stores one burn-in tray 5 in this embodiment. , wafers 6 (Fl to Fm) on this tray 5
is the contact pin 15 (Jl~J) of the contact board 7.
Electrical stress is applied from the terminals n..Hl to Hn). Relay 8 (Dl~Dn, El~En)
controls the connection/opening of the contact pins 15, and its signals/data are sent from the host computer 4 through the control bus 3 and multiplexer 9. And 10(Aj (j=l~k)
) is a device power supply supplied to the wafer to be measured 6 of each module, 11 (Nj (j=l to k)) is a heater power supply of each module 1, 12 is a guide pin, and 13 is a constant temperature bath. Here, the volume of the constant temperature chamber 13 in the burn-in module 1 (Bj) in which the wafers to be measured 6 are placed is made small in order to facilitate dust prevention and temperature control, and the number of trays 5 on which the wafers 6 are placed is also limited (here (1 sheet in the example).

For the same reason, the method for heating (or cooling) the wafer 6 is to use a metal block 1 made of aluminum, copper, etc.
The tray 5 on which the wafers 6 are mounted is heated (or cooled) by heating (or cooling) the tray 5 on which the wafers 6 are mounted, rather than the hot air (or cold air) blower method of a normal burn-in device. However, in order to prevent oxidation of the wafers 6, the inside of the tank is purged with nitrogen gas, and the tray 5 is placed in the module inlet 2 (
Enter from Rj). On this tray 5, m wafers 6 are placed and fixed in advance at predetermined positions.

The contact pins 15 of the contact board 7 and the contact pads on the wafer 6 are aligned in the module 1 by inserting them into the guide holes of the tray 5 corresponding to the guide pins 12 (Kj, Lj) of the contact board 7. Do by doing. Next, after the tray 5 is inserted, the metal block 14 of the stand is raised, and the tray 5 moves appropriately to enable self-alignment with the guide pins 12 and guide holes. The contact pins 15 and guide pins 12 of the contact board 7 are aligned in advance, and contact the contact pads of the wafer 6 at the same time when the tray 5 and the contact board 7 come sufficiently close to each other. The contact pins 15 each control the power opening/connection of each chip to be measured by the relay 8 . A signal is sent to the relay 8 by the multiplexer 9 so that only good chips are connected. The map data of the wafer test (coordinate data of good chips) is converted by the host computer 4 to generate an input signal to the multiplexer 9 for relay control, and is sent via the control bus 3. In addition, heater (or cooling) power supply 1
1. Other general functions such as the power supply 10 (Aj) for supplying to the chip under test are the same as those of the conventional burn-in test apparatus.

In this embodiment, a static burn-in case in which only the power supply is supplied to the chip under test has been described, but the present invention is not limited to this, and dynamic burn-in can be performed by supplying a normal signal from a pattern generator. It can also be easily applied in the case of

[0024]

[Effects of the Invention] According to the present invention, it is possible to eliminate the need for a burn-in board, increase the number of devices under test stored in the burn-in equipment tank than before, and prevent damage to packages, etc. You can do it like this,
This has the effect of improving product quality and reliability.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating a burn-in test according to an embodiment of the present invention.

FIG. 2 is a diagram showing burn-in wiring according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing the configuration of a burn-in test device according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating the principle of a burn-in module and the entire device according to an embodiment of the present invention.

FIG. 5 is a schematic diagram showing the configuration of a conventional burn-in device.

FIG. 6 is a diagram showing a conventional burn-in test and steps before and after the burn-in test.

[Explanation of symbols]

1 Burn-in module 2 Door 3 Control bus 4 Host computer 5 Tray 6 Wafer 7 Contact board 8 Relay 9 Multiplexer 10, 11 Power supply 12 Guide pin 13　　　　Thermostatic chamber 14 Metal block 15 Contact pin 21 Ground potential 22 Ground electrode 23 Power supply potential 24 Power supply electrode 25 Intersection 26 Orientation flat part

Claims (1)

[Claims] 1. A burn-in test method comprising performing a burn-in test in a wafer state by applying temperature and electrical stress.