JPH0427234A - Serial data discriminating circuit - Google Patents

Abstract

PURPOSE:To obtain the discriminating signal being free from a discrimination error by executing the control so that phases of a synchronizing signal (discrimination clock signal) and a serial logical signal (input data signal) have a margin before an FF circuit latches erroneous data. CONSTITUTION:A serial logical signal (input data signal) (a) and a synchronizing signal (discrimination clock signal) (b) inputted to a phase detecting circuit 12 are converted to signals (c), (d) and (e) by delaying circuits 5 - 7, and inputted to F/F circuits 9, 10 and 8. The circuits 8 - 10 output latch signals (h), (g) and (f) of the signals (a), (c) and (d) by synchronizing with the discrimination clock signal (e). When a phase margin of the signals (c), (e) or the signals (d), (e) becomes below t0 time, the circuit 8 or 10 latches data being different from the circuit 9. The latch signal (g) of the signal (c) is a discriminating signal. The signals (f), (g) and (h) are inputted to a comparing circuit 11, and the circuit 11 outputs a signal (j) of H for showing a fact that a phase margin of the signal (c) does not exist from a terminal 3 to the signal (e) being an output of the circuit 7, and when a phase margin of the signal (d) does not exist with respect to the signal (e), a signal (k) of H is outputted to a terminal 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a serial data receiving circuit, and more particularly to a serial data discrimination circuit that discriminates serial logic signals using synchronization signals.

[Conventional technology]

An example of a conventional 7 real data discrimination circuit is shown in FIG. 5 and will be described.

In the figure, 21 is a data input terminal, 22 is a discrimination clock input terminal, and 23 is a discrimination data output terminal from which a discrimination signal g is obtained.

As shown in FIG. 5, the conventional serial data discrimination circuit includes a flip-flop 24 that latches serial data (serial logic signal) a using a sampling clock (synchronization signal) b, and samples the center of the serial data pit cell. It has delay lines 25 and 26 for adjusting the phases of the serial data a and the sampling clock b in advance so that the phase of the serial data a and the sampling clock b are adjusted in advance.

FIGS. 6(a) to 6(c) are waveform diagrams showing waveforms at each point in FIG. In this FIG. 6, PD indicates phase delay.

[Problems to be Solved by the Invention] The conventional serial data discrimination circuit described above has no problem during low-speed data transfer when there is sufficient phase margin between the discrimination clock and the data signal. This example is shown in FIG. 5, and the waveforms at each point are shown in FIG. The discrimination clock numbers I to ■ shown in FIG. 6 are waveforms when there is a phase margin. but,
In the case of high-speed data transfer, there is a problem in that discrimination errors occur when the phase margin becomes insufficient due to factors such as data signal drift and temperature drift in circuit element characteristics. This mode is shown by discrimination clock numbers ① to ② in FIG.

[Means to solve the problem]

The serial data discrimination circuit of the present invention includes a discrimination circuit that discriminates a first serial logic signal using a first synchronization signal, and a second serial logic signal that is delayed by a first predetermined time and a second predetermined time. serial logic signal and the third
a first and a second serial logic signal, respectively.
a third delay circuit that generates a second synchronization signal by delaying the first synchronization signal by a first predetermined time; and a third delay circuit that uses the first, second, and third serial logic signals as data signals. , the first . second and third flip-flop circuits; The respective output signals of the second and third flip-flop circuits are compared, and the first and second
The output signal of the flip-flop circuit is equal to its third
output a first new signal when the output signals of the flip-flop circuits are different, and the output signals of the second and third flip-flop circuits are equal to the output signals of the first flip-flop circuit. a comparator circuit that outputs a second new signal when the first serial logic signal and the first synchronization signal are different; The first new signal or the second new signal is inputted so that the phase of the first serial logic signal with respect to the first synchronizing signal is changed from the first and second original signals of the synchronizing signal. a signal generating means for generating the first serial logic signal delayed or advanced by a preset time each time, the first synchronization signal; and the second flip-flop circuit. It is provided with a signal output means for outputting the output signal as a discrimination signal.

[Effect]

In the present invention, even if the phase margin between the serial data and the discrimination clock signal is no longer sufficient due to factors such as temperature drift or data signal drift, the flip-flop circuit 9 in FIG. The synchronization signal (discrimination clock signal) b and the serial logic signal (input data signal) a are controlled to have a phase margin.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the serial data discriminator circuit according to the present invention.
Serial logic signal) a and discrimination clock signal (synchronization signal)
3 shows a configuration example of a phase detection circuit that detects a phase margin of b.

In FIG. 1, 1 indicates a serial data input terminal, 2 indicates a discrimination clock input terminal, and 3 and 4 indicate phase margin detection signal output terminals.

5 and 6 are the serial logic signal (input data signal) a to
A delay circuit that generates signals c and d delayed by time and 2to time, respectively, 7 is a synchronization signal (discrimination clock signal) b
8, 9. 10 is a serial logic signal (input data signal) a.

This serial logic signal (input data signal) a is input to t.

A time-delayed signal C, a signal d obtained by delaying the serial logic signal (input data signal) a by 2to time are used as data signals,
synchronization signal (discrimination clock signal) b to t.

A flip 70-tub circuit (hereinafter referred to as an F/F circuit) inputs the time-delayed signal e as a clock signal, and 11 is a latch signal f which is each output signal of the F/F circuits 8, 9 and 10. , g, h, respectively, and F/
When the output signals of F circuits 10 and 9 are equal and the output signal of F/F circuit 8 is different, a new signal j is output, and
74゛749.8 output signals are equal F/F circuit 10
This is a comparator circuit that outputs a new signal k when the output signals of the two are different.

Reference numeral 17 denotes a discrimination signal output terminal connected to the output end of the F/F circuit 9, and these constitute signal output means for outputting the output signal of the F/F circuit 9 as a discrimination signal.

FIG. 2 is a block diagram showing an example of the overall configuration of a serial data discrimination circuit according to the present invention.

In FIG. 2, the same symbols as in FIG. 1 indicate corresponding parts, and 12 is a serial logic signal (input data signal) a.
This is a phase detection circuit that detects the phase margin of the synchronization signal (discrimination clock signal) and the synchronization signal (discrimination clock signal) b. 13 is a programmable delay circuit that inputs the data signal from the serial data input terminal 15 and new signals j and k from the phase detection circuit 12 as control signals and outputs a serial logic signal (input data signal) a; 14 is a discrimination circuit; This is a delay circuit that receives the clock signal from the clock input terminal 16 and outputs a synchronization signal (discrimination clock signal) b, and these are input stages for the serial logic signal (input data signal) a and synchronization signal (discrimination clock signal) b. , and from the original signals of the serial logic signal (input data signal) a and the synchronization signal (discrimination clock signal) b, the serial logic signal (input data signal) a with respect to the synchronization signal (discrimination clock signal) b is A signal that generates a serial logic signal (input data signal) a and a synchronization signal (discrimination clock signal) b whose phase itself is delayed or advanced by a preset time each time a new signal j or k is input. It constitutes a generation means.

In this way, the phase detection circuit 12 shown in FIG. 2 has a delay circuit 5 that generates signals c and d by delaying the phase of the serial logic signal (input data signal) a by to time and 2t.
, 6, and the phase of the synchronization signal (discrimination clock signal) b is t.

A delay circuit 7 that generates a signal (discrimination clock signal) e whose phase relationship between the serial synchronization signal (input data signal) a and the synchronization signal (discrimination clock signal) b is equivalent to the signal C by time delay, and the signal -e. Compare the output levels of the three F/F circuits 8.9.10 that latch the serial logic signals (input data, evening signals) a, signals c, and d at the start-up stage with the output levels of these b-chome streets 8-10. The comparator circuit 11 is composed of υ.

3(a) to 3(j) are waveform diagrams showing waveforms at each point in FIG. 1, and FIGS. 4(a) to 4(e) are waveform diagrams showing waveforms at each point in FIG. 2.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained with reference to FIGS. 3 and 4.

First, the serial logic signal (input data signal) a and the synchronization signal (discrimination clock signal) b input to the phase detection circuit 12 shown in FIG.
are converted into the phase-related signals c, d, and e described above,
Each is input to the F/F circuit 9°10.8.

These F/F circuits 8 to 10 latch signals a, c, and d in synchronization with the discrimination clock signal e.
However, when the phase margin between the signal C and the discrimination clock signal e or between the signal d and the discrimination clock signal e becomes less than the time to, the F/F circuit 8 or the F/F circuit 10 outputs the F/F circuit 8 or 10.
/F circuit 9 and latches different data. Here, the latch signal g of the signal C is a discrimination signal.

These latch signals f, g, h are input to the comparison circuit 11,
The comparison circuit 11 outputs a high level signal j from the phase margin detection signal output terminal 3 indicating that there is no phase margin of the signal C with respect to the discrimination clock signal e which is the output signal of the delay circuit 7, When there is no phase margin for the signal d with respect to the signal e, a high level signal k is output to the phase margin detection signal output terminal 4.

Next, the overall operation of the serial data discrimination circuit of the present invention will be explained with reference to FIG.

A high level signal j, which is the phase margin detection signal mentioned above,
is input as a control signal to the programmable delay circuit 13. If the serial logic signal (input data signal) a is ahead in phase with respect to the synchronization signal (discrimination clock signal) b, this programmable delay circuit 13 is set in advance for each input of a high-level signal j, which is a control signal. Serial logic signal (input data signal) a for the time Δ
It operates to delay the phase of the signal, and to advance the phase in the opposite case.

〔Effect of the invention〕

As explained above, the present invention allows the F/F circuit 9 in FIG. Before latching the data, synchronization signal (discrimination clock signal) b and serial logic signal (
Since the phase of the input data signal (a) is controlled to have a margin, there is an effect that a discrimination signal g without discrimination errors can be obtained from the output terminal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the serial data discrimination circuit according to the present invention, FIG. 2 is a block diagram showing an example of the overall configuration of the serial data discrimination circuit according to the present invention, and FIG. 4 is a waveform diagram showing the waveforms at each point of the second circuit, FIG. 5 is a block diagram showing an example of a conventional serial data discriminator circuit, and FIG. FIG. 3 is a waveform diagram showing waveforms. -'...2,') 1...-serial arter input terminal, 2...discrimination clock input terminal, 3, 4...phase margin detection signal output terminal, 5-7...delay Circuit, 8-10...F/
F circuit (flip-flop circuit), 11... Comparison circuit, 12... Phase detection circuit, 13... Programmable delay circuit, 14... Delay circuit. Patent Applicant NEC Corporation Agent Masaki Yamakawa Fig. 1 Fig. 2 Fig. 2 (e) )

Claims (1)

[Claims] In a discrimination circuit that discriminates a first serial logic signal using a first synchronization signal, the first serial logic signal is
first and second delay circuits that generate a second serial logic signal and a third serial logic signal delayed by a predetermined time and a second predetermined time, respectively; a third delay circuit that generates the second synchronization signal; and first, second, and third delay circuits that input the first, second, and third serial logic signals as data signals and the second synchronization signal as a clock signal, respectively. The third flip-flop circuit is compared with the output signals of the first, second and third flip-flop circuits, and it is determined that the output signals of the first and second flip-flop circuits are equal. a first new signal is output when the output signals of the flip-flop circuits are different, and the output signals of the second and third flip-flop circuits are equal; a comparison circuit that outputs a second new signal when the first serial logic signal and the first synchronization signal are different; from the first and second original signals of the synchronization signal of the first synchronization signal.
the first serial logic signal whose phase itself is delayed or advanced by a preset time each time the first new signal or the second new signal is input; A serial data discrimination circuit comprising: signal generation means for generating the first synchronization signal; and signal output means for outputting the output signal of the second flip-flop circuit as a discrimination signal.