JPH0427220Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a circuit that prevents latch-up occurring in a switch circuit (abbreviated as CMOS SW or _U2 ) composed of CMOS FETs.

Currently commercialized CMOS SWs are usually used with a single power supply voltage. In other words, add 0V to one power supply terminal V _EE and apply +15V to the other terminal V _DD .
Or used with 6V added. When using this
The signals switched by CMOS SW are approximately
Constrained by voltage range between V _DD and V _EE . For example, the output of operational amplifier U ₁ included in a resistive temperature transducer
When E ₂ is led to a CMOS SW and switched (see Figure 1), when U ₁ is driven by two power supplies of ±15V, for example, E ₂ is in the range of 1 to 5V during normal operation.
Although the voltage is higher than 0V, when the input of U ₁ is open,
When switch S is switched to swing the output of _U2 to its upper limit or lower limit, there is a possibility that a signal voltage of 0V or less will be applied to the switch input and output of _U2 . As shown in the figure, the cathode of diode D is connected to the output terminal 2 of the amplifier, and the voltage of E ₂ is approximately -0.6 to -0.7V.
clipped to At this time, if the potential at the V _EE end of the CMOS SW is 0V, the switch input voltage E ₂ is V _EE
If the voltage drops below the potential, a latch-up phenomenon will occur in the CMOS SW, causing the input/output wiring or power supply line to melt. In order to prevent this phenomenon, it is necessary to keep the potential of V _EE at a potential lower than that of the input signal E ₂ . _One way _to do this is to use _{a voltage} -V _S (-
_{A circuit ( No.} (see Figure 2), and the negative power supply voltage terminal - as shown in Figure 3.
Diode D and current limiting resistor between V _S and G
A circuit in which a series circuit of R ₁ is inserted and the voltage at the connection point 4 between D and R ₁ is applied to the V _EE terminal, or a current limiting resistor R ₁ is inserted between -V _S and G as shown in Figure 4. A circuit has been proposed in which a Zener diode _DZ is inserted and the voltage at the connection point 4 between _DZ and _R1 is applied to _VEE , but all of these circuits have the following drawbacks. In other words, when the switch S of the CMOS SW is switched, a large current I (about several mA) flows out from the V _EE terminal, so in the circuit shown in Figure 2, that current flows through the resistor.
The potential of V _EE , which is shunted to R ₁ and R _2, rises to 0V or higher, and there is a possibility that the U ₂ switch will latch up due to its relationship with the switch input signal E ₂ . _VEE
If the values of R ₁ and R ₂ are made small in order to suppress the rise in the potential of , the current that constantly flows through these resistors becomes large, which has the disadvantage of increasing power consumption.
In the circuit shown in Figure 3, as in the circuit shown in Figure 2, when switch S is switched, current flows through _{R1 and} V _EE increases.
If the voltage exceeds 0V, the cause of the latch-up will not be resolved. In the circuit shown in FIG. 4, when the Zener voltage of the Zener diode _DZ is _VZ , the potential of _VEE is maintained at _-Vz . Also, when switch S is switched, R ₁
When a current I ₁ flows in and the potential of V _EE is about to rise, a current in the I ₃ direction flows in D _Z , and the potential of V _EE increases from 0.6V to
It can be suppressed to about 0.7V. Therefore, the possibility that the potential of _VEE exceeds the voltage of the switch input signal is reduced, and by inserting a current limiting resistor R into the input/output signal circuit, latch-up can be prevented. However, Zener diodes with a Zener voltage V _Z of 2V or less are currently unavailable.
Considering the conversion standard of V _DD (15V±10%), V _DD ~
Since the voltage between V _{and EE} exceeds the absolute maximum rating of the CMOS SW, this circuit may not be practical. In the case of the circuits shown in Figures 2 and 3, a resistor R is also inserted between the input and output of the switch signal to limit the current flowing through it, but if the potential of V _EE increases significantly, a large amount of current flows through R. This increases the probability that this will trigger a latchup.
In any case, an effective solution for preventing latch-up is to suppress the potential at the _VEE point from rising above 0V when the switch S is switched to as small as possible. This invention uses a circuit with a simple configuration.
The potential of V _EE is +1V when the CMOS switch is switched.
A circuit that prevents CMOS SW latch-up is realized by following the steps below. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

FIG. 5 shows the configuration of a circuit according to an embodiment of the present invention. This circuit is an improvement on the circuit shown in Fig. 2, and as shown in the figure, a diode D ₁ is connected in parallel to a resistor R ₂ inserted between the low potential end V _EE of the power supply terminal and the potential reference point G.
Connect. In this case, connect an anode electrode of D ₁ to the V _EE end.
Connect a cathode electrode to each end.

According to this configuration, when the switch S of the switch circuit _U2 is switched, the _VEE terminal rises due to the current I flowing through it, and the value is set to the diode
The forward voltage drop of _D1 can be kept below 0.6 to 0.7 V. This makes the switch circuit
Even if the potential of the switch input signal terminal 2 of _U2 falls below the potential of the _VEE terminal, the current flowing through the input signal circuit is limited to a small value by the current limiting resistor R inserted therein, preventing latch from occurring in the switch circuit _U2 . The voltage drop caused by the current flowing in the forward direction of a commercially available diode _D1 is standardized, and its maximum value is predictable. In addition, in commercially available CMOS SW, it is guaranteed that latch will not occur if the current flowing through the input/output terminals a, b, and c of switch S is below a specified value (for example, 10 mA or less). Therefore, the value of resistor R connected to the input and output is also set to a value that is within the range of the switch circuit
The power supply voltage (V _DD -V DD ) of the switch circuit U2 can be determined so that no latch occurs in the switch circuit _U2 .
V _EE ) is also kept below the allowable maximum rating.

FIG. 6 shows an example of a circuit in which the CMOS switch _U2 to which the latch-up prevention circuit of the present invention is applied is applied to switch the output signal to a burnout signal when a resistance temperature converter fails. In the figure,
R _t is a resistance temperature detector, and a constant current I ₁ is supplied from the reference power supply V _ref , and changes in R _t due to temperature are converted into voltage.
This converted voltage is amplified by an amplifier U ₁ and produces an output voltage E ₂ at its output 2. _E2 is led to the switch signal input end of CMOS switch _U2 .
The switch U ₂ used here is a composite circuit consisting of two sets of changeover switches S ₁ and S ₂ , and its power supply terminal is
V _EE is connected to a latch-up prevention circuit composed of resistors R ₁ , R ₂ and diode D ₁ as in FIG. 5. In the figure, switch S ₁ of U ₂ ,
The signal CON controlling the switching of S ₂ utilizes the voltage E ₁ occurring at the input 1 that supplies the current to R _t . Under normal operating conditions when a constant current is supplied to R _t , the voltage E ₁ at the input terminal 1 is almost zero, and the switches S ₁ and S ₂ controlled by this signal have their output terminals O ₁ , O ₂ is connected to the L side terminal, and the output voltage E ₂ of amplifier U ₁ is output through switch S ₁ .
Guided to OUT.

Now, if either the internal conductor of the temperature sensing resistor R _t or the conductors A and C is disconnected, the voltage E ₁ at the input terminal 1 increases, and the switch element S ₁ in the switch circuit U ₂ ,
The output terminals O ₁ and O ₂ of S ₂ are respectively switched to H-side terminals. FIG. 7 illustrates this failure time _t1 and the corresponding voltage waveform generated at the power supply terminal _VEE . if
If there is no diode _D1 included in the latch-up prevention circuit connected to V _EE , the potential of V _EE rises to about 4 to 5 V as shown by the dotted line, and its maximum value also varies. This potential rise passes through the V _EE point and resists
This is because current flows into R ₁ and R ₂ . If D ₁ is added in parallel with R ₂ as shown in the figure, the potential of V _EE can be kept below approximately +0.7V as shown by the solid line. When the output terminals O ₁ and O ₂ of the switch elements S ₁ and S ₂ are switched to the H side, the voltage at the output terminal 10 of the burnout signal generation circuit BU passes through the resistor R ₄ and is output to the O ₂ of the switch S ₂ .
lead to a point. Terminal 6 of switch SW ₁ of current BU
–7 is closed, the voltage 6V at point _VB is the resistance R ₄ ,
When capacitor C ₁ is charged through R ₆ and the charging time constant is determined by R ₄ , R ₆ and C ₁ , the voltage V _C of C ₁ is
6V, V _C passes through R ₇ and H→O ₁ of S ₁ and sends out a voltage higher than the upper limit of voltage E ₂ of amplifier U ₂ to the output of S ₁ . Also, 8- of SW ₁ of the BU circuit
9 can be closed, V _C drops to 0V. In this way, the burnout operation is performed by switching the _U2 circuit.

[Brief explanation of the drawing]

Figure 1 shows a circuit diagram of an example of CMOS SW usage.
FIGS. 2, 3, and 4 show examples of circuits proposed to prevent latch-up of CMOS SWs. FIG. 5 shows an embodiment of the latch-up prevention circuit of the present invention. FIG. 6 shows an example of a circuit to which a CMOS SW can be applied to implement the latch-up prevention circuit of the present invention. FIG. 7 is a voltage waveform diagram for explaining the operation. U ₂ ... CMOS SW, V _EE ... Power supply terminal, R ₁ ,
R ₂ ……divider resistance, D ₁ ……diode element.

Claims (1)

[Scope of utility model registration request] Add 0V to one power supply terminal V _EE and the other power supply terminal
For a CMOS switch that applies a constant voltage to V _DD and constrains the switched signal to this voltage range,
In a latch-up prevention circuit for a CMOS switch that prevents latch-up that occurs when the input voltage is lower than the potential on the power supply terminal _VEE side, the power supply terminal
Two resistors R ₁ and R ₂ are installed between a voltage −V _S of opposite polarity to the voltage applied to V _DD and a potential reference point G, and their common connection point is connected to the power supply terminal V _EE .
a series circuit consisting of a series circuit, which is installed between the power supply terminal V _EE and the potential reference point G, and whose anode electrode is connected to the electrode terminal V _EE and whose cathode electrode is connected to the potential reference point G. A latch-up prevention circuit for a CMOS switch characterized by being provided with a diode element.