JPH04271B2 - - Google Patents

Description

[Detailed description of the invention]

<Technical Field> The present invention relates to a moving image display device of an electrostatic display device. <Prior Art> First, the principle of an electrostatic display device will be explained. When a dielectric layer is interposed between a fixed electrode and a movable electrode and a voltage V is applied between both electrodes, polarization occurs in the dielectric layer due to the electric field generated between both electrodes, and attraction occurs between the fixed and movable electrodes. A force is generated, and this attractive force causes the movable electrode to be attracted to the fixed electrode, changing the state viewed from the front. FIG. 1 shows a perspective view of an example of an electrostatic display unit, and FIG. 2 shows a cross-sectional view of the same with a voltage application circuit added thereto. The first and second fixed electrodes 1 and 2 are symmetrical with respect to the movable electrode 3 and have a flat rectangular shape as a whole. In other words, the cross-sectional shape is from the fixed parts 1A and 2A facing each other parallel to each other, gradually approaching the front from both sides toward the plane of symmetry, and forming the closest part 4.
After this, inwardly convex arcuate curved surfaces 1B and 2B are formed that are gradually spaced apart, and tip portions 1C and 2C that face each other in parallel are formed beyond these. Further, terminals 12 and 13 for connecting lead wires rearward from the fixed parts 1A and 2A are integrally formed. A male spacer 5 made of an insulator, a film holder 6 made of a conductor, and a female spacer 7 made of an insulator are interposed between the fixed parts 1A and 2A.
A fixed part of the movable electrode 3 is sandwiched between them. Each fixed electrode is fixed by screwing in screws 8 and 9 from the outside of the fixed portions 1A and 2A of the fixed electrodes 1 and 2. The movable electrode 3 has a structure in which a thin film of a polymer such as polyester or polycarbonate is used as a core, and a conductive material such as aluminum is deposited on both sides of the core to make both sides mirror-finished, and the thickness is 0.006 mm to 0.012 mm. That's about it. The fixed part of the movable electrode 3 is closely attached to the film holder 6 or is bonded with a conductive adhesive, passes through the nearest part 4 and extends straight forward to form a free end, which is connected to the first and second parts. second fixed electrode 1,
2 can be freely adsorbed. Also,
A terminal 14 for connecting a lead wire is integrally formed on the film holder 6. The structure of the closest part 4 is such that a shim with a thickness of about 0.1 mm at both ends is interposed between both fixed electrodes 1 and 2 to form a slit defined by the thickness of the shim, and the movable electrode 3 is inserted into the slit. It's passing through. An insulating paint having a predetermined color such as white, red, blue, yellow, etc. is applied to the inside of the first fixed electrode 1, at least the inner surface in front of the nearest portion 4, to form a first dielectric layer. It consists of Similarly, the inner surface of the second fixed electrode 2 is coated with an insulating paint of a color different from that of the first fixed electrode or black to constitute a second dielectric layer. When using this device, an AC (or DC) power source 10 and a display control switch 11 are provided as shown in FIG. Connect to one pole,
The terminal 13 of the second fixed electrode is connected to the terminal B of the switch 11 and the other pole of the power source 10, and the terminal 14 of the movable electrode 3 is connected to the common contact C of the switch 11. When the A side of the switch 11 is on, the movable electrode has the same potential as the first fixed electrode, and both poles of the power source 10 are applied between the movable electrode and the second fixed electrode, so that the movable electrode 3 Since it is attracted to the inner surface of the first fixed electrode 2 and covers its painted surface, direct light from the colored painted surface of the first fixed electrode 1 and reflected light from the surface of the movable electrode can be recognized from the front. Next, when the B side of the switch 11 is turned on, the movable electrode becomes at the same potential as the second fixed electrode, and the electric charge previously stored between the movable electrode and the second fixed electrode is discharged and the movable electrode is turned on. When the attractive force of the electrode toward the second fixed electrode disappears and the movable electrode begins to return to its neutral position due to the elastic force of the movable electrode, both poles of the power source 10 are applied between it and the first fixed electrode. Therefore,
The movable electrode is attracted to the first fixed electrode 1, and from the front, direct light from the painted surface of the second fixed electrode 2 and reflected light from the surface of the movable electrode are recognized. <Object of the Invention> Therefore, an object of the present invention is to provide a moving image display device using such an electrostatic display device. <Structure of the Invention> The moving image display device of the electrostatic display device of the present invention includes (a) a fixed electrode, a movable electrode that can be attracted to or separated from the surface of the fixed electrode, and a surface of the fixed electrode or the movable electrode. It has a dielectric layer provided on one or both of them, and a lead wire for applying a voltage between the fixed electrode and the movable electrode, and when the voltage is applied, the movable electrode is connected to the fixed electrode. (b) A display section in which a large number of electrostatic display units are arranged in a matrix so that the appearance of the display unit changes when electrostatically attracted to the surface of the display section (b). It has a bit corresponding to the display unit, and can be changed to 1 by a shift pulse.
Display register shifted column by column (c) A display information section in a matrix format in which one frame of display information to be displayed on the display section is written, and a blank section in a matrix format with a predetermined number of columns are arranged alternately in a series. Display information for multiple frames is written, and a control command code is written to identify and display the high-speed shift command written in the area corresponding to the display information section and the stop command written in the area corresponding to the margin section. (d) An address counter that increments the matrix-format columns of this memory (e) A decoder (f) that reads the control command code written in the memory and selectively outputs a high-speed shift command or a stop command. a first frequency that is high enough to transfer one frame of display information to be displayed on the display section from the memory to the display register within the response time of the movable electrode of the electrostatic display unit; Clock signal generating means (g) for generating a pulse having a second frequency much lower than that of the clock signal generating means (g) causing the address counter to be incremented by the clock signal having the first frequency when the decoder outputs a high-speed shift command; Transfer means (h) for transferring display information corresponding to the instruction from the memory to the display register at high speed; when the decoder outputs a stop instruction, the address counter is incremented by the clock signal having the second frequency; and stop mode control means for stopping the supply of shift pulses to the display register while the stop command is being outputted, so that a series of moving images can be displayed by sequentially changing one-frame still images. It is characterized by its structure. <Operation> When the memory address is incremented by the high-speed shift output (Q ₁ ), the electrostatic display unit cannot respond to changes in the display register and continues to statically display the previous state. When displaying a video, a high-speed shift control command code is written corresponding to one pattern of display information, and then, for example, a stop time measurement control command code is written in the margin of 4 columns, and similarly one frame Display information and margins are written alternately (4th
figure). When the display pattern information area is a blank area, the display statically displays the previous display content. The duration is, for example, 1 second. Next, the pattern information for the next display frame is transferred from the memory to the display register, and the high-speed shift mode is selected.
During this time, the electrostatic display unit cannot respond to the change and continues to statically display the previous display content. Then, when the stop mode is selected, the display units are finally able to respond to the contents of the display registers, and immediately after the stop mode is selected, the display units all respond to the pattern contents that were transferred when the fast shift mode was selected. Switch to . Thereafter, this action is repeated and the video is displayed. <Description of Examples> FIG. 3 shows the circuit configuration of the entire device. Display section 2
1 has a large number of electrostatic display units 20 illustrated in FIG. 1 arranged in a matrix on one panel, and the number of units is, for example, 20×200.
It's a dot. The drive circuit section 22 is composed of a large number of thyristors that correspond one-to-one to the display unit 20. The display register 23 is composed of a matrix-structured shift register shifted by a clock pulse CK', and each bit corresponds to each dot of the display unit 20. The control circuit section 24 includes an oscillator 2 that generates a clock source oscillation CL.
5. A circuit 26 that divides the frequency of the clock source oscillation CL to generate a timing signal CK, an address counter 27 that counts the frequency-divided pulse signal CK, and controls frequency division using control instructions C ₀ , C ₁ , and C ₂ It is comprised of a control decoder 28 and a data transfer circuit 29 that transfers display data from a storage device 30 (described later) to the display register 23 described above. The storage device 30 is made up of a RAM (random access memory), and all display data and control commands corresponding to each display data are written therein. The control commands include C ₀ , C ₁ , and C ₂ for each column of the display data storage section.
These three bits are assigned to specify various modes as shown in the table below.

[Table] FIG. 4 shows the format of the storage device 30.
It is a matrix type RAM with 24 bits per column, of which 4 bits are allocated to storage of control instructions and the remaining 20 bits are allocated to storage of display data. In the diagram, the white background represents logic “0” and the black dotted area represents logic “1”.
It represents. For example, display data “ABCDE”
The control instruction corresponding to the column where is stored is C ₁ =
1, C ₂ =0 and the high-speed shift mode is set, and the control command corresponding to the column in which the next display data "FGHIJ" is stored also becomes C ₁ =1 and C ₂ =0. The control commands corresponding to the column of the margin immediately after the display data “ABCDE” and the column of the margin immediately after the display data “FGHIJ” are C ₁ = 0, C ₂
= 1 and is in stop mode. FIG. 5 shows a circuit of the control circuit section 24 related to a device that displays a moving image by repeating high-speed shifting and stopping. The frequency dividing circuit 32 sequentially divides the frequency of the clock source oscillation CL of the oscillator 25. Output Q ₁ is the output of the first stage of frequency division, output Q ₉ is the output of the ninth stage, output
_Q12 is the output of the 12th stage and is the clock source oscillation.
When the frequency of CL is f ₀ , the frequency of Q ₁ is f ₀ ×
2 ^-1 , the frequency of Q ₉ is f ₀ ×2 ^-9 , the frequency of Q ₁₂ is f ₀ ×
2 ^-12 . Output Q ₁ is provided for high-speed shifting, output Q ₉ is provided for flow display, and output Q ₁₂ is provided for stop clock measurement. NAND gate 33 has C ₁ = 1, C ₂ = 0
The NAND gate 34 opens when C ₁ =0, C ₂ =
0, the NAND gate 35 is C ₁ = 0, C ₂
Opens when =1. Each NAND gate 33, 34,
The output of 35 is input to AND gate 36, and this
The output of AND gate 36 is the output of flip-flop 3
7 and is shaped into a pulse signal with a constant time width, and then passed through the inverter 38 to the frequency dividing circuit 3.
It is connected to the second reset terminal. counter 2
7 is an address counter which increments by one in response to the output Q of the flip-flop 37. The 12 output terminals Q ₁ ...Q ₁₂ can provide 2 ¹² = 4096 status outputs. The address of the random access memory (RAM) 30 is selected by this state output, and the data stored in the memory 30 is outputted from the data output terminals D _{0 .} . . D ₁₉ . Also, the output Q of the flip-flop 37 is the NAND gate 39
A shift pulse is output to the display register 23 via the transistor 40, but in the stop mode, the NAND gate 39 is closed to prevent the shift pulse from being output to the display register. The reason why this shift of the display register is stopped is that it is undesirable in terms of moving image expression for the pattern being displayed to be washed away, even if it is gradual. Assume that control codes C ₁ =1 and C ₂ =0 specifying high-speed shifting have been written together with the display data in the memory 30. FIG. 6 shows voltage waveforms at various parts in the high-speed shift mode. NAND
The outputs of the gates 34 and 35 are always "1", and the output _Q1 of the frequency dividing circuit 32 changes from L (low) to H (high).
At the moment when the frequency is reversed, the frequency divider circuit 32 is reset by the reset circuit of the inverter 38, so that
The output of AND gate 36, ie, the input signal of flip-flop 37, becomes a sharp negative pulse. Flip-flop 37 outputs a square wave that divides this negative pulse, and this output advances the address in memory 30 one by one, and in synchronization with this, the contents of display register 23 advances one column at a time. However, the frequency of this stepping pulse is, for example, 5 KHz, and the movable electrode of the electrostatic display unit 20 cannot cope with this frequency, so that the previous display pattern is maintained. In this mode, the frequency divider circuit is always reset after outputting _Q1 , so it does not proceed to the second stage or later and the outputs _Q9 and _Q12 are never output. The memory 30 address then advances to change the control command from fast shift mode to stop mode, i.e.
When C ₁ = 0, C ₂ = 1, NAND gate 3
5 is ready to open, and at this time other
The outputs of the NAND gates 33 and 34 are always "1". The output Q ₁₂ of the frequency divider circuit ₃₂ is
2 ¹¹ = Output at 2048 times the period. When this is output, the frequency divider circuit is reset by the reset circuit of the inverter 38 as soon as the NAND gate 35 and AND gate 36 are opened, as in the previous high-speed shift mode, so the output waveform of the AND gate 36 is A sharp negative pulse. FIG. 7 shows voltage waveforms at various parts. The time axis of FIG. 7 is much compressed compared to FIG. 6. The address written in this static command mode is, for example, 4.
It is an address. The time required for the counter 27 to advance through four addresses at extremely low speed is, for example, one second. During this stop time, no shift pulses are sent to the display register, and the previous high-speed shifted content, for example "ABCDE", is statically displayed. When the control instruction code goes into high-speed shift mode again, the contents of the display register are switched from "ABCDE" to "FGHIJ" at high speed, but during this time, as mentioned above, the movable electrode of the electrostatic display unit cannot respond, so The display unit continues to display "ABCDE". After entering the stop display mode after the memory address is "FGHIJ", the movable electrodes finally respond and the display contents switch from "ABCDE" to "FGHIJ" all at once. <Effects of the Invention> According to the present invention, the response speed of the movable electrode of the electrostatic display unit is appropriately slow and cannot follow the shift of the display register in the high-speed shift mode, so the display pattern does not flicker when switching. , it is possible to perform stable frame-by-frame advance. In addition, the high-speed shift and standstill modes are switched at the frequency division stage, which simplifies the circuit configuration.Furthermore, the standstill time can be set arbitrarily by the number of addresses that have a standstill mode command, making it easy to use. It is possible to display a variety of moving images depending on the program.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing an example of an electrostatic display unit used in the present invention, and FIG. 2 is a cross-sectional view of the same with an electric circuit added thereto. 3 is a circuit block diagram showing the overall configuration of an embodiment of the present invention, FIG. 4 is a diagram showing an example of the format of the storage device 30 shown in FIG. 3, and FIG. 5 is a diagram showing the timing generation circuit 26 shown in FIG. 3.
6 and 7 are time charts for explaining the operation of FIG. 5. 1, 2...fixed electrode, 3...movable electrode, 20...
...Capacitive display unit, 21...Display section,
22...Drive circuit, 23...Display register, 27
... RAM address counter, 28 ... Control instruction code decoder, 32 ... Frequency division circuit, 33,
34, 35, 39...NAND gate.

Claims (1)

[Scope of Claims] 1. A moving image display device of an electrostatic display device having the following (a) to (h) and configured to display a series of moving images by sequentially changing one-frame still images. (a) a fixed electrode, a movable electrode that can be attracted to or separated from the surface of the fixed electrode, a dielectric layer provided on either or both of the surface of the fixed electrode or the surface of the movable electrode; A lead wire is provided for applying a voltage between the movable electrodes, and the application of the voltage causes the movable electrode to be electrostatically attracted to the surface of the fixed electrode, thereby changing the appearance of the display unit. A display section (b) in which a large number of electrostatic display units configured to
Display register shifted column by column (c) A display information section in a matrix format in which one frame of display information to be displayed on the display section is written, and a blank section in a matrix format with a predetermined number of columns are arranged alternately in a series. Display information for multiple frames is written, and a control command code is written to identify and display the high-speed shift command written in the area corresponding to the display information section and the stop command written in the area corresponding to the margin section. (d) An address counter that increments the matrix-format columns of this memory (e) A decoder (f) that reads the control command code written in the memory and outputs a high-speed shift command or a stop command alternatively. a high-speed first frequency capable of transferring one frame of display information displayed on the display section from the memory to the display register within the response time of the movable electrode of the electrostatic display unit; Clock signal generating means (g) for generating a pulse having a second frequency much lower than the clock frequency; when the decoder outputs a high-speed shift command, the address counter is incremented by the clock signal having the first frequency; Transfer means (h) for transferring display information corresponding to the command from the memory to the display register at high speed; when the decoder outputs the stop command, the address counter is clocked by the clock signal having the second frequency; stop mode control means for causing the display register to advance and stopping the supply of shift pulses to the display register while the stop command is being outputted;