JPH04271676A - Video synthesizer circuit - Google Patents

Abstract

PURPOSE:To obtain the video signal synthesizer circuit capable of synthesizing television video signals with a simple configuration. CONSTITUTION:This circuit is composed of a first multiplying circuit 3 to receive the first television video signal and to attenuate the amplitude of the signal, a second multiplying circuit 4 to receive the second television video signal and to attenuate the amplitude, switching circuit 5 to selectively switch the signals from the first and second multiplying circuits 3 and 4, and timing generation circuit 6 to output a required timing pulse respectively to the first and second multiplying circuits 3 and 4 and the switching circuit 5 while receiving a key signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in television video signal processing devices, and more particularly to a video synthesis circuit for television video signals.

0002

2. Description of the Related Art As shown in FIG. 3, a conventional video synthesis circuit includes a first multiplier circuit 13 that receives a first television video signal input to a first input terminal 11 and controls the amplitude of the signal. , a second multiplier circuit 14 that receives a second television video signal input to the second input terminal 12 and controls the amplitude of the signal, and these first and second multiplier circuits 1
It has an addition circuit 15 that adds signals from 3 and 14.

In this video synthesis circuit, when combining the first television video signal and the second television video signal, for example, at a certain timing, the first multiplication circuit 13 combines the first television video signal with the first television video signal. While multiplying the signal by 0, the second multiplication circuit 14 multiplies the second television video signal by 1, and the added signals are added in the addition circuit 15. At this timing, A second television video signal can be output. By performing this process at each timing,
It becomes possible to obtain a signal that is a combination of the first and second television video signals.

0004

[Problems to be Solved by the Invention] In such a conventional video synthesis circuit, the first and second television video signals processed by the first and second multiplier circuits 13 and 14 are processed by the addition circuit 15. Although video signals are synthesized by addition, if processing such as inserting a required signal (synchronization signal, etc.) between the synthesized signals is required, this addition circuit 15
There is a problem in that the configuration of the circuit becomes extremely complicated, and as a result, the entire video synthesis circuit becomes complicated. An object of the present invention is to provide a video signal synthesis circuit that can synthesize video signals with a simple configuration.

[0005]

[Means for Solving the Problems] A video signal synthesis circuit of the present invention includes a first multiplier circuit that receives a first television video signal and attenuates the amplitude of the signal, and a first multiplication circuit that receives a first television video signal and attenuates the amplitude of the signal. a second multiplier circuit that receives the key signal and attenuates its amplitude; a switching circuit that selectively switches the signals from each of the first and second multiplier circuits;
and a timing generation circuit that causes each of the second multiplier circuits and the switching circuit to output required timing pulses. Further, in this case, the attenuation ratio in each of the first and second multiplier circuits is set to 1/2 or 0.

[0006]

[Operation] By switching between a signal obtained by multiplying the first television video signal and a signal obtained by multiplying the second television video signal in a switching circuit based on a timing pulse, each television video signal is Synthesis becomes possible.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a circuit according to an embodiment of the present invention. A first television video signal is input to a first input terminal 1, and the amplitude of this video signal is attenuated by a first multiplier circuit 3. be done. Similarly, a second television video signal is input to the second input terminal 2, and the amplitude of this video signal is attenuated by the second multiplier circuit 4. The signals from each of the first and second multiplication circuits 3 and 4 are selectively switched by a switching circuit 5 and output. The multiplication circuits 3 and 4
The attenuation process and the switching process in the switching circuit 5 are performed by a timing pulse output from the timing generation circuit 6 in response to a key signal input from the third input terminal 7.

FIG. 2 shows the operation of the video synthesis circuit with this configuration.
Explain using. FIG. 2 shows a television video signal in which time is plotted on the horizontal axis and amplitude of the television video signal is plotted on the vertical axis. In particular, television video signals in the vicinity of which images are to be synthesized are shown. First, the first television video signal input to the first input terminal 1 as shown in FIG. 2(a) is input to the first multiplier circuit 3, where the timing is adjusted as shown in FIG. In response to the timing pulses P1 and P1' output from the generation circuit 6, the amplitude of the television video signal is attenuated to 1/2 and 0 times, respectively, and output. When timing pulses P1 and P1' are not received,
The first multiplication circuit 3 outputs the television video signal without processing it.

Similarly, a second television video signal as shown in FIG. 2(c) inputted to the second input terminal 2 is
is input to the multiplication circuit 4, where, as shown in FIG. 2(d),
Timing pulse P output from the timing generation circuit
2 and P2', the amplitude of the television video signal is attenuated by /2 times and 0 times, respectively, and output. When the timing pulses P2 and P2' are not received, the second multiplier circuit 4 outputs the television video signal without processing it.

Then, the switching circuit 5 converts the output signals from the first multiplier circuit 3 and the second multiplier circuit 4 into a timing pulse P.
2 (e) by selectively switching and outputting
), it is possible to obtain a video signal that is a composite of the first television video signal and the second television video signal. . Incidentally, the timing pulses P1, P1', P2
, P2', and P3 receive a key signal from the third input terminal 7 that determines the position of video synthesis, and the timing generating circuit 6 generates the key signal.

Therefore, in this video synthesis circuit, instead of the conventional adding circuit with a complicated circuit configuration, a switching circuit 5 and
Video synthesis can be realized by providing each multiplier circuit 3, 4 and switching circuit 5 with a timing generation circuit 6 that outputs a timing pulse, and since these switching circuits and timing generation circuit have simple circuit configurations, It becomes possible to simplify the configuration of the entire video synthesis circuit. In particular, by limiting the attenuation ratio of each multiplier circuit 3, 4 to 1/2, 0,
The process of inserting a synchronization signal or the like between the synthesized video signals becomes easier, and the circuit can be further simplified. Furthermore, when the input television video signal is a digital signal, each of the circuits described above is constructed with a digital circuit, so that the first multiplier circuit 3 and the second multiplier circuit 4 in particular are simpler than when constructed with analog circuits. It can be configured as follows.

0012

As explained above, the present invention allows a signal obtained by multiplying a first television video signal and a signal obtained by multiplying a second television video signal to be connected in a switching circuit based on a timing pulse. Since the configuration is configured to switch between
This has the effect of simplifying the configuration of the video synthesis circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a video synthesis circuit of the present invention.

2A to 2E are diagrams showing video signals of sections a to e in FIG. 1, respectively;

FIG. 3 is a block diagram of a conventional video synthesis circuit.

[Explanation of symbols]

3 First multiplication circuit 4 Second multiplication circuit 5 Switching circuit 6 Timing generation circuit

Claims (2)

[Claims] 1. A first multiplier circuit that receives a first television video signal and attenuates the amplitude of the signal; and a second multiplier circuit that receives a second television video signal and attenuates the amplitude of the signal. , a switching circuit that selectively switches signals from each of the first and second multiplier circuits; and a switching circuit that receives a key signal and causes each of the first and second multiplier circuits and the switching circuit to output required timing pulses. A video synthesis circuit comprising a timing generation circuit. 2. The video synthesis circuit according to claim 1, wherein the attenuation ratio in each of the first and second multiplier circuits is set to 1/2 or 0.