JPH04271507A - Digital transversal filter - Google Patents

Abstract

PURPOSE:To realize the digital transversal filter able to cope with a higher bit rate. CONSTITUTION:A product sum between input data by an odd number side arithmetic section 1 and odd number tap coefficients and a product sum between input data by an even number side arithmetic section 2 and even number tap coefficients are added by an adder section 3, from which an output is generated. Or a multiplier section 4 multiplies alternately input data and an odd number tap coefficient and an even number tap coefficient, an odd number side accumulate section 5 adds the result of multiplication between the data and the odd number tap coefficient and an even number side accumulate section 6 adds the result of multiplication between the data and the even number tap coefficient, and an adder section 7 adds the accumulation result of the odd number accumulation section 5 and the accumulation result of the even number accumulation section 6 and generates an output to form the digital transversal filter.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of an FIR type digital transversal filter, and more particularly to a digital transversal filter (hereinafter referred to as DTF) used in a digital demodulator.

[0002] When performing baseband signal processing in a digital demodulator for wireless communications, an analog signal is normally sampled four times per period at the analog-to-digital (A/D) conversion stage, and the data is waveform-shaped using a DTF. Then, timing playback etc. are performed.

[0003] Such a DTF is required to be compatible with high bit rates. Furthermore, if the bit rate is the same, it is desired that the hardware scale can be reduced. Furthermore, it is desired that the device be compatible with a method of timing recovery by changing tap coefficients.

0004

[Background Art] When signal processing is performed in the baseband in a digital demodulator, the input analog signal is subjected to A/D conversion with 4 samples per period, and the resulting data is subjected to waveform shaping processing using DTF. and perform timing playback etc. The bit rate in this case is DT
It depends on F and the operating speed of the timing recovery circuit and carrier wave recovery circuit. In particular, the number of DTF taps is large (for example, 2
5 taps, etc.), the calculation speed of the multiplier inside the DTF becomes a bottleneck, and it is often impossible to achieve a high bit rate.

FIG. 9 shows an example of the circuit configuration of a conventional DTF.
16,121 to 126 are flip-flops (FF)
, 131 to 136 are multipliers, 141 to 146, 1
51 to 156 are flip-flops (FF), 161
~165 is an adder.

In the DTF shown in FIG.
operates with a clock having a bit rate four times the bit rate R of the input signal. Tap coefficients C1 to C6 as FF1
11 to 116, and input to FF12.
1 to 126 in parallel, the outputs of the corresponding FFs are multiplied in multipliers 131 to 136, respectively, and the multiplication results are held in FFs 141 to 146. Then, the signal obtained by delaying the output of FF141 by FF151 and the output of FF142 are added by an adder 161, and F
Hold F152, output of FF152 and FF143
The adder 162 adds the outputs of the input signal to the input signal and stores the result in the FF 153, and the sum of products is sequentially calculated in the same manner, thereby obtaining an output signal whose waveform has been shaped with respect to the input signal.

[0007]

[Problem to be Solved by the Invention] In the conventional DTF, as shown in the example of FIG. The output is obtained by performing sum-of-products calculations. Therefore, the operation speed is limited by the calculation speed of the multiplier, and there is a problem in that it is difficult to realize a high bit rate.

[0008] The present invention aims to solve the problems of the prior art as described above, and it is possible to reduce the calculation speed in the multiplier to 1/2 that of the conventional DTF, and therefore, it is possible to use the same multiplier. In this case, the purpose is to provide a DTF that can support higher bit rates.

[0009]

[Means for Solving the Problems] As shown in FIG. 1(a) in principle, the present invention outputs data by sequentially accumulating the results of multiplying a plurality of tap coefficients and input data. In a digital transversal filter, the input data is sampled using a clock that is four times faster than the input data, and the odd-numbered tap coefficient among the multiple tap coefficients is multiplied by a clock that is twice the speed of the input data. Odd-number side calculation unit 1 sequentially accumulates the results, and multiplies the input sample and the even-numbered tap coefficient among the plurality of tap coefficients by an inverted clock of a clock twice the speed of the input data, and sequentially accumulates the results. It is characterized by having an even number side calculation section 2 and an addition section 3 that adds the output of the odd number side calculation section 1 and the output of the even number side calculation section 2.

The present invention also provides a digital transversal system that obtains an output by sequentially accumulating the results of multiplying a plurality of tap coefficients and input data, as shown in FIG. 1(b). In the filter, a multiplier 4 that alternately and sequentially multiplies data obtained by sampling input data using a clock that is four times faster than the input data by an odd-numbered tap coefficient and an even-numbered tap coefficient among a plurality of tap coefficients; The odd-number side accumulator 5 sequentially adds up the results of calculations with the odd-numbered tap coefficients of the input data every clock at twice the speed of the input data, and the calculation results of the even-numbered tap coefficients of the multiplier 4 with the input data. Even number side accumulator 6 that sequentially accumulates for each inverted clock of the double speed clock
and an adder 7 that adds the output of the odd-number side accumulator 5 and the output of the even-number side accumulator 6.

[0011]

[Operation] As a timing recovery method for a digital demodulator, there is a method of double sampling the output of the DTF to detect the phase difference. If you have it, you can regenerate the timing. Therefore, in DTF calculation, A/D
Decimation may be performed on the converted four-sample data to output data for two samples, a data point and a zero-crossing point. However, in this case, in order to avoid loss of calculation accuracy, all calculations are performed on the 4 sample data, and then the necessary 2
It is necessary to output sample data. By paying attention to this point and creating a configuration as shown in FIG. 1, it is possible to perform required calculations at half the calculation speed of the conventional DTF.

In the DTF of the present invention, as shown in FIG. 1(a), in a digital transversal filter that obtains an output by sequentially accumulating the results of multiplying a plurality of tap coefficients and input data, An odd-number side arithmetic unit 1 is provided to multiply input data sampled using a clock that is four times faster than the input data by an odd-numbered tap coefficient among a plurality of tap coefficients, respectively, by a clock that is twice the speed of the input data. The results are sequentially accumulated, and an even-number side arithmetic unit 2 is provided to multiply the input sample and the even-numbered tap coefficient among the plurality of tap coefficients by an inverted clock of a clock that is twice the speed of the input data. is sequentially accumulated, an adder 3 is provided, and the output of the odd-number side arithmetic unit 1 and the output of the even-number side arithmetic unit 2 are added together to generate the DTF output. te1
The desired output can be obtained by performing multiplier operations at an operation speed of /2.

Furthermore, in the DTF of the present invention, as shown in FIG. 1(b), in a digital transversal filter that obtains an output by sequentially accumulating the results of multiplying a plurality of tap coefficients and input data, , a multiplier 4 is provided to alternately and sequentially multiply input data sampled by a clock that is four times faster than the input data by the odd-numbered tap coefficient and the even-numbered tap coefficient among the plurality of tap coefficients. An accumulator 5 is provided to sequentially accumulate the operation results with the odd-numbered tap coefficients of the multiplier 4 for each clock at twice the speed of the input data. The calculation result with the th tap coefficient is sequentially accumulated for each inverted clock of the clock that is twice as fast as the input data, and an adder 7 is provided, and the output of the odd-number side accumulator 5 and the output of the even-number side accumulator 6 are summed. DTF by adding
Since the output of the multiplier is made to be generated, the desired output can be obtained by performing the calculation of the multiplier at 1/2 the calculation speed compared to the conventional DTF.

[0014]

[Embodiment] FIG. 2 shows an embodiment of the present invention, in which a 6-tap DTF is configured, and 20 is a clock 4CK with a bit rate four times the input bit rate R. Operating flip-flop (FF), 211,
213, 215, 221, 223, 225 are flip-flops (FF) that operate with a clock of double bit rate 2CK, 231, 233, 235 are multipliers, 24
1,243,245,251,253,255 are flip-flops (FF) that operate with 2CK clock, 26
1,263 is an adder, which constitutes an odd number side calculation section. 212, 214, 216, 222, 2
24,226 is an inverted clock with double bit rate*
Flip-flop (FF) operating with 2CK, 232,
234, 236 are multipliers, 242, 244, 246,
Flip-flops (FF) 252, 254, and 256 operate with an inverted clock *2CK, and adders 262 and 264 constitute an even number side calculation section. 27 is a flip-flop (
FF), 28 is an adder, and 29 is a flip-flop (FF) that operates with a clock of 2CK.

The 4-sample data input is taken into the FF20 with a clock of 4CK, and then inputted into the FF2 of the odd-number side arithmetic unit.
21, 223, 225 with clock 2CK, and FF211, 213, 215 with clock 2CK.
Odd-numbered tap coefficients C1, C3, taken in by CK
C5 and multipliers 231, 233, 235, and the multiplication results are taken into FFs 241, 243, 245 at clock 2CK. Then, the signal obtained by delaying the output of FF241 by FF251 and the output of FF243 are added by an adder 261 and held in FF253.
Adder 26 adds the output of F253 and the output of FF245.
3 and held in FF255.

[0016] The data taken in by the clock 4CK to the FF20 is sent to the FF222, 224, 226 of the even number side arithmetic unit.
is taken in by clock *2CK, and FF212, 21
4,216 are multiplied by even-numbered tap coefficients C2, C4, and C6 taken in by clock *2CK, respectively, by multipliers 232, 234, and 236, and the multiplication result is F.
F242, 244, 246 take in clock *2CK. Then, the output of FF242 is converted to FF252.
Adder 262 adds the delayed signal and the output of FF 244.
The outputs of FF254 and FF246 are added together by an adder 264 and held in FF256. The output of FF256 is taken into FF27 at clock 2CK.

Odd number side data held in FF255 and even number side data held in FF27 are connected to adder 2.
8, and is shaped by the FF 29 with a clock of 2CK and output. In the DTF shown in FIG. 2, decimation is performed, making it possible to reduce the calculation speed of the multiplier by half compared to the conventional DTF shown in FIG.

FIG. 3 is a time chart showing the signals of each part in the embodiment of FIG. FF221, 22 which is the output of each part
3,225 odd-number side captured data de (x1, x
3, x5,...), odd-number side intake tap coefficients t1 (C1), t3 (C3
), t5 (C5), odd side multipliers 231, 233
, 235 output data m1, m3, m5, output data a1, a3, a5 of FF 251, 253, 255 indicating addition operation on odd number side, output data o of odd number side calculation section
o is shown. Furthermore, only the output data oe of the even number side calculation section is shown. Note that in the figure, the output of the multiplication result is expressed only by subscripts, for example, C1 x
1 is expressed as 11. Odd number side output data oo
A DTF output is generated by adding the even-numbered output data oe and the even-numbered output data oe.

FIG. 4 shows the relationship between the DTF calculation results shown in FIG. 3 and the 2-sample output data, where (a) shows the 4-sample data, and (b) shows the DTF input data. It shows the output of DTF calculation results for columns x1, x2, x3, x4, x5, . . . By referring to FIG. 3 and FIG. 4, it is clear that according to the present invention, only two sample data of the necessary D point and Z point among the four sample data can be outputted from the DTF.

FIG. 5 shows another embodiment of the present invention, and shows an example of a DTF circuit configuration when used in a method of regenerating timing by changing tap coefficients for each clock. DTF similar to the embodiment shown in FIG.
311 to 316 are read-only memories (ROM) corresponding to the tap coefficients C1 to C6 of the DTF 30, respectively, and 321 to 326 are ROM3, respectively.
11 to 316, SR311 and 314 are one stage, SR
SRs 312 and 315 have two stages, and SRs 313 and 316 have three stages.

In the embodiment shown in FIG. 5, the tap coefficients C1 to C6 of the DTF 30 are stored in the ROMs 321 to 3, respectively.
SR311 to 31 are stored in advance in SR311 to SR311 and read out in accordance with the timing control signal and address signal.
By delaying the required time by 6 and applying it to the DTF 30, the DTF operation can be performed in the same manner as in the embodiment of FIG. According to the embodiment of FIG. 5, DT
When F is used in a timing recovery circuit of a digital demodulator, the timing can be recovered by changing the tap coefficient of the DTF for each clock.

FIG. 6 is a time chart showing a method of loading tap coefficients in the embodiment of FIG.
)321, ROM(3)323, ROM(5)325
The tap coefficient is read out according to clock 2CK from
Based on this, SR(1)311, SR(3)313,
It is shown that tap coefficients are output from the SR(5) 315 at required timing and loaded into the DTF 30. Note that the tap coefficient ROM can also be configured so that the ROM for the odd number side calculation section and the one for the even number side calculation section are multiplexed and used.

FIG. 7 shows still another embodiment of the present invention, in which multiple processing is performed, and a case of 6 taps is illustrated. 40, 411, 412, 413
, 421, 422, 423 are flip-flops (FF) that operate on a 4CK clock with a bit rate 4 times the input bit rate R, 431, 432, 433 are multipliers, and 441, 442, 443 are double bits. A flip-flop (FF) that operates with a clock rate of 2CK,
451, 452 are adders, 461, 462, 463
471, 472, and 48 are adders, and 49 is a flip-flop (FF) that operates with an inverted clock *2CK of twice the bit rate.

[0024] After the 4 sample data input is taken into the FF 40 at a clock of 4 CK, the 4 sample data is input to the FF 421, 422,
423 with a clock of 4CK. When performing calculations on odd-numbered tap coefficients, FF411,
Odd-numbered tap coefficients C1, C3, and C5 are taken in by clock 4CK at FF412 and 413, respectively, and when performing calculations on even-numbered tap coefficients, FF41
Even-numbered tap coefficients C2, C4, and C6 are taken in at clocks 1, 412, and 413, respectively, with a clock of 4CK. In the multipliers 431, 432, 433, FF42
1,422,423 and F
If the multiplication result is an odd-numbered tap coefficient, the output of the multiplier 431 is delayed by the FF441 and the output of the multiplier 432 is added to the adder. 451 and held in FF442, and adder 452 adds the output of FF442 and the output of multiplier 433 and stores it in FF442.
3, and in the case of an even-numbered tap coefficient, the signal obtained by delaying the output of the multiplier 431 by the FF 461 and the output of the multiplier 432 are added by the adder 471, and the output of the FF 46 is
The output of the FF 462 and the output of the multiplier 433 are added by the adder 472 and held in the FF 463. Then, in the adder 48, the output of FF443 and the FF
463 and the output of the addition result is sent to FF49.
formats and generates output.

According to the embodiment shown in FIG. 7, the part that multiplies input data and tap coefficients is shared by the calculation of odd-numbered tap coefficients and the calculation of odd-numbered tap coefficients. The scale will be reduced.

In the case of the embodiment shown in FIG. 7 as well, the tap coefficients may be stored in the ROM in advance and read out and given to the multiplier at the required timing to perform multiplication. can. Further, this ROM may be used by multiplexing odd-numbered tap coefficients and even-numbered tap coefficients. By this, in DTF,
It becomes possible to perform control to change the tap coefficient for each clock.

FIG. 8 shows an example of a demodulator to which the DTF of the present invention is applied, in which 50 is a quadrature detection section, 51, 5
2 is an analog-digital converter (A/D), 53, 54
is the DTF of the present invention, 55 is carrier recovery (CR),
56 is a symbol timing recovery (STR), and 57 is a clock source.

The input QPSK modulated wave signal is transmitted to the quadrature detection section 5
0 is orthogonally detected and decomposed into orthogonal components, and the A/D
51 and 52, the clocks from the clock source 57 are used to convert the signals into digital signals, and the DTFs 53 and 5
4 is input. The DTFs 53 and 54 have tap coefficients set by the STR 56, so that the A/D
The digitized input signals from 51 and 52 are waveform-shaped and input to the CR 55. The CR 55 generates and outputs demodulated data consisting of an I component and a Q component from this waveform-shaped orthogonal signal input. On the other hand, STR5
6 detects the phase difference between the outputs of the DTFs 53 and 54, generates a tap coefficient corresponding to the phase difference, and outputs the DTFs 53 and 54.
supply to.

In the demodulator shown in FIG. 8, for example, the DTF characteristics shown in FIG. 5 are changed in accordance with changes in the input waveform by changing the tap coefficient of the DTF for each clock. Therefore, demodulation can always be performed in the best condition.

[0030]

As explained above, according to the DTF of the present invention, the calculation speed of the multiplier can be reduced by 1/1 compared to the conventional DTF.
2, so if the same multiplier is used, it is possible to achieve a bit rate twice that of the conventional DTF. Also, if the bit rate is the same as before,
Since the multiplier can perform multiple processing, the hardware scale can be reduced. Also, the tap coefficient is RO
If the tap coefficients are given from M, the tap coefficients can be changed for each clock, so it can be applied to a demodulator or the like that performs timing recovery while changing the DTF tap coefficients.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are diagrams showing the basic configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a time chart showing signals of various parts in the embodiment of FIG. 2;

FIG. 4 is a diagram showing the relationship between the calculation results of the DTF of the present invention and 2-sample output data, where (a) shows 4-sample data, and (b) shows the DFT input data string x1, x2,
The output of the DFT calculation results for x3, x4, x5, . . . is shown.

FIG. 5 is a diagram showing another embodiment of the present invention.

FIG. 6 is a time chart showing a method of loading tap coefficients.

FIG. 7 is a diagram showing still another embodiment of the present invention.

FIG. 8 is a diagram illustrating a demodulator to which the DTF of the present invention is applied.

FIG. 9 is a diagram showing an example of a circuit configuration of a conventional DTF.

[Explanation of symbols]

1 Odd number side calculation section 2 Even number side calculation section 3 Addition section 4 Multiplication section 5 Odd number side cumulative part 6 Even number side cumulative part 7 Addition section

Claims (5)

[Claims] Claim 1: A digital transversal filter that obtains an output by sequentially accumulating the results of multiplying a plurality of tap coefficients and input data, comprising:
Odd number side that multiplies data obtained by sampling the input data using a clock that is four times faster than the input data and an odd-numbered tap coefficient among the plurality of tap coefficients by a clock that is twice the speed of the input data, and sequentially accumulates the results. an arithmetic unit (1); and an even side that multiplies the input sample and an even-numbered tap coefficient among the plurality of tap coefficients by an inverted clock of a clock that is twice as fast as the input data, and sequentially accumulates the results. A digital transversal filter comprising: an arithmetic unit (2); and an adder (3) that adds the output of the odd-number side arithmetic unit (1) and the output of the even-number side arithmetic unit (2). 2. A digital transversal filter that obtains an output by sequentially accumulating the results of multiplying a plurality of tap coefficients and input data,
a multiplier (4) that alternately and sequentially multiplies data obtained by sampling input data using a clock that is four times faster than the input data by an odd-numbered tap coefficient and an even-numbered tap coefficient among a plurality of tap coefficients; an odd-number side accumulator (5) that sequentially adds up the calculation results with the odd-numbered tap coefficients of 4) every clock at twice the speed of the input data; and an even-numbered tap coefficient of the multiplication unit (4). an even-number side accumulator (6) that sequentially accumulates the calculation results every inverted clock of a clock that is twice as fast as the input data; an output of the odd-number side accumulator (5); and an output of the even-number side accumulator (6). Addition unit (7) that adds
A digital transversal filter comprising: [Claim 3] A plurality of ROMs storing tap coefficients.
(321 to 326) and a plurality of shift registers (311 to 316) that delay the output of each of the ROMs, and read out the plurality of tap coefficients from each of the ROMs in response to address input. 3. The digital transversal filter according to claim 1, wherein the calculation is performed by inputting the signal through a shift register. 4. The plurality of ROMs are odd-numbered ROs.
M (321, 323, 325) and even number side ROM (3
4. The digital transversal filter according to claim 3, wherein the digital transversal filter is configured by multiplexing 22, 324, 326). 5. The digital transversal filter according to claim 3, wherein the tap coefficient read from each of the ROMs changes every clock of the calculation.