JPH0427015Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a PLL circuit, and particularly to a PLL circuit that can read reproduced signals with high precision both during normal reproduction and during high-speed search.

<Prior art> A head is rotated while being inclined relative to the longitudinal direction of the magnetic tape, and audio data is digitally recorded on the magnetic tape by the head,
and a digital audio tape device (R-DAT) that reads audio data from magnetic tape and plays it back.
There is a device (called a device).

The rotary head configuration used in such an R-DAT device has substantially the same configuration as the rotary head in a VTR. That is, as shown in Fig. 3, two heads HD1 and HD2 for both recording and playback are arranged on a rotating body RB at an interval of 180 degrees from each other, and the running trajectory of each head HD1 and HD2 on the magnetic tape MT surface is determined. The relative positional relationship between the magnetic tape MT and each head is determined such that the magnetic tape MT is inclined with respect to the longitudinal direction of the magnetic tape MT. And the rotating body RB is
Each time the heads HD1 and HD2 rotate by 180 degrees, each head HD1 and HD2 alternately contacts the magnetic tape MT for 90 degrees to record audio data on the magnetic tape or read audio data from the magnetic tape.

In addition, in the R-DAT device, a clock generator built in the signal processing circuit 11 generates a signal CLC (T) synchronized with the rotation of the cylinder (rotating head) shown in FIG.
is the rotation period), and a contact signal HTC is generated in synchronization with the contact between the head and the tape, and signal processing and recording/reproduction processing are performed in synchronization with this signal. For example, in the case of playback, (a) the audio data is read from the magnetic tape by the first and second heads HD1 and HD2 when the head and tape are in contact, that is, when the contact signal HTC is at a high level (periods T2 and T4); The read audio data is input to the PLL circuit 11a to reproduce the clock signal, and the audio data is input to the demodulator 11b in synchronization with the reproduced clock signal. (b) When the head and tape are not in contact, that is, when they are in contact. When signal HTC is low level (T1, T3 period)
The demodulator 11b performs error detection and correction processing on the audio data written in the RMA, performs DA conversion, and outputs the data.

That is, the head switching unit 12 inputs a switching signal to the switch circuit 13 every time the head rotates, and causes the switch circuit to alternately switch the reproduced signals from the first and second heads HD1 and HD2 to the signal processing circuit 11.
Enter.

As shown in FIG. 5, the PLL circuit 11a includes a phase difference comparator PDC that generates a voltage signal according to the phase difference between the reproduced signal SD and the reproduced clock signal CLS;
An amplifier AMP that amplifies the voltage signal, a voltage controlled oscillator VCO that generates a signal with a frequency proportional to the output voltage value of the amplifier, in other words, a frequency proportional to the phase difference between the reproduced signal and the reproduced clock signal, and a voltage controlled oscillator. A frequency divider circuit that divides the frequency of the signal output from 1/N to generate the reproduced clock signal CLS.
The demodulator 11b has a DVC, and the demodulator 11b receives the reproduced clock signal.
The reproduction signal SD is read in synchronization with CLS and stored in the built-in memory.

<Problems to be solved by the invention> Now, during normal playback, the tape running is stable, so there is little jitter (fluctuation in the time axis direction) in the playback signal. For this reason, the PLL
As for the circuit, the accuracy of signal reading is higher if the followability is slow and the frequency fluctuation is small.

Incidentally, the R-DAT device must read subcode data on the tape even during high-speed running such as searching. Furthermore, during high-speed search, the tape running becomes unstable compared to during normal playback, and the playback signal becomes more jittery. For this reason,
For high-speed searches, a PLL circuit with a fast response that can follow even minute frequency fluctuations in the reproduced signal is required.

However, in the past, the
Since the followability of the PLL circuit is determined, there was a problem in that the accuracy of signal reading during high-speed searches deteriorated, causing malfunctions.

In light of the above, an object of the present invention is to provide a PLL circuit that can read signals with high accuracy both during normal playback and during high-speed search.

<Means for Solving the Problems> FIG. 1 is a block diagram of a PLL circuit that is an embodiment of the present invention.

11a is a PLL circuit, 11b is a demodulator,
The PLL circuit 11a includes a phase comparator PDC, a regenerated clock generator CLG, and a low-pass filter LPF.
A switch section that bypasses the low-pass filter
Has SW.

The recovered clock generator CLG has an amplifier AMP, a voltage controlled oscillator VCO, and a frequency dividing circuit DVC.

<Operation> A low-pass filter LPF and a switch section SW for bypassing the low-pass filter are provided between the phase comparator PDC and the recovered clock generating section CLG.

When the low-pass filter LPF enters the closed loop of the PLL circuit, the followability of the PLL circuit deteriorates and becomes unable to follow fast frequency fluctuations. However, by bypassing the low-pass filter LPF, the followability improves and it becomes possible to follow fast frequency fluctuations.

Therefore, during normal playback, the phase comparator PDC
The output is input to the regenerated clock generator CLG via the low-pass filter LPF to generate the regenerated clock signal.
Generates CLS and uses phase comparator during high-speed search
The output of the PDC is input to the regenerated clock generator CLG without passing through the low-pass filter LPF to generate the regenerated clock signal CLS.

<Embodiment> FIG. 1 is a block diagram of a PLL circuit which is an embodiment of the present invention.

11a is a PLL circuit, 11b is a demodulator,
The PLL circuit 11 includes a phase comparator PDC, a reproduced clock generator CLG, a low-pass filter LPF, and a switch SW that bypasses the low-pass filter.
have.

The phase comparator PDC compares the phases of the bit-serial reproduced signal SD and the reproduced clock signal CLS, and generates a voltage signal E corresponding to the phase difference.

The regenerated clock generator CLG is a phase comparator PDC.
Amplifier AMP that amplifies the voltage signal E output from
The signals output from the voltage controlled oscillator VCO and the voltage controlled oscillator, which generate a signal having a frequency proportional to the voltage value of the amplifier, or in other words, a signal having a frequency proportional to the phase difference between the reproduced signal SD and the reproduced clock signal CLS, are 1. It has a frequency divider circuit DVC that divides the frequency into /N and generates a regenerated clock signal CLS, and a phase comparator PDC.
A low-pass filter LPF and a switch section SW for bypassing the low-pass filter are provided between the LPF and the reproduced clock generating section CLG.

During normal playback, a switching signal CS is generated from the system controller (not shown), and the switching signal causes the switch section SW to be in the open state, and the PLL circuit 1
A low pass filter LPF is inserted into the closed loop of 1a. As a result, the followability of the PLL circuit 11a decreases, and it becomes unable to follow fast frequency fluctuations, and the frequency fluctuations of the reproduced clock signal CLS are reduced, making it possible to read the reproduced signal with high precision.

On the other hand, during high-speed search, a switching signal CS is generated from the system controller (not shown), and the switching signal closes the switch section SW.
The low pass filter LPF is removed from the closed loop of the PLL circuit 11a. As a result, PLL circuit 11
The followability of a is improved, it becomes possible to follow fast frequency fluctuations of the reproduced signal SD, and it becomes possible to read the reproduced signal with high precision.

FIG. 2 shows a specific example of the PLL circuit in FIG. 1, and the same parts as in FIG. 1 are given the same reference numerals.

In the normal playback mode, when a high-level switching signal CS is generated, the transistor TR (corresponding to the switch section SW in Figure 1) turns on, and as a result, the low-pass filter LPF is activated by the resistors R1 to R3 and the capacitor C. configured. In other words, in normal playback mode, the low pass filter LPF
It is inserted between the phase comparator PDC and the recovered clock generator CLG of the PLL circuit.

On the other hand, when the high-speed search mode is entered, the switching signal CS
When becomes low level, the transistor TR is turned off, and as a result, the low-pass filter is no longer formed, and the low-pass filter is removed from the PLL circuit.

Although the present invention is applied to an R-DAT device, it goes without saying that the present invention can also be applied to a fixed head type digital audio tape device.

<Effects of the invention> According to the invention, there is provided a phase comparator that generates a voltage signal according to the phase difference between a reproduced signal and a reproduced clock signal, and a regenerator that generates a reproduced clock signal based on the voltage value of the voltage signal. A low-pass filter and a switch section for bypassing the low-pass filter are provided between the clock generator and the clock generator, and the output of the phase comparator is input to the reproduced clock generator during normal reproduction without going through the low-pass filter. , tracking performance can be reduced during normal playback, and tracking performance can be improved during high-speed playback, so signals can be read with high accuracy even during normal playback and high-speed search. .

[Brief explanation of the drawing]

Figure 1 is a block diagram of a PLL circuit that is one embodiment of the present invention, Figure 2 is a PLL circuit that is another embodiment of the present invention, and Figures 3 and 4 are explanatory diagrams of the R-DAT device. , FIG. 5 is a block diagram of a conventional PLL circuit. 11a...PLL circuit, 11b...demodulation section,
PDC: Phase comparator, CLG: Regenerated clock generator, LPF: Low-pass filter, SW: Switch.

Claims (1)

[Claims for Utility Model Registration] In a PLL circuit in a digital audio tape device that reproduces a clock signal included in a reproduced signal read from a magnetic tape and reads the reproduced signal in synchronization with the reproduced clock signal, A low-pass filter is provided between a phase comparator that generates a voltage signal according to a phase difference with the recovered clock signal, and a recovered clock generator that generates the recovered clock signal based on the voltage value of the voltage signal. A switch section is provided to bypass the phase comparator, and during playback, the output of the phase comparator is input to the recovered clock generation section via a low-pass filter, and during search, the output of the phase comparator is input to the recovered clock generation section without passing through the low-pass filter. A PLL circuit characterized by: