JPH04268639A - Digital signal processing processor - Google Patents

Abstract

PURPOSE:To shorten the processing time of a processor by providing a second private bus to shorten the machine cycle. CONSTITUTION:Not only a data RAM 2 and a data ROM 3 connected to a data bus 1 are provided but also a multiplier block having a multiplier 8 as the center and a computing element block having a computing element as the center are provided. Further, a first private bus 10 through which the multiplication result of the multiplier 8 is transferred to an input register 12 of the computing element 14 before being latched in an output register 9 and a second private bus 16 through which the operation result of the computing element 14 is transferred an input register 5 through a multiplexer 4 for the multiplier 8 before being latched in an output register 15.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing processor, and more particularly to a digital signal processing processor that performs exponentiation operations at high speed by improving arithmetic unit blocks and multiplier blocks.

0002

2. Description of the Related Art A conventional digital signal processor includes a program memory, a multiplier, and an arithmetic unit, and performs pipeline processing.

FIG. 3 is a block diagram of a multiplier and its peripheral circuits in a digital signal processor for explaining an example of such a conventional multiplier. As shown in FIG. 3, a conventional signal processing processor has a data bus 1 used for data transfer processing between registers or with memory, a data RAM 2 for storing various data, and a data RAM 2 for storing filter coefficients, constants, etc. It has a data ROM 3, a multiplier block, and an arithmetic unit block.

Among these, the multiplier block includes a multiplexer (MPX) 4A that inputs data from the data RAM 2 and the data bus 1 to create a multiplier, a multiplier register 5 that stores the data, and a data ROM 3 and the data bus 1. A multiplexer (MP
X) Multiplicand register 7 that stores 6 and its data
When the values of these registers 5 and 7 are multiplied, the multiplier 8
and a multiplication result output register 9 that outputs the multiplication result to the data bus 1. In addition, MPX4A selects whether the input to multiplier register 5 is data from data bus 1 or data from data RAM 2, and similarly, MPX6 selects whether input to multiplicand register 7 is data from data bus 1. Select either data or data from the data ROM3. Furthermore, the output of the multiplier 8 is latched into the output register 9, while being outputted to the arithmetic block as a multiplication result via the dedicated bus 10.

On the other hand, the arithmetic unit block includes a multiplexer (MPX) 11 that inputs data from the data bus 1 and the dedicated bus 10, input registers 12 and 13, and data latched in these registers 12 and 13. It is composed of an arithmetic unit 14 that performs arithmetic operations, and an arithmetic result output register 15 that outputs the arithmetic results to the data bus 1. Here, the aforementioned dedicated bus 10 transfers the multiplication result in the multiplier 8 to the input register 12 to the arithmetic unit 14 before latching it into the multiplication result output register 9. Also, M
PX11 inputs data to the input register 12 for the arithmetic unit 14 from the data bus 1 or from the dedicated bus 10.
Select whether to use data from

In order to perform processing at high speed, the digital signal processor configured as described above employs pipeline processing consisting of three stages: fetch/decode→operation execution→operation result latching as a program execution method. This situation will be explained below using FIG. 4.

FIG. 4 is a processing timing diagram for explaining pipeline processing of the digital signal processor in FIG. As shown in FIG. 4, the instruction at address n stored in the program memory is fetched and decoded at timing N. Next, at timing N+1, the arithmetic unit block has two input registers 12,
The data is transferred to 13 and the calculation is executed. On the other hand, the multiplier block transfers data to the multiplier register 5 and the multiplicand register 7 and executes multiplication. Such multiplier register 5
Since a bus is directly connected to the data RAM 2 and a bus is directly connected to the multiplicand register 7 from the data ROM 3, the data in the data RAM 2 and the data in the data ROM 3 can be multiplied at timing N+1. Further, at timing N+2, the arithmetic unit block latches the arithmetic result in the arithmetic result output register 15, and the multiplier block latches the multiplication result in the multiplication result output register 9. Therefore, at timing N+2, the operation result of the instruction at address n in the program memory is latched, the instruction at address n+1 in the program memory is executed, and the instruction at address n+2 in the program memory is fetched and decoded. All will be processed in parallel.

The digital signal processing processor described above has a configuration suitable for multiplication of the contents of a data RAM and the contents of a data ROM, such as in a digital filter, but it uses the calculation results of the calculation unit as a multiplier or a multiplicand Multiplication such as is described below.

FIG. 5 is an execution timing diagram of one program by the digital signal processing processor in FIG. As shown in FIG. 5, this program causes the digital signal processor described above to execute the calculation shown in equation (1).

[0010]y=(bx+a)x...(1)y=ax+
bx2 ...(2) Expanding this equation (1), it becomes equation (2), and this (2)
The formula is a "power" calculation formula that is frequently used when approximating functions such as SIN, COS, and EXP. Also,
Data x is stored in data RAM2, and constants a and b are stored in data ROM3. The arithmetic processing program to execute this equation (2) is as follows.
It consists of two steps. The first step is to execute the instruction at address n in the program memory. Specifically, data x is transferred from the data RAM 2 to the multiplier register 5.
At the same time, the data RO is transferred to the multiplicand register 7.
Transfer constant b from M3, perform multiplication in multiplier 8, and obtain bx
Create. The second step is program memory n+
This is the execution of the instruction at address 1, and at the same time the constant a is transferred from the data ROM 3 to the input register 13 to the arithmetic unit 14, the dedicated bus is transferred before the multiplication result bx in the multiplier 8 is latched to the multiplication result output register 9. 10 to the input register 12 to the arithmetic unit 14, and the arithmetic unit 14 performs addition to create a+bx. Further, the third step is the execution of the instruction at address n+2 in the program memory, but it is a no-operation since it is only a fetch decode. Furthermore, the fourth and final step is the execution of the instruction at address n+3 in the program memory. Here, since x has already been stored in the multiplier register 5, there is no need to retransfer it, and the value b latched in the operation result output register 15 is
x+a is transferred to the multiplicand register 7 and multiplied by the multiplier 8 to obtain (bx+a)x. In this way, six machine cycles from N to N+5 are required from fetching and decoding of the instruction at address n to latching the multiplication result of the instruction at address n+3.

[0011]

[Problems to be Solved by the Invention] Looking at the contents of the program in the conventional digital signal processing processor described above, in order to transfer the calculation result to the multiplicand register, the calculation result must be latched in the calculation result output register. A no-operation instruction is often included to adjust this timing. Also, for y=(cx+b)x+a)x, where the order of "power" has increased by one, 9 machines・
The number of cycles required increases by three machine cycles each time the order of the "power" increases by one. One of these machine cycles is a no-operation, and the processing efficiency is extremely low. As described above, conventional multiplications, such as "power" operations, in which the result of an operation in an arithmetic unit is used as a multiplier or multiplicand, have the drawback of requiring a long processing time.

An object of the present invention is to provide a digital signal processing processor that can shorten the processing time even for multiplications such as exponentiation operations in which the results of operations in arithmetic units are used as multipliers or multiplicands. .

[0013]

[Means for Solving the Problems] A digital signal processing processor of the present invention includes a program memory connected to a data bus, a multiplier that uses the output of the program memory as one input and exclusively performs multiplication, and an arithmetic unit that performs various logical operations based on data from a data bus; a first dedicated bus for supplying the multiplication results of the multiplier to the arithmetic unit; a second dedicated bus for supplying the other input of the arithmetic unit to the other input of the arithmetic unit; and an arithmetic result output register for latching the output of the arithmetic unit and outputting it to the data bus; By inputting the data to the multiplier via the second dedicated bus before latching it to the result output register, three-stage pipeline processing consisting of fetch/decode, operation execution, and operation result latching is executed. configured.

[0014]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a multiplier, an arithmetic unit, and their peripheral circuits in a digital signal processor for explaining one embodiment of the present invention. As shown in FIG. 1, this embodiment has a data bus 1, a data RAM 2, a data ROM 3, a multiplier block centered on a multiplier 8, and an arithmetic unit block centered on an arithmetic unit 14. There is. Note that the same numbers are given to the parts that are the same as those in the conventional example shown in FIG. 3 described above, and the explanation thereof will be omitted. This embodiment differs from the conventional example in that the first dedicated bus 10 is used to input the multiplication result in the multiplier 8 to the input register 12 to the arithmetic unit 14 before latching it to the multiplication result output register 9. Another point is that a second dedicated bus 16 is provided for outputting the output of the arithmetic unit 14 to the MPX 4. The operation of this processor will be explained below.

FIG. 2 is an execution timing diagram of one program by the digital signal processing processor in FIG. As shown in FIG. 2, this program is executed by a digital signal processor using equation (1),
+a) Executes the operation shown in x. Note that the data x is stored in the data RAM 2, and the constants a and b are stored in the data ROM 3, respectively. The arithmetic processing program of this embodiment consists of the following three steps. The first step is to program memory n.
This is the execution of the instruction at address, and data R is stored in multiplier register 5.
Data x is transferred from AM2, constant b is transferred from data ROM3 to multiplicand register 7, and multiplier 8
Multiply by and create bx. Next, the second step is to execute the instruction at address n+1 in the program memory,
At the same time as transferring the constant a from the data ROM 3 to the input register 13 to the arithmetic unit 14, before latching the multiplication result bx in the multiplier 8 to the multiplication result output register 9, the arithmetic unit A +
Create bx. Also, the third step is the program
Although the instruction at memory address n+2 is executed, since x has already been stored in the multiplier register 5, there is no need to retransfer it. Here, the calculation result bx+a in the calculation unit 14 is
Before being latched into the operation result output register 15, it is transferred to the multiplicand register 7 using the second dedicated bus 16, and multiplied using the multiplier 8 to obtain (bx+a)x.

In this way, the process from fetching and decoding the instruction at address n to latching the multiplication result of the instruction at address n+2 can be completed in 5 machine cycles from N to N+4, and the order of "power" is 1. Next increased y=((c
x+b)x+a)x results in 7 machine cycles,
Two machine cycles are required for each increase in the power order. However, in the conventional digital signal processor, the number of machine cycles increases by 3 each time the order of the "power" increases by one order, so the processing time can be reduced to 2/3 compared to the conventional one.

[0018]

[Effects of the Invention] As explained above, the digital signal processing processor of the present invention is provided with a dedicated bus for inputting the calculation results of the calculation unit to the multiplier before latching them to the calculation result output register. This has the effect that the conventional processing time can be reduced to 2/3 for multiplications such as exponentiation operations in which the result of an operation in an arithmetic unit is used as a multiplier or multiplicand.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multiplier, an arithmetic unit, and their peripheral circuits in a digital signal processing processor for explaining an embodiment of the present invention.

FIG. 2 is an execution timing diagram of one program by the digital signal processing processor in FIG. 1;

FIG. 3 is a block diagram of a multiplier, an arithmetic unit, and their peripheral circuits in a digital signal processing processor to explain a conventional example.

FIG. 4 is a processing timing diagram for explaining pipeline processing of the digital signal processor in FIG. 3;

FIG. 5 is an execution timing diagram of one program by the digital signal processing processor in FIG. 3;

[Explanation of symbols]

1 Data bus 2 Data RAM 3 Data ROM 4, 6, 11 Multiplexer (MPX) 5
Multiplier register 7 Multiplicand register 8 Multiplier 9 Multiplication result output register 10 First dedicated bus 12, 13 Input register 14 Arithmetic unit 15 Arithmetic result output register 16 Second dedicated bus

Claims (1)

[Claims] [Claim 1] A program connected to a data bus.
a multiplier that uses the output of the program memory as one input and performs multiplication exclusively; an arithmetic unit that performs various logical operations based on data from the data bus; a first dedicated bus for supplying the arithmetic unit to the arithmetic unit; a second dedicated bus for supplying the arithmetic result of the arithmetic unit to the other input of the multiplier; and an arithmetic result output register that is output to a data bus, and the arithmetic result of the arithmetic unit is inputted to the multiplier through the second dedicated bus before being latched to the arithmetic result output register, thereby fetching the result of the arithmetic operation. - A digital signal processing processor characterized by executing three-stage pipeline processing consisting of decoding, execution of calculations, and latching of calculation results.