JPH04266218A - Or circuit - Google Patents

Abstract

PURPOSE:To reduce the discharge time constant originated from a parasitic capacitance and toe increase the operating speed by employing the current voltage conversion circuit of parallel feedback type with a low input impedance. CONSTITUTION:When a voltage being a reference voltage or above at an input terminal 103 is fed to one of input terminals 104-10n or above, relevant TRs 4-n are conductive and a TR 3 is nonconductive. When all of the input terminals 104-10n are set to a reference voltage or below, the TRs 4-n are nonconductive and the TR 3 is conductive, The level of each collector current of the TRs 3,4-n is converted into a voltage level in a differential amplifier current voltage conversion circuit in which emitters are connected in common to a current setting element 22 and resistors 13, 14 are connected between collectors and bases to apply parallel feedback, and an OR output is obtained at an output terminal 201 connected to a resistor 11 and an inverted output is obtained at an output terminal 202 connected to the resistor 12.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OR circuit, and more particularly to a circuit that performs an OR process on high-speed data signals.

0002

[Prior Art] Conventionally, this type of circuit configuration has been CML.
A current switching type OR circuit based on a differential pair circuit configuration called (or ECL) was used.

FIG. 2 shows an example of the configuration of a conventional OR circuit. This OR circuit consists of a transistor 3 whose base is supplied with a reference voltage, and a plurality of transistors 4 to n whose respective emitters are commonly connected to the emitter of this transistor 3.
, a current value setting element 21 connected between the commonly connected emitters of the transistors 3 to n and the negative power supply, and a resistor 11 connected between the collector of the transistor 3 and the positive power supply.
This is a current switching OR circuit configured by connecting the collectors of the transistors 4 to n in common and a resistor 12 connected between the commonly connected collectors and a positive power supply.

0004

[Problems to be Solved by the Invention] The conventional OR circuit described above has a circuit configuration based on a differential pair circuit, so the operating speed is limited by the connection between the collector of the transistor 3 and the positive power supply. A resistor 12 connected between the resistor 11 and the commonly connected collectors of transistors 4 to n and the positive power supply, and a parasitic capacitor (such as transistor collector-base capacitance or wiring capacitance) to the collector of each transistor 3 to n The operating speed is determined by the charging/discharging time constant (synthesis). To improve the operating speed, firstly, the capacitance value of the parasitic capacitor can be reduced, and secondly, the resistance value of the resistors 11 and 12 connected to each collector can be reduced, but the first solution is This method has limitations in terms of transistor manufacturing technology and connection technology to other circuits. In the second solution, there is a limit to the reduction of the resistance value in order to secure the necessary amplitude to ensure operating margin against noise.

[0005]

[Means for Solving the Problems] The OR circuit of the present invention has the following features:
a first transistor whose base is given a reference voltage;
a plurality of second transistors, each having its base connected to each corresponding input terminal, each collector connected in common, and each emitter connected in common with the emitter of the first transistor; a first current value setting element connected between the commonly connected emitters of the two transistors and a negative power supply; and a first resistor connected between the collector of the first transistor and the positive power supply. , a second resistor provided between the commonly connected collectors of the second transistors and the positive power supply, and performs an OR operation of logic signals input to each of the input terminals. In a current switching type OR circuit that outputs a calculation result to one end of each of the first and second resistors, a third transistor has a third resistor connected between the base and the collector, and a third transistor between the base and the collector. a fourth transistor whose emitter is connected in common to the emitter of the third transistor, and between the commonly connected emitters of the third and fourth transistors and a negative power supply; a second current value setting element connected to the first current value setting element, and the collector of the first transistor is connected to the first current value setting element through a parallel connection between the third resistor and the base and collector of the third transistor. a commonly connected collector of the second transistor to the second resistor through a parallel connection of the fourth resistor and the base and collector of the fourth transistor; This is the configuration.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention. A transistor 3 whose base is connected to an input terminal 103 and supplied with a reference voltage, and a transistor 4 whose emitter is connected in common to the emitter of the transistor 3.
to transistor n, a current value setting element 21 connected between the commonly connected emitters of transistors 3 to n and the negative power supply, and a resistor 11 provided between the collector of transistor 3 and the positive power supply. , in a current switching type OR circuit constituted by a resistor 12 provided between the commonly connected collectors of transistors 4 to n and a positive power supply, a resistor is connected between the collector of transistor 3 and resistor 11. The base and collector of transistor 1 are connected in parallel to each other, and the resistor 1, which is a current-voltage conversion element, is connected to the mutually connected collectors of transistors 4 to n.
a transistor 2 with a resistor 14 connected in parallel between the transistors 2 and 2;
The base and collector of the transistor 1 are connected, and the transistor 1
A current value setting element 22 is connected between the commonly connected emitters of the transistors 2 and the negative power supply.

[0008] When a voltage of a sufficiently high potential to make the transistor conductive compared to the reference voltage applied to the input terminal 103 is applied to one or more input terminals from the input terminal 104 to the input terminal 10n, Input terminals 104-10
transistors 4 whose respective bases are connected to n
~n, the corresponding transistor becomes conductive,
Transistor 3 becomes non-conductive. In addition, the input terminal 104
When the reference voltage applied to input terminal 103 is at a sufficiently high potential to cause the transistor to conduct as compared to the voltage applied to ~10n, transistor 3 becomes conductive and transistors 4 to n become non-conductive. . A current set by the current value setting element 21 flows through the collector of the transistors 3 to n that are turned on.

In this way, the emitters of transistors 1 and 2, which are connected to the collector of transistor 3 and the collector of transistor 4 to transistor n, are connected to each other, and a resistor is connected between each collector and base to perform parallel parallel feedback. In the differential current-voltage conversion circuit, the current level is converted to a voltage level by the current-voltage conversion circuit connected to the collectors of transistors 3 to n that have become conductive. The logical sum of the logic signals applied to 10n is obtained at the output terminal 201, and its inverted output is obtained at the output terminal 202.

The parasitic capacitor charging time constant τr of the conventional OR circuit shown in FIG.
, if the capacitance value of the parasitic capacitor is Cs, τr=Rc
×Cs[s] The discharge time constant τf is expressed as τf=Ron, where Ron is the collector impedance when the transistor is conductive.
×Cs[s], and the resistance value Rc of the resistors 11 and 12 is sufficiently large compared to the collector impedance Ron during normal conduction, and the operating speed is limited by τr.

On the other hand, the parasitic capacitor charging time constant Tr in the OR circuit of the present invention shown in FIG.
It is expressed as s[s].

Here, the output impedance Ro of the current-voltage conversion circuit is determined by the resistance values of the feedback resistors 13 and 14 being Rf,
If the mutual conductance of transistors 1 and 2 is gm, and the current amplification factor of transistors 1 and 2 is Bf, then Ro=1
/gm+Rf/(Bf+1), and the resistance value Rc of the collector resistors 11 and 12 is usually
The value will be smaller. Therefore, Tr<τr, and the operating speed can be improved.

[0013]

[Effects of the Invention] As explained above, the OR circuit of the present invention shortens the discharge time constant of the parasitic capacitance that limits the operating speed by using a parallel-parallel feedback current-voltage conversion circuit with low input/output impedance. The operating speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional OR circuit.

[Explanation of symbols]

1 to 5, n Transistors 11 to 14 Resistors 21, 22 Current value setting elements 103 to 105, 10n Input terminals 201, 20
2 Output terminal

Claims (1)

[Claims] 1. A first transistor whose base is supplied with a reference voltage; each base connected to a corresponding input terminal, each collector connected in common, and each emitter connected to the first transistor; a plurality of second transistors commonly connected together with the emitters; a first current value setting element connected between the commonly connected emitters of the first and second transistors and a negative power supply; a first resistor provided between the collector of the first transistor and the positive power source; and a second resistor provided between the commonly connected collector of the second transistor and the positive power source; In a current switching type OR circuit that performs an OR operation on logic signals input to each of the input terminals and outputs the operation result to one end of each of the first and second resistors, a third transistor to which a third resistor is connected; a fourth transistor to which a fourth resistor is connected between the base and the collector and whose emitter is commonly connected to the emitter of the third transistor; a second current value setting element connected between commonly connected emitters of the third and fourth transistors and a negative power supply; the first transistor through a parallel connection with the base and collector of the third transistor;
the commonly connected collectors of the second transistors to the second resistor through a parallel connection of the fourth resistor and the base and collector of the fourth transistor. An OR circuit characterized in that it is connected.