JPH0331014B2 - - Google Patents
Info
- Publication number
- JPH0331014B2 JPH0331014B2 JP55026954A JP2695480A JPH0331014B2 JP H0331014 B2 JPH0331014 B2 JP H0331014B2 JP 55026954 A JP55026954 A JP 55026954A JP 2695480 A JP2695480 A JP 2695480A JP H0331014 B2 JPH0331014 B2 JP H0331014B2
- Authority
- JP
- Japan
- Prior art keywords
- collector
- transistor
- voltage
- input
- constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
この発明は、論理回路、特に複数の入力端子を
有する電流切換型論理回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic circuit, and particularly to a current switching type logic circuit having a plurality of input terminals.
一般に論理回路のスイツチング特性は、立ち上
がり時間立ち下がり時間および伝搬遅延時間が重
要な要素であり特に、高速動作を特徴とする電流
切換型論理回路では、優れたスイツチング特性を
得る事が大きな目標となつている。 In general, the switching characteristics of logic circuits are determined by the important factors such as rise time, fall time, and propagation delay time. In particular, for current switching type logic circuits, which are characterized by high-speed operation, obtaining excellent switching characteristics is a major goal. ing.
第1図は、n個の入力端子をもつ従来の電流切
換型論理回路について示したものでありベースを
入力端子とし並列接続された入力トランジスタ
T1〜Toと、エミツタがT1〜Toの共通エミツタに
接続されると共に定電流源を介して第1の電圧源
に接続され、ベースが基準電圧源に接続された基
準トランジスタTRのコレクタをそれぞれ負荷抵
抗を介して第2の電圧源に接続し、T1〜Toのコ
レクタ電圧の変化を出力として取り出すものであ
る。しかしながらこの種の電流切換型論理回路に
おいては入力トランジスタの全てのコレクタが共
通接続されているため入力トランジスタ数の増加
に伴ない入力トランジスタの共通コレクタ部のコ
レクタ容量が増大し負荷抵抗値とコレクタ容量値
の積で決まる負荷抵抗部の時定数が大きくなり、
立ち上がり時間、立ち下がり時間、伝搬遅延時間
が増大する欠点があつた。 Figure 1 shows a conventional current-switching logic circuit with n input terminals, in which input transistors are connected in parallel with the base as the input terminal.
T 1 to T o and a reference transistor T R whose emitters are connected to the common emitter of T 1 to T o and to the first voltage source via a constant current source, and whose base is connected to the reference voltage source. The collectors of each are connected to a second voltage source via a load resistor, and changes in collector voltage from T 1 to T o are taken out as an output. However, in this type of current switching logic circuit, all the collectors of the input transistors are commonly connected, so as the number of input transistors increases, the collector capacitance of the common collector part of the input transistors increases, and the load resistance value and collector capacitance increase. The time constant of the load resistance section, which is determined by the product of the values, becomes larger,
The disadvantage was that the rise time, fall time, and propagation delay time increased.
本発明の目的は従来の回路における本質的欠点
を軽減し入力端子数が増加した場合においても優
れたスイツチング特性を有する回路を提供するこ
とにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that alleviates the essential drawbacks of conventional circuits and has excellent switching characteristics even when the number of input terminals increases.
この発明によれば、ベースを入力端子とする複
数個並列接続された入力トランジスタ群と、エミ
ツタが該入力トランジスタ群のエミツタに接続さ
れると共に定電流源を介して第1の電圧源に接続
され、コレクタが抵抗を介して第2の電圧源に接
続されると共にベースが基準電圧源に接続された
基準トランジスタTRと、エミツタが前記入力ト
ランジスタ群のコレクタに接続されコレクタが抵
抗を介して第2の電圧源に接続されると共にベー
スに定電圧を印加する定電圧トランジスタTVを
有しTVのコレクタの電圧変化を出力として取り
出す回路において、入力トランジスタ数の増加に
伴ないコレクタ容量が増加する入力トランジスタ
のコレクタの電圧変化を小さくし、かつコレクタ
容量の小さな定電圧トランジスタTVのコレクタ
の電圧変化を出力として取り出すことにより、入
力トランジスタ数が増加しても優れたスイツチン
グ特性を有する論理回路が得られる。 According to this invention, a plurality of parallel-connected input transistor groups each having a base as an input terminal, and an emitter connected to the emitter of the input transistor group and connected to a first voltage source via a constant current source. , a reference transistor TR whose collector is connected to a second voltage source via a resistor and whose base is connected to a reference voltage source; In a circuit that has a constant voltage transistor T V that is connected to the second voltage source and applies a constant voltage to its base, and extracts voltage changes at the collector of the TV as an output, the collector capacitance increases as the number of input transistors increases. A logic circuit that has excellent switching characteristics even when the number of input transistors increases, by reducing the voltage change at the collector of the input transistor and extracting the voltage change at the collector of the constant voltage transistor TV , which has a small collector capacitance, as an output. is obtained.
第2図により、本発明の第1の実施例を入力端
子数n個の場合について示す。ベースを入力端子
とし、並列接続された入力トランジスタT1〜To
と、エミツタが入力トランジスタ群のエミツタに
接続されると共に定電流源を介して第1の電圧源
に接続されベースが基準電圧源に接続された基準
トランジスタTRと、エミツタが入力トランジス
タT1〜Toのコレクタに接続されベースが定電圧
源に接続された定電圧トランジスタTVから成り
定電圧トランジスタTVおよび基準トランジスタ
TRのコレクタをそれぞれ負荷抵抗R1およびR2を
介して電圧源2に接続し、定電圧トランジスタ
TVのコレクタの電圧変化を出力として取り出す
回路である。 FIG. 2 shows a first embodiment of the present invention in the case where the number of input terminals is n. Input transistors T 1 to T o connected in parallel with the base as the input terminal
, a reference transistor TR whose emitter is connected to the emitter of the input transistor group, and which is connected to the first voltage source via a constant current source and whose base is connected to the reference voltage source, and whose emitter is connected to the input transistor T 1 ~ Consisting of a constant voltage transistor T V connected to the collector of T o and whose base is connected to a constant voltage source, it consists of a constant voltage transistor T V and a reference transistor.
The collectors of T R are connected to the voltage source 2 through load resistors R 1 and R 2 , respectively, and the constant voltage transistor
This is a circuit that extracts voltage changes on the TV collector as output.
該回路において定電圧トランジスタのベース電
位をトランジスタT1〜ToおよびTVが飽和しない
範囲内の適当な電位に設定すれば入力トランジス
タT1〜Toの少なくとも1個以上が導通すれば定
電圧トランジスタTVは導通しそれ以外の場合に
は、TVはしや断状態になりTVのコレクタの電圧
変化を出力として取り出せば第1図に示した従来
の電流切換型論理回路と全く同じ論理動作を実現
出来る。 In this circuit, if the base potential of the constant voltage transistor is set to an appropriate potential within a range that does not saturate the transistors T 1 to T o and TV , the voltage will be constant if at least one of the input transistors T 1 to T o is conductive. The transistor TV is conductive, and in other cases, the TV is turned off.If the voltage change at the collector of the TV is taken out as an output, it is exactly the same as the conventional current switching type logic circuit shown in Figure 1. Logical operations can be realized.
該回路において定電圧トランジスタのエミツタ
電流は入力トランジスタの各々のコレクタ電流の
総和に等しくエミツタ電流に依存する定電圧トラ
ンジスタのVBEの変化は入力トランジスタのしや
断時と導通時のTBEの変化にほぼ等しい。したが
つて入力と出力の論理振巾の等しい通常の電流切
換論理回路においては、定電圧トランジスタの
VBEの変化および入力トランジスタのコレクタ電
位の変化は出力論理振巾の約1/2となり、スイツ
チング時における入力端子からみたコレクタ電圧
の変化が帰還容量を通して帰還するミラー効果が
減少し、スイツチング特性が改善される。 In this circuit, the emitter current of the constant voltage transistor is equal to the sum of the collector currents of each of the input transistors and depends on the emitter current.The change in V BE of the constant voltage transistor is the change in T BE when the input transistor is disconnected and conductive. approximately equal to. Therefore, in a normal current switching logic circuit where the input and output logic amplitudes are equal, the constant voltage transistor
Changes in V BE and changes in the collector potential of the input transistor are approximately 1/2 of the output logic amplitude, reducing the Miller effect in which changes in the collector voltage seen from the input terminal during switching are fed back through the feedback capacitance, and improving the switching characteristics. Improved.
また、入力トランジスタT1〜Toの全てのトラ
ンジスタがしや断の状態から、いずれかが導通の
状態になつた場合、トランジスタT1〜Toおよび
TVのコレクタ容量は定電流源の電流値によつて
決定する速度で放電されるために、スイツチング
特性は、容量値と端子電圧の変化の積で表わされ
るスイツチング時の充放電々荷の総和に関係す
る。 Furthermore, when all of the input transistors T 1 to T o change from a OFF state to one of them to a conductive state, the transistors T 1 to T O and
Since the collector capacitance of a TV is discharged at a rate determined by the current value of the constant current source, the switching characteristics are the sum of charging and discharging loads during switching, which is expressed as the product of the capacitance value and the change in terminal voltage. related to.
従つてT1〜ToおよびTVのコレクタ容量が各々
すべて等しくその値がCであり、入力および出力
の論理振巾をVWとした場合、スイツチング時の
各コレクタ容量の放電々荷の総和Qを第1図にお
いてQ1とすれば
Q1=C×n×VW=nCVw
で表わされ同様に第2図の回路においてQ2は
Q2=C×n×VW/2+C×VW
=(1+n/2)・C・VW
となり本回路を用いた場合、放電々荷の総和を
(n/2−1)・C・VWだけ減少出来立ち下がりおよ
びスイツチング時間を速くできる。さらに入力ト
ランジスタT1〜Toが導通状態からしや断状態に
変化した場合、共通コレクタの容量はTVを介し
て充電され共通コレクタ電位が上昇するため、ベ
ースが定電圧源に接続されたTVのベース・エミ
ツタ電圧VBEが減少する。VBEの変化に対するコ
レクタ電流の変化は、指数関数的でありVBEのわ
ずかな減少によりTVのコレクタ電流は、急激に
減少するため、出力電圧の変化は、入力トランジ
スタ数の増加に伴なう共通コレクタのコレクタ容
量が増加しても、わずかな遅れを要するだけで
TVのコレクタ容量値と負荷抵抗値との積である
時定数によつて決定され、優れたスイツチング特
性を有する論理回路が得られる。 Therefore, if the collector capacitances of T 1 to T o and T V are all equal and their value is C, and the logical amplitude of input and output is V W , then the sum of the discharge loads of each collector capacitance during switching is If Q is Q 1 in Fig. 1, then Q 1 = C x n x V W = nCVw, and similarly, Q 2 in the circuit of Fig. 2 is Q 2 = C x n x V W /2 + C x V. W = (1+n/2).C.V W , and when this circuit is used, the total discharge load can be reduced by (n/2-1).C.V W , and the falling and switching times can be made faster. Furthermore, when the input transistors T 1 to T o change from a conductive state to a depleted state, the capacitance of the common collector is charged through T V and the common collector potential increases, so that the base is connected to a constant voltage source. The base-emitter voltage V BE of TV decreases. The change in the collector current with respect to the change in V BE is exponential, and the collector current of the TV decreases rapidly with a slight decrease in V BE . Therefore, the change in the output voltage will change as the number of input transistors increases. Increasing the collector capacity of the common collector requires only a small delay.
This is determined by the time constant, which is the product of the collector capacitance value of the TV and the load resistance value, and a logic circuit with excellent switching characteristics can be obtained.
第3図によりこの発明の第2の実施例を示す。
第1の実施例との違いは定電圧トランジスタTV
のベースが電圧源2に直接接続されていることで
あり出力論理振巾が小さい場合に適用出来、T1
〜Toの1個以上が導通すれば、TVは導通しそれ
以外の場合にはTVはしや断状態になりTVのコレ
クタ電圧の変化を出力として取り出せば第1の実
施例と全く同じ論理動作および本発明の効果が得
られる。前述した実施例につき、この発明の範囲
内で種々の変形を施すことが可能であり本発明は
特許請求の範囲記載の全てにおよびものである。 FIG. 3 shows a second embodiment of the invention.
The difference from the first embodiment is that the constant voltage transistor T V
Since the base of is directly connected to voltage source 2, it can be applied when the output logic width is small, and T 1
~ If one or more of T o is conductive, the TV is conductive; otherwise, the TV is in a disconnected state.If the change in the collector voltage of the TV is taken out as an output, the result is the same as the first embodiment. Exactly the same logical operation and effects of the invention are obtained. Various modifications can be made to the embodiments described above within the scope of the present invention, and the present invention encompasses all of the scope of the claims.
第1図は従来の論理回路を示す回路図である。
第2図および第3図は、この発明による論理回路
の第1および第2の実施例を示す回路図である。
T1〜To……トランジスタ、R1,R2……抵抗、
I1……定電流源、1,2……電圧源、3,4,
5,6,IN1〜INo……端子。
FIG. 1 is a circuit diagram showing a conventional logic circuit.
2 and 3 are circuit diagrams showing first and second embodiments of the logic circuit according to the present invention. T 1 ~ T o ...transistor, R1 , R2 ...resistance,
I 1 ... Constant current source, 1, 2 ... Voltage source, 3, 4,
5, 6, IN 1 ~ IN o ... terminal.
Claims (1)
論理回路において、上記複数の入力トランジスタ
の共通接続されたコレクタと負荷素子との間にベ
ースに定電圧が印加されたトランジスタを介挿
し、該介挿されたトランジスタと前記負荷素子と
の接続部の電圧変化を出力として取り出すように
したことを特徴とする論理回路。1. In a current switching logic circuit having a plurality of input transistors, a transistor to which a constant voltage is applied to the base is inserted between the commonly connected collectors of the plurality of input transistors and the load element, and A logic circuit characterized in that a voltage change at a connection between a transistor and the load element is extracted as an output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2695480A JPS56123128A (en) | 1980-03-04 | 1980-03-04 | Logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2695480A JPS56123128A (en) | 1980-03-04 | 1980-03-04 | Logic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56123128A JPS56123128A (en) | 1981-09-28 |
JPH0331014B2 true JPH0331014B2 (en) | 1991-05-02 |
Family
ID=12207541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2695480A Granted JPS56123128A (en) | 1980-03-04 | 1980-03-04 | Logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56123128A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69426713T2 (en) * | 1993-06-16 | 2001-09-06 | Koninklijke Philips Electronics N.V., Eindhoven | Integrated logic circuit with logic gates with a single input |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54109363A (en) * | 1978-02-15 | 1979-08-27 | Nec Corp | Gate circuit |
-
1980
- 1980-03-04 JP JP2695480A patent/JPS56123128A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54109363A (en) * | 1978-02-15 | 1979-08-27 | Nec Corp | Gate circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS56123128A (en) | 1981-09-28 |
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