JPH04264557A - Formation of fine pattern - Google Patents

Formation of fine pattern

Info

Publication number
JPH04264557A
JPH04264557A JP2591491A JP2591491A JPH04264557A JP H04264557 A JPH04264557 A JP H04264557A JP 2591491 A JP2591491 A JP 2591491A JP 2591491 A JP2591491 A JP 2591491A JP H04264557 A JPH04264557 A JP H04264557A
Authority
JP
Japan
Prior art keywords
resist
layer
imidazole
silylating
silylation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2591491A
Other languages
Japanese (ja)
Inventor
Masanori Soenosawa
添ノ澤 正宣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2591491A priority Critical patent/JPH04264557A/en
Publication of JPH04264557A publication Critical patent/JPH04264557A/en
Pending legal-status Critical Current

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  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To enable silylation to be conducted at room temp. and to form good fine patterns by silylating a resist by using a silylating agent contg. imidazole to be a catalyst for silylation or its deriv. CONSTITUTION:The polyimide resist 2 to form a lower layer resist is applied on a semiconductor substrate 1 and thereafter, a novolak resist 3 to form an upper layer resist is applied thereon. The upper layer resist 3 is then subjected to exposing and developing to form patterns and thereafter, the silylating agent 7 prepd. by incorporating the imidazole into, for example, chlorotrimethyl silane is sprayed at room temp. to form a silylated layer 9 on the surface of the upper layer resist 3. The fine patterns 10 are then formed by RIE etching using gaseous O2 plasma with the silylating layer 9 as a mask.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は半導体製造工程に関し、
特にリソグラフィ工程に関するものである。
[Industrial Application Field] The present invention relates to a semiconductor manufacturing process.
In particular, it relates to lithography processes.

【0002】0002

【従来の技術】従来技術による微細パターンの形成方法
として、シリコン添加2層レジスト法について図3(a
)〜(d)を参照して説明する。
[Prior Art] As a conventional method for forming fine patterns, the silicon-added two-layer resist method is shown in FIG. 3(a).
) to (d).

【0003】はじめに図3(a)に示すように、半導体
基板1上に下層レジスト(例えばポリイミド系レジスト
)5を塗布し、上層レジスト(例えばノボラック系レジ
スト)6を塗布する。
First, as shown in FIG. 3A, a lower layer resist (eg, polyimide resist) 5 is coated on a semiconductor substrate 1, and an upper layer resist (eg, novolac resist) 6 is coated.

【0004】つぎに図3(b)に示すように、上層レジ
スト6を露光・現像してパターンを形成する。
Next, as shown in FIG. 3(b), the upper resist 6 is exposed and developed to form a pattern.

【0005】つぎに図3(c)に示すように、全体を加
熱しながらシリル化剤(例えばヘキサメチルジシラザン
またはクロロトリメチルシランなど)8の蒸気を当てる
と、シリル化が可能な上層レジスト6の表面がシリル化
されて、シリル化層9が形成される。
Next, as shown in FIG. 3(c), by applying vapor of a silylating agent (such as hexamethyldisilazane or chlorotrimethylsilane) 8 while heating the entire resist, an upper resist 6 that can be silylated is formed. The surface of is silylated to form a silylated layer 9.

【0006】つぎに図3(d)に示すように、シリル化
層9をマスクとしてO2 RIEのドライエッチングを
行なうことにより微細パターン10を形成する。
Next, as shown in FIG. 3(d), a fine pattern 10 is formed by dry etching by O2 RIE using the silylated layer 9 as a mask.

【0007】通常上層レジストとしてはノボラック樹脂
をベースとしたレジストが用いられる。化学式(1)に
示すように、左辺第1項にある上層レジストのノボラッ
ク系レジストの分子構造に含まれる水酸基に、左辺第2
項にあるシリル化剤が直接反応してシリル化して、右辺
第1項にあるシリル化されたノボラック系レジストが形
成される。
[0007] Usually, a resist based on novolac resin is used as the upper layer resist. As shown in chemical formula (1), the hydroxyl group contained in the molecular structure of the novolak resist of the upper layer resist, which is the first term on the left side, has the second term on the left side.
The silylating agent in the first term on the right side directly reacts and silylates, forming the silylated novolak resist in the first term on the right side.

【0008】[0008]

【0009】[0009]

【発明が解決しようとする課題】レジストの性能向上を
目的として、ノボラック系樹脂の分子構造に側壁を導入
するなどの改良が行なわれ、サブミクロンパターンの上
層レジストなどに用いられるレジストベースの分子構造
が複雑になっている。
[Problems to be Solved by the Invention] In order to improve the performance of resists, improvements such as the introduction of sidewalls to the molecular structure of novolac resins have been made, and the molecular structure of resist bases used for upper layer resists of submicron patterns, etc. has become complicated.

【0010】そのため立体構造が大変複雑になり、ノボ
ラック系樹脂の反応部である水酸基を覆い隠して反応し
にくくしてしまうことがある。レジストの分子構造に含
まれる水酸基に直接シリル基を導入する際に、このよう
な立体障害のため反応性が乏しくシリル化がかなり困難
である。
[0010] As a result, the three-dimensional structure becomes very complicated, and the hydroxyl group, which is the reactive part of the novolak resin, may be covered up, making it difficult to react. When a silyl group is directly introduced into a hydroxyl group contained in the molecular structure of a resist, silylation is quite difficult due to poor reactivity due to such steric hindrance.

【0011】O2 ガスプラズマを用いたRIEエッチ
ングに対する充分な耐性を得るまでシリル基を導入する
には、反応温度を120〜150℃以上の高温に設定し
なければならない。ところがシリル化の温度が高くなる
とレジストパターンが流動して変形するという問題があ
った。
[0011] In order to introduce silyl groups to the extent that sufficient resistance to RIE etching using O2 gas plasma is obtained, the reaction temperature must be set at a high temperature of 120-150°C or higher. However, when the silylation temperature becomes high, there is a problem in that the resist pattern flows and becomes deformed.

【0012】0012

【課題を解決するための手段】本発明の微細パターンの
形成方法は、半導体基板の一主面にレジスト膜を形成し
たのち露光・現像する工程と、シリル化の触媒となるイ
ミダゾールおよびイミダゾールの誘導体のうち1つを含
有するシリル化剤を用いて前記レジスト膜の表面をシリ
ル化する工程とを含むものである。
[Means for Solving the Problems] The method for forming a fine pattern of the present invention includes a step of forming a resist film on one main surface of a semiconductor substrate and then exposing and developing it, and imidazole and an imidazole derivative serving as a silylation catalyst. and silylating the surface of the resist film using a silylating agent containing one of the above.

【0013】[0013]

【作用】シリル化剤に触媒となるイミダゾールまたはそ
の誘導体を含有させることにより化学式(2)に示すよ
うに、左辺第1項にあるシリル化剤に左辺第2項にある
イミダゾールが結合して、右辺第1項にある反応性の高
いシリル化剤となる。つぎに化学式(3)に示すように
、左辺第1項にあるノボラック系レジストが左辺第2項
にある反応性の高いシリル化剤と結合して、右辺第1項
にあるシリル化されたノボラック系レジストが形成され
る。
[Operation] By incorporating imidazole or its derivative as a catalyst into the silylating agent, as shown in chemical formula (2), the imidazole in the second term on the left side bonds to the silylating agent in the first term on the left side, It becomes a highly reactive silylating agent, which is the first term on the right side. Next, as shown in chemical formula (3), the novolak resist in the first term on the left side combines with the highly reactive silylating agent in the second term on the left side, and the silylated novolac resist in the first term on the right side is formed. A system resist is formed.

【0014】[0014]

【0015】[0015]

【実施例】本発明の第1の実施例について、図1(a)
〜(d)を参照して説明する。
[Example] Regarding the first example of the present invention, FIG. 1(a)
This will be explained with reference to (d).

【0016】はじめに図1(a)に示すように、半導体
基板1に下層レジストとなるポリイミド系レジスト2を
塗布してから、上層レジストとなるノボラック系レジス
ト3を塗布する。
First, as shown in FIG. 1A, a polyimide resist 2 serving as a lower resist layer is applied to a semiconductor substrate 1, and then a novolac resist 3 serving as an upper resist layer is applied.

【0017】つぎに図1(b)に示すように、上層レジ
スト3を露光し現像することによってパターンを形成す
る。
Next, as shown in FIG. 1(b), the upper resist 3 is exposed and developed to form a pattern.

【0018】つぎに図1(c)に示すように、シリル化
剤として例えばクロロトリメチルシランにイミダゾール
を含有させたもの7を室温で噴霧して、上層レジスト3
の表面にシリル化層9を形成する。
Next, as shown in FIG. 1(c), a silylating agent 7 containing imidazole in chlorotrimethylsilane, for example, is sprayed at room temperature to form the upper resist layer 3.
A silylated layer 9 is formed on the surface of the silylated layer 9.

【0019】つぎに図1(d)に示すように、シリル化
層9をマスクとしてO2 ガスプラズマを用いたRIE
エッチングにより、微細パターン10が形成される。
Next, as shown in FIG. 1(d), RIE was performed using O2 gas plasma using the silylated layer 9 as a mask.
A fine pattern 10 is formed by etching.

【0020】つぎに本発明の第2の実施例について、図
2(a)〜(d)を参照して説明する。
Next, a second embodiment of the present invention will be explained with reference to FIGS. 2(a) to 2(d).

【0021】はじめに図2(a)に示すように、半導体
基板1に下層レジストとなるノボラック系レジスト3を
塗布してから、上層レジストとなるメタクリル系レジス
ト4を塗布する。
First, as shown in FIG. 2A, a novolac resist 3 serving as a lower layer resist is applied to a semiconductor substrate 1, and then a methacrylic resist 4 serving as an upper layer resist is applied.

【0022】つぎに図2(b)に示すように、上層レジ
スト4を露光し現像することによってパターンを形成す
る。
Next, as shown in FIG. 2(b), the upper resist 4 is exposed and developed to form a pattern.

【0023】つぎに図2(c)に示すように、シリル化
剤として例えばクロロトリメチルシランにイミダゾール
を含有させたもの7を室温で噴霧して、露出した下層レ
ジスト3の表面にシリル化層9を形成する。
Next, as shown in FIG. 2C, a silylating agent 7 containing imidazole in chlorotrimethylsilane, for example, is sprayed at room temperature to form a silylated layer 9 on the exposed surface of the lower resist 3. form.

【0024】つぎに図2(d)に示すように、シリル化
層9をマスクとしてO2 ガスプラズマを用いたRIE
法により上層パターン4および下層レジスト3をエッチ
ングして、反転した微細パターン10が形成される。
Next, as shown in FIG. 2(d), RIE was performed using O2 gas plasma using the silylated layer 9 as a mask.
The upper layer pattern 4 and the lower layer resist 3 are etched by a method to form an inverted fine pattern 10.

【0025】[0025]

【発明の効果】微細パターン形成において、シリル化の
触媒となるイミダゾールまたはその誘導体を含有するシ
リル化剤を用いてレジストをシリル化する。その結果室
温でシリル化が可能になり、良好な微細パターンを形成
することができた。
Effects of the Invention In forming fine patterns, a resist is silylated using a silylating agent containing imidazole or a derivative thereof serving as a silylation catalyst. As a result, silylation became possible at room temperature and a good fine pattern could be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の第1の実施例を工程順に示す断面図で
ある。
FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in order of steps.

【図2】本発明の第2の実施例を工程順に示す断面図で
ある。
FIG. 2 is a cross-sectional view showing a second embodiment of the present invention in order of steps.

【図3】従来技術による微細パターンの形成方法を工程
順に示す断面図である。
FIG. 3 is a cross-sectional view showing a method for forming a fine pattern according to the prior art in order of steps;

【符号の説明】[Explanation of symbols]

1    半導体基板 2    ポリイミド系レジスト 3    ノボラック系レジスト 4    メタクリル系レジスト 5    下層レジスト 6    上層レジスト 7    イミダゾールを含有したシリル化剤8   
 シリル化剤 9    シリル化層 10    形成された微細パターン
1 Semiconductor substrate 2 Polyimide resist 3 Novolac resist 4 Methacrylic resist 5 Lower layer resist 6 Upper layer resist 7 Imidazole-containing silylation agent 8
Silylating agent 9 Silylated layer 10 Formed fine pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体基板の一主面にレジスト膜を形
成したのち露光・現像する工程と、シリル化の触媒とな
るイミダゾールおよびイミダゾールの誘導体のうち1つ
を含有するシリル化剤を用いて前記レジスト膜の表面を
シリル化する工程とを含む微細パターンの形成方法。
1. A step of forming a resist film on one main surface of a semiconductor substrate and then exposing and developing it, and using a silylation agent containing one of imidazole and an imidazole derivative as a catalyst for silylation. A method for forming a fine pattern, including a step of silylating the surface of a resist film.
JP2591491A 1991-02-20 1991-02-20 Formation of fine pattern Pending JPH04264557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2591491A JPH04264557A (en) 1991-02-20 1991-02-20 Formation of fine pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2591491A JPH04264557A (en) 1991-02-20 1991-02-20 Formation of fine pattern

Publications (1)

Publication Number Publication Date
JPH04264557A true JPH04264557A (en) 1992-09-21

Family

ID=12179048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2591491A Pending JPH04264557A (en) 1991-02-20 1991-02-20 Formation of fine pattern

Country Status (1)

Country Link
JP (1) JPH04264557A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001003173A1 (en) * 1999-07-01 2001-01-11 Lam Research Corporation Method for patterning a layer of a low dielectric constant material
JP2011049468A (en) * 2009-08-28 2011-03-10 Tokyo Ohka Kogyo Co Ltd Surface treatment agent and surface treatment method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001003173A1 (en) * 1999-07-01 2001-01-11 Lam Research Corporation Method for patterning a layer of a low dielectric constant material
JP2011049468A (en) * 2009-08-28 2011-03-10 Tokyo Ohka Kogyo Co Ltd Surface treatment agent and surface treatment method

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