JPH0426220A - Adaptive equalizer - Google Patents

Abstract

PURPOSE:To enable equalization processing for a high-speed signal even when the calculation of each coefficient updating part is carried out at low speed by providing the plural coefficient updating parts and switching those outputs by a switching means. CONSTITUTION:After a signal from a transmission line is modulated, it is converted to a received signal y(n) being a discrete time signal by an A/D converter, afterwards inputted to an input terminal 11. On the other hand, a frequency divider 22 divides the frequency of a timing signal CLK inputted from an input terminal 12 and according to a select signal S22 as the result of the frequency division, respective selectors 21a and 19 are controlled to be switched in a selector part 21. Based on the select signal S22, the selector 19 supplies an error signal e(L) to be outputted from a subtracter 18 while switching it to first and second coefficient updating parts 20-1 and 20-2. By using a received signal y(L) inputted from the input terminal 11 and the error signal e(L) to be outputted from the selector 19, the coefficient updating parts 20-1 and 20-2 alternately execute algorythm for updating coefficients. Thus, even when the calculation is carried out at low speed in the coefficient updating part, the high-speed signal can be equalized.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a linear equalizer and a decision feedback equalizer that follow line fluctuations and eliminate code amount interference at decision points in digital data transmission. This relates to adaptive equalizers such as the following.

(Prior art) Conventionally, as a technology in this field, for example, C, F
, N. Cowan, P., M. Grant (eds.), Adaptive Filters.
” (1985) Prentice Hall (USA) P.
There was one described in 29-34. The configuration will be explained below using figures.

FIG. 2 is a block diagram showing an example of the configuration of a linear equalizer, which is one of conventional adaptive equalizers.

This linear equalizer modulates a signal from a transmission path (not shown) and converts it into analog/digital conversion (hereinafter referred to as A//
The first input signal y (referred to as D conversion)
input terminal 1, and a second input terminal to which the timing signal CLK is input.
It has an input terminal 2. A shift register 3 is connected to this input terminal 1.2. A multiplier 4 is connected to the output terminal of the shift register 3.
is connected to the output terminal 7 via the adder 5 and the determiner 6. A subtracter 8 is connected between the input and output terminals of the determiner 6, and a coefficient modification section 9 is connected to the subtracter 8.

Next, the operation will be explained.

A signal from a transmission path (not shown) is modulated, and it is converted into an A/D
The received signal y (n) is converted into a discrete time signal by a converter and is input to the first input terminal 1. This received signal y (n) is input to the second input terminal 2. The coefficients are input to the shift register 3 and the coefficient update unit 9 at the timing of the timing signal CLK.

The shift register 3 shifts the received signal y (n>) in synchronization with the timing signal CLK, and provides the shifted output signal to the multiplication section 4.The multiplication section 4 uses the output signal of the shift register 3 and the coefficient update section. Coefficient Ci output from 9
(i = -N-, -M) and outputs the multiplication result to the adder 5. Here, both N and M are integers of 0 or more. Adder 5 adds all the multiplication results output from multiplier 4 and outputs the sum signal z (n) to determiner 6 and subtracter 8 .

The determiner 6 determines the received signal y (n>) and outputs the output signal x (n), which is a determination result of 11 or -1, to the output terminal 7 and the subtracter 8. Vessel 6
The addition signal z (n) is subtracted from the output signal x (n), and the error signal e (n) is output as a coefficient to the updating section 9. In the coefficient updating unit 9, the received signal y (n) and the error signal e (
n>, the coefficient C1 is updated so that the coefficient of the multiplier 4 follows the change in the transmission path, and is output to the multiplier 4.

The algorithm for updating coefficients in the coefficient updating unit 9 includes, for example, RLS (Recursive Lea
st 5QUare>There is an algorithm. This coefficient update algorithm at the time of day is expressed as the following equation.

c (L) = c (L-1>÷k (L) e (L
)k (L) =P (L-1)Yu(L)+1+17(
L) P (L~1〉Y (L)) 'P (L> =
P (L-1> -k (L) DanT(L)P(L-1) Dan (L)= (y (L+N), y (L+N-1,
..., y (L), -5., y (L + M)) ... (1) Uni, 1 represents transposition, and under par represents a vertical belt.

This coefficient updating operation in the coefficient updating unit 9 is normally performed by software of a data signal processor (hereinafter referred to as DSP) each time the received signal y (n>) is input from the first input terminal 1.

(Problems to be Solved by the Invention) However, the apparatus with the above configuration has the following problems.

Since the coefficient update algorithm in the coefficient update unit 9 requires many operations such as multiplication between matrices, it is executed by a DSP or the like that operates according to a program. In this coefficient updating section 9, the received signal y (n
) needs to be processed in real time. However, for example, the bit rate is several tens of d
Even if an attempt is made to perform equalization processing on a signal sent from a high-speed transmission line that is higher than ps, real-time processing cannot be performed in the coefficient update unit 9. Therefore, an adaptive equalizer that can be applied to a high-speed transmission line is realized. was difficult.

The present invention provides an adaptive equalizer that solves the problem of the prior art, which is that it is difficult to perform equalization processing in real time for high-speed transmission lines.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an adaptive equalizer having a coefficient updating unit that shifts a received signal and adaptively changes a coefficient to be multiplied by the shift result. A plurality of coefficient update sections are provided, and a switching means is provided for switching the outputs of the plurality of coefficient update sections in synchronization with the shift operation of the received signal and multiplying the switched output by the shift result. be.

(Function) According to the present invention, since the adaptive equalizer is formed into an ellipse as described above, when the received signal from the transmission path is input, the switching means synchronizes with the shifting operation of the received signal. The output of the coefficient update section is switched, and the switched output is multiplied by the shift result. Therefore, by adding the multiplication results and determining whether or not the addition result is larger than the reference signal, equalization processing can be performed on the received signal. In this way, even if the calculation speed of each coefficient update section is slow, each coefficient update section can perform coefficient update processing in a time-sharing manner, so that high-speed equalization processing of signals from a transmission path can be performed.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a configuration block diagram of a linear equalizer, which is one of the adaptive equalizers, showing an embodiment of the present invention.

In this figure, the thick lines connecting each block represent a data bus consisting of a plurality of signal lines, and the thin line represents one signal line.

This linear equalizer uses the received signal y(n
) and a second input terminal 12 to which an external timing signal CLK is input, and a shift register 13 is connected to the input terminals 11 and 12. The shift register 13 includes, for example, a plurality of delay flip-flops (hereinafter referred to as D-FF) 13.
A is connected in cascade, and each of those D-FF13
a has a function of performing a shift operation in synchronization with the timing signal CLK.

A multiplier 14 including a plurality of multipliers 14 a is connected to the output terminal of each stage of the shift register 13 , and each multiplier 14 a is connected to an adder 15 . Multiplication section 1
4 has a function of multiplying the output signal of the shift register 13 by a coefficient Ci, and an adder 15 has a function of adding the multiplication results and outputting a sum signal z (n).

An output terminal 17 is connected to the output terminal of the adder 15 via a determiner 16, and a subtracter 18 is further connected between the output terminal of the determiner 16. The determiner 16 is
It is determined whether the addition signal z (n>) output from the adder 15 is larger than the reference signal (0), and if it is larger, +1
, has a function of outputting an output signal x(n), which is a determination result of 1 when it is small, to the output terminal 17 and the subtracter 18. 'AxAlB12 It has a function of subtracting the addition signal z (n>) from the output signal x (n) and outputting the error signal e (n).

The output terminal of the subtracter 18 is connected to the first
and second coefficient updating sections 20-1 and 202 are connected, and the output terminals of the first and second coefficient updating sections 20-1 and 20-2 are connected to a selector section 21 consisting of a plurality of selectors 21a.
It is connected to the multiplier 14 via. The first and second coefficient updating units 20-1 and 20-2 are connected to the first input terminal 11.
Based on the received signal y(n) input from the input signal y(n) and the error signal e(n) input via the selector 19, the coefficient Ci
It has a function of updating (i − NzM) and outputting it to the selector unit 21. The selector unit 21 has a function of selecting one of the coefficients Ci from the first or second coefficient updating unit 20-1 or 20-2 and providing it to each multiplier 14a in the multiplication unit 14. There is.

Furthermore, a frequency divider 22 is connected to the second input terminal 12 . This frequency divider 22 divides the frequency of the timing signal CLK and outputs a selection signal S22.
1a, for example, D-FF
22a.

FIG. 3 is a circuit diagram showing an example of the internal configuration of the coefficient updating sections 20-1 and 20-2 in FIG. 1.

This coefficient updating unit 20-1. ．． 20-2 executes coefficient update calculation by software, and outputs the read signal RD, write signal WR and address signal AD at predetermined timing.
It has a DSP 30 that outputs O to AD7. This D
The SP30 is connected to the first address via eight address buses, for example.
and a second address decoder 31.33 are connected thereto, and first and second selectors 32.34 are connected via, for example, four data buses.

The first address decoder 31 has a function of decoding address signals ADO to AD7 based on a read signal RD from the DSP 30 and outputting a selection signal S31 to the first selector 32. The first selector 32 selects either the received signal y (n) or the error signal e (n) based on the selection signal S31, and transfers it to the data DO.
~D3 has the function of providing to the DSP 30 or the second selector 34. The second address decoder 33 is a circuit that decodes the address signals ADO to AD7 based on the write signal WR from the DSP 30 and outputs a selection signal 333 to the second selector 34. Further, the second selector 34 selects the data DO based on the selection signal 833.
~D3 and outputs the coefficient Ci to the selector section 21.

Next, the operation of the linear equalizer configured as above will be explained.

In FIG. 1, after a signal from a transmission path (not shown) is modulated, a received signal y, which is a discrete time signal, is sent to an A/D converter.
(n>) and then input to the first input terminal 11. The received signal y (n) input from the input terminal
The shift register 13 and the first and second coefficient updating units 2
0-1.20-2.

The shift register 13 receives the received signal y (n
) are sequentially shifted, and the result of the shift is applied to the multiplier 14.
Output to. The multiplier 14 uses the output signals of each stage of the shift register 13 and the coefficient C output from the selector 21.
t(i--N to M), and outputs the multiplication result to the adder 15. The adder 15 adds all the multiplication results multiplied by each multiplier 14a in the multiplier 14, and outputs the added signal z (n>) to the determiner 16 and the subtracter 18. The 15 addition signal Z(L) is
It is expressed by the following formula.

The determiner 16 determines whether the addition signal z (L> is greater than the reference signal (0) or not. If the addition signal z (L> and output to the subtracter 18. The subtracter 18 subtracts the addition signal z(L) from the output signal x(L) and outputs the error signal e(L) to the selector 19.

On the other hand, the timing signal CLK input from the second input terminal 12 is frequency-divided by the frequency divider 22, and the selection signal S22, which is the frequency division result, causes each selector 21a in the selector section 21 and the selector 19 to , respectively, are switched and controlled. The selector 19 switches and supplies the error signal e (L) output from the subtracter 18 to the first and second coefficient updating sections 20-1 and 20-2 based on the selection signal S22. For example, when the time is an odd number, the error signal e (L) is the first
When the time is an even number, the error signal e (L) is input to the second coefficient updating unit 20-1.
-2 is input.

The first and second coefficient updating units 20-1 and 20-2 update the received signal y(L) input from the first input terminal 11 and the error signal e(L) input from the selector 19. and execute the coefficient update algorithm alternately. for example,
When the time is an odd number, the first coefficient updating unit 20-1 updates the coefficient, and when the time is an even number, the second coefficient updating unit 20-2 updates the coefficient. This coefficient update operation is
This will be explained with reference to the figures.

In FIG. 3, the DSP 30 outputs a read signal RD and address signals ADO to A according to the coefficient update program.
D7 is output to the first address decoder 31. The first address decoder 31 decodes the address signals ADO to AD7 based on the read signal RD, and selects the selection signal S3.
1 is output to the first selector 32. Then, the first selector 32 selects the received signal y(L
) and send it to the DSP30 in the form of data DO~D3.
give to

Next, in the same manner as described above, the first selector 32 inputs the error signal e (L) in response to the selection signal S31, and provides it to the DSP 30 in the form of data DO to D3. DSP3
0, the coefficient C1 (i=-N to M) is calculated according to the algorithm shown in the following equation (3). This algorithm at the time of day is executed by the software of the DSP 30.

c (L>=c (L-2>+k (L)e (L)k
(L) = P (L-2) Dan (L) (1 + Dan 0 (L)
P (L-2>dan (L)) -1P (L> =P
(L-2> -k (L>T(L)P (L-2> ,,5LT(L)=CV(L+N),y(L+N)
-1).

..., y (L> , ..., y (L+M))・
(3) Next, the DSP 30 outputs the write signal WR and address signals ADO to AD7 to the second address decoder 33. The second address decoder 33 decodes the address signals ADO to AD7 based on the write signal WR, and outputs a selection signal 833 to the second selector 34. Then, the second selector 34 selects the data DO to D3 based on the selection signal 833, and outputs the coefficient Ci to the selector 21a in the selector section 31 shown in FIG. By repeating this operation, all the selectors 21 in the selector section 21
Output the coefficient Ci to a.

This coefficient update is performed by the first and second coefficient update units 2 every other time.
0-1.20-2 alternately. For example, when the time is an odd number, the first coefficient update unit 20-1 updates the coefficient, and when the time is an even number, the second coefficient update unit 20-1 updates the coefficient.
-2, the coefficient is updated.

Each selector 23a in the selector section 21 in FIG. For example, when the time is an odd number, the coefficient Ci from the first coefficient updating section 20-1 is output to the multiplication section 14,
When the time is an even number, the coefficient Ci from the second coefficient updating section 20-2 is output to the multiplication section 14. In this way, the first and second coefficient updating sections 20-1 and 20-2 are used in a time-sharing manner. The multiplier 14 multiplies the output of the shift register 13 by the coefficient Ci, the multiplication results are added in the adder 15, and the added signal z (L) is sent to the determiner 1.
6, and equalization processing is performed on the received signal y (n).

As described above, in this embodiment, the first and second coefficient updating sections 20-1 and 20-2 are provided, and they are connected to the selector section 21.
Since the coefficient updating operation is performed by switching in a time-sharing manner, the first and second coefficient updating units 20-1.2
Even if the coefficient update operation at 0-2 is slow, it is possible to equalize high-speed signals.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of such modifications include the following.

(i) First and second coefficient updating units 20-1.20-
By providing three or more selector units 21 and correspondingly increasing the number of selector units 21 to three or more, it is possible to perform faster time-division coefficient update calculations than in the above embodiment. Furthermore, the frequency divider 22 that outputs the selection signal S22 for switching the selector section 21 can also be configured with a timing generation circuit having another circuit configuration.

(ii) In the above embodiment, the coefficient updating operation in a linear equalizer has been described, but this coefficient updating operation can be easily applied to a decision feedback type equalizer, which is one of adaptive equalizers. For example, in order to change the linear equalizer in FIG. 1 to a decision feedback type equalizer, the shift register 13 is divided into a first and second shift register, and the output of the first shift register is transferred to 14 and an adder (not shown), which outputs the output of the first shift register and adder 1.
5, the addition result is given to the determiner 16 and the subtracter 18, and the output of the determiner 16 is shifted by the second shift register and input to the multiplier 14. Operates as a feedback equalizer.

(iii) In the above embodiment, all signals are treated as real signals, but when performing equalization on a four-phase phase modulation circuit (QPSK modulation signal), it is necessary to treat all signals as complex numbers. In this case, a complex equalizer capable of equalizing complex numbers can be easily constructed by changing each component circuit in Figure 1 to a circuit configuration that can process complex numbers consisting of a real part and an imaginary part. can.

(iv) The DSP 30 shown in FIG. 3 is a microcomputer with a built-in multiplier and the like to speed up product-sum calculations. Using SP software like this,
It is also possible to execute the entire equalizer process shown in FIG. 1, thereby reducing the amount of hardware (circuit scale).

(Effects of the Invention) As described in detail above, according to the present invention, a plurality of coefficient update sections are provided and the outputs thereof are switched by a switching means, so that the plurality of coefficient update sections can change the coefficients. Updates can be performed using time-sharing processing. Therefore, even if the calculations of each coefficient updating section are slow, high-speed signal equalization processing is possible, and the present invention can be applied to high-speed transmission lines.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of a linear equalizer, which is one of the adaptive equalizers, showing an embodiment of the present invention, and FIG. 2 is the configuration of a linear equalizer, which is one of the conventional adaptive equalizers. The block diagram in FIG. 3 is a circuit configuration diagram of the coefficient updating section in FIG. 1. 13... Shift register, 14... Multiplication section, 15.
・Adder, 16... Determiner, 18... Subtractor, 19
...Selector, 20-1.20-2...1st. Second
21... Selector unit, 22... Frequency divider, CLK... Timing signal, e (n>... Error signal, X(n)... Output signal, y (n )... Received signal.

Claims (1)

[Claims:] An adaptive equalizer having a coefficient updating section that shifts a received signal and adaptively changes a coefficient to be multiplied by the shift result, further comprising: a plurality of the coefficient updating sections; An adaptive equalizer, comprising: switching means for switching the outputs of the plurality of coefficient updating units in synchronization with the shift operation of the plurality of coefficient updating units, and for multiplying the switched output by the shift result.