JPH04260921A - Signal processor - Google Patents

Abstract

PURPOSE:To shorten a processing time by converting an arithmetic result of a processor into a prescribed format by an exclusive data converter, and writing the result of conversion a memory. CONSTITUTION:The processor 8 executes the calculation of data sent from the memory 20 or the external through a data bus 11 and obtains a result consisting of >=9 bits. In the case of storing the result of calculation in the memory 20, an address is outputted to the memory 20 through an address bus 10 and an address signal line 12 and data consisting of >=9 bits are sent to a data transforming device 19 as they are through the data bus 11. The device 19 executes rounding processing for rounding the data >=9 bits to 8-bit data and stores the 8-bit data in the memory 20 through a data signal line 13b. Since rounding is executed by the exclusive data converter without executing it by a processor 8, the load of the processor 8 can be reduced and the processing time can be shortened.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data processing between a processor and a memory, and is particularly widely used in image signal processing.

0002

2. Description of the Related Art Conventionally, there has been an image signal encoding device as shown in FIG. 4 as an example of this type of device often used. In the figure, 1 is a video input terminal, 2 is a subtracter that takes the difference between the current video input and locally decoded video data from one frame before, which will be described later, and 3 is a quantizer that quantizes the difference signal from subtracter 2. 4 is an inverse quantizer that inversely quantizes the signal from the quantizer 3; 5 is an adder that adds the locally decoded video data of one frame before and the output of the inverse quantizer 4; 6 is an A frame memory 7 is an output terminal to which the output of the adder 5 is added.

Next, the operation of FIG. 4 will be explained. Digital video input data is input from a video input terminal 1, and a subtracter 2 calculates the difference between the digital video data and the locally decoded video data of the previous frame, and outputs interframe video data. This interframe video data is quantized by a quantizer 3 and output from an output terminal 7. On the other hand, the quantized data from the quantizer 3 is dequantized by the dequantizer 4 and becomes inter-frame difference data. This difference data and the locally decoded data of the previous frame from the frame memory 6 are added by an adder 5, and the added output is stored in the frame memory 6. At this time, if the dequantized inter-frame difference data is an 8-bit digital signal and the local decoded data of the previous frame from the frame memory 6 is also an 8-bit digital signal, the output from the adder 5 is a maximum of 9 bits. Since it is a bit digital signal, it must be rounded to 8 bits when stored in the frame memory 6.

This device is used here, and conventionally,
An example of this type of device is the one shown in FIG. This diagram is from "MC68881 User's Manual" (published by Dempa Shimbunsha), Figure 1 from June 20, 1986.
7, in FIG. 3 8 is a processor, 9
is an 8-bit memory with the same data signal line for reading and writing, 10 is an address bus, 11 is a data bus, 1
2 is an address signal line, and 13 is a data signal line.

Next, a description will be given of the bit rounding operation performed by the processor in order to write data into memory. Here, a case will be described in which the number of bits for reading from and writing to memory is 8 bits. Assume that when the processor 8 performs an operation on data sent from memory or the outside through the data bus 11, the number of bits of the data becomes 9 bits or more. Therefore, a rounding process is performed to round the post-operation data of 9 bits or more to 8 bits, and the data is adjusted to 8 bits. When the work of aligning this data to 8 bits is completed, the address is output from the address bus 10 to the memory 9 through the address signal line 12. Then, the 8-bit post-operation data rounded to that address is sent out through the data bus 11 to the data signal line 1.
3 and is written to memory 9.

FIG. 5 shows the flow of the rounding operation of the processor 8 at this time. First, when the processor finishes the data operation, the resulting data X is -
It is determined whether it is less than 128, and if YES, step 1
5, X=-128, and if NO, it is determined in step 16 whether it is greater than 127; if YES, X=127 is determined in step 17, and if NO, it is passed as is and outputted in step 18. Because of this configuration, if X<-128, step 1
4. 3 steps of step 15 and step 18, X>1
27, step 14, step 16, step 1
7. 4 steps of step 18, -128≦X≦127
In this case, three steps of step 14, step 16, and step 18 are passed. Therefore, it will take at least three steps for any data X.

[0007]

[Problem to be Solved by the Invention] Conventional bit rounding was processed by a processor as described above.
The process took at least three steps. This invention was made to solve the above-mentioned problems, and its purpose is to shorten the processing time for bit rounding of data.

[0008]

[Means for Solving the Problems] A signal processing device according to the present invention uses a dedicated data converter that takes in data and converts the data format, instead of a processor, to perform bit rounding processing that has conventionally been performed by a processor. It is provided before writing to memory.

[0009]

[Operation] In the present invention, the operation result data enters a dedicated data converter, has its data format converted, and enters the memory.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, in which numerals 8, 10 to 12 are the same as the conventional device shown in FIG. 13a is a lead data signal line, 13b
19 is a data converter that performs bit rounding processing, and 20 is an 8-bit memory having separate unidirectional data signal lines for reading and writing. Next, the operation will be explained. The operation described here changes the number of bits of the processed data from the processor 8 to the required number of bits when the number of bits of the processed data from the processor is larger than the required number of bits (8 bits in this case). This is the operation that involves rounding down the bits to make them the same as the number (8 bits in this case) and writing them into memory.

When the processor 8 performs an operation on the data sent from the memory or the outside through the data bus 11, the number of bits of the data becomes 9 bits or more. Therefore, the post-operation data of 9 bits or more is outputted as an address from the address bus 10 to the memory 20 through the address signal line 12. On the other hand, post-operation data of 9 bits or more after the operation is outputted through the data bus 11, and passed through a data converter 19 that performs a rounding process of rounding the 9-bit or more post-operation data to 8 bits. After passing through the data converter 19, the data after the operation is rounded to 8 bits and is written into the memory at the address outputted by the processor earlier through the data signal line 13b. When the data is difficult to read, reading and writing are different, so the data signal line 13a is passed directly from the data bus 11 to the memory 2 without passing through the data converter 19.
I'm going to read 0.

In another embodiment, the memory may have bidirectional data signal lines. FIG. 2 is a block diagram showing another embodiment of the invention. 8 to 13 are the same as the conventional device shown in FIG. 19 is a data converter that performs bit rounding processing, and 21 is a one-way buffer.

Next, the operation will be explained, which is almost the same as the previous embodiment. The difference is that the memory 9 has the same bidirectional data signal line for reading and writing, unlike the previous embodiment, so when reading data, the data converter 1
9 is placed in a high impedance state, data passes through the data signal line 13 without passing through the data converter 19, passes through the one-way buffer 21, and is taken into the processor 8 via the data bus 11. Furthermore, when it is difficult to write data, since there is a one-way buffer 21, the data is written from the data bus 11 through the data converter 19 to the memory 9.

[0014] In this way, efficient processing can be achieved by performing processing that was previously performed using software using hardware. As an application example, in the block diagram of the image signal encoding device shown in FIG. 4, it is placed between the adder 5 and the frame memory 6, and the dequantized inter-frame difference data from the dequantizer 4 is 8 bits. When the local decoded data of the previous frame from the frame memory 6 is also 8 bits, the output from the adder 5 is 9 bits at most, so this device rounds it to 8 bits and stores it in the frame memory 6. In addition to bit rounding, other application examples include sign extension, truncation, and rounding up.

[0015]

[Effects of the Invention] As described above, according to the present invention, a dedicated data converter is used to perform bit rounding of operation result data, which was conventionally performed by a processor, so that the burden on the processor is lightened and the processing time can be shortened. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the invention.

FIG. 3 is a block diagram illustrating connections between a conventional processor and memory.

FIG. 4 is a block diagram of an image signal encoding device.

FIG. 5 is a flowchart of bit rounding processing by a conventional processor.

[Explanation of symbols]

8 Processor 9. Memory 11 Data bus 13 Data signal line 13b data signal line 19 Data converter

Claims (1)

[Claims] Claim 1: A signal processing device comprising a processor that processes data and a memory that stores data before and after processing, wherein when writing data from the processor to the memory, a A signal processing device characterized by using a data converter having a function of exclusively converting a data format from a processor into a predetermined format.