JPH04260911A - Control bus driver - Google Patents

Abstract

PURPOSE:To shorten the recovery time of a control bus from a low signal to a high signal and to improve the transmission capacity (throughput) of the control bus. CONSTITUTION:This control bus driver is constituted of a bus driver 104, an AND gate 108, a delay element 107, and a pull-up resistor 109, and when an input signal 105 is changed from a low signal to a high signal, a gate signal 106 is delayed for a short time by the element 107 to convert the low signal into the high signal. Thereby the bus driver 104 outputs the high signal for the short time only at the time of non-active conversion.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a control bus driver for driving a control bus inside a control device.

0002

2. Description of the Related Art The structure of a conventional bus circuit will be described with reference to FIG. 3, taking as an example a case where a control device is formed of each unit. As shown in the figure, the bus circuit of this configuration example is an example in which the control device is constituted by each unit, and the signal from each unit is received via one bus.

[0003] Here, the control device consists of a central control unit A and individual functional units B, C, and D, and each unit is connected by a control bus 101. Inside the central control unit A, a bus receiver 102 that receives signals from the control bus 101 and a pull-up resistor 103 for establishing the potential of the control bus 101 are arranged.

[0004] Furthermore, the inside of the individual functional units B and D is as follows.
The individual functional unit B is composed of an open collector bus driver 113 and a pull-up resistor 109, and the individual functional unit D is composed of a tri-state bus driver 104 and a pull-up resistor 1 for driving the control bus 101.
09. In addition, 110a, 110b,
110c and 110d indicate equivalent stray capacitances on the control bus 101, respectively.

The operation of the above configuration will be explained. Control bus 10 inputting to central control unit A
The signal No. 1 is in a format in which the bus drivers of individual functional units B and D are ORed, and the bus drivers of individual functional units B and D are
The bus drivers 104 and 113 are activated only when the control unit A sends a signal to the central control unit A, and the control bus 101 is brought to a "Low" potential (ie, a Low signal). Bus driver 1 is inactive when not sending a signal.
04 and 113 to the high impedance "Zero" state, the control bus is restored to the "High" potential by the pull-up resistors 103 and 109.

FIG. 4 shows the signal waveform of the control bus 101. As shown in the figure, the signals on the control bus 101 are transmitted to the bus driver 1.
04, 113 become active (Low signal), in other words, when the signal on the control bus 101 changes from a High signal to a Low signal, there is little time delay and the signal becomes Low immediately. However, when the bus drivers 104 and 113 become inactive (High signal), in other words, the signal on the control bus 101 becomes Low.
In the case of transition from the w signal to the High signal, the potential of the control bus 101 is recovered only by the pull-up resistor, so the equivalent stray capacitances 110a, 110b, 1 on the control bus 101
10c and 110d require recovery time (T2) in the figure.

[0007]

[Problems to be Solved by the Invention] Conventional control buses are configured as described above, and because the bus recovery time when the bus driver of an individual functional unit becomes inactive is long, it is difficult for the central control unit to control the control bus. The timing for receiving the state of the bus needs to have a long time interval in consideration of the bus recovery time, which poses a problem in that the transmission capacity (throughput) of the control bus decreases.

The present invention was made in order to solve the above-mentioned problems, and it shortens the recovery time of the control bus from a low signal to a high signal, and improves the transmission capacity of the control bus (
The objective is to obtain an improvement in throughput.

[0009]

[Means for Solving the Problems] A control bus driver according to the present invention brings a control bus inside a control device into an active state (Low signal) by outputting a Low signal.
In a control bus driver that is driven by a high signal, the control bus driver outputs a high signal following the low signal for a predetermined period of time after the control bus driver finishes outputting the low signal until the potential of the control bus recovers to the high signal. It is designed to output a signal.

0010

[Operation] The control bus driver according to the present invention takes the bus recovery time into account when receiving the control bus state by shortening the control bus "H" potential recovery time (recovery time to a high signal). no longer needed,
The transmission capacity (throughput) of the control bus can be improved. Further, in the above configuration, by using a tri-state bus driver IC containing a tri-state bus driver, an AND gate, and a delay element, the same improvement can be achieved without configuring a circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the interior of individual functional units B and D includes a tri-state bus driver 104 for driving a control bus 101 and an AND gate 108 for generating a gate signal 106 from an input signal 105 to the tri-state bus driver 104. , a delay element 107 and a pull-up resistor 109. Other parts are the same as those of the conventional example shown in FIG. 2, and therefore will be omitted.

The operation of the above configuration will be explained. Delay element 107 does not delay when input signal 105 transitions from a high signal to a low signal, and input signal 1
05 is delayed for a short time when it transitions from a Low signal to a High signal. Therefore, the gate signal 106 output from the AND gate 108 is a gate signal that is not delayed when the input signal 105 transitions from a high signal to a low signal.
When the input signal 105 transitions from a Low signal to a High signal, it becomes a gate signal whose transition from the Low signal to the High signal is delayed by an amount corresponding to the time delayed by the delay element 107 . As a result, the bus driver 104 outputs a high signal for a short time only when transitioning to inactive mode. In other words, the control bus 101 is forcibly restored.

FIG. 2 shows the signal waveform of the control bus 101. As shown in the figure, the control bus 101 goes high only for a short time (T1 in the figure) when the bus driver 104 goes inactive.
h signal is output, and the bus recovers to a high signal in a short time.

Although the embodiment is an example of a circuit configuration of a tri-state bus driver, similar effects can be obtained by configuring an equivalent circuit inside an open collector bus driver IC.

In addition, in FIG. 1, the control bus driver is constructed using the bus driver 104, the AND gate 108, the delay element 107, and the pull-up resistor 109, but the bus driver 104, the AND gate 108,
The circuit configuration can be further simplified by configuring the control bus driver using a tri-state bus driver IC incorporating the delay element 107 and a pull-up resistor.

[0016]

As described above, according to the present invention, it is possible to shorten the recovery of the control bus to a high signal (“H” potential recovery) when the bus driver becomes inactive, and the central control unit, etc. The transmission capacity (throughput) of the control bus can be shortened by reducing the reception time interval.
can be significantly improved.

Further, in the above-mentioned configuration, the circuit configuration is
By converting to C, the control bus driver can be made more compact. As a result, as a secondary effect,
To facilitate the production of devices and systems using this IC,
Moreover, it can be made compact.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing signal waveforms in one embodiment of the invention.

FIG. 3 is a circuit diagram of a conventional control bus driver.

FIG. 4 is an explanatory diagram showing signal waveforms of a conventional control bus driver.

[Explanation of symbols]

101 Control bus 10
2 Bus receiver 103 pull-up resistor
104 Tri-state bus driver 105 Input signal 10
6 Gate signal 107 Delay element
108 AND gate 109 Pull-up resistor 110a, 110b, 110c, 110d Equivalent stray capacitance of control bus A Central control unit B, C, D Individual functional unit

Claims (3)

[Claims] [Claim 1] By outputting a Low signal, the control bus inside the control device is brought into an active state (Low signal).
In a control bus driver that is driven by a high signal, the control bus driver outputs a high signal following the low signal for a predetermined period of time after the control bus driver finishes outputting the low signal until the potential of the control bus recovers to the high signal. A control bus driver characterized by outputting a signal. [Claim 2] A tri-state bus driver;
The control bus driver according to claim 1, comprising an AND gate, a delay element, and a pull-up resistor. [Claim 3] Tri-state bus driver, A
3. The control bus driver according to claim 1, comprising a tristate bus driver IC incorporating an ND gate and a delay element, and a pull-up resistor.