JPH0425969A - Compiling system which is made into definition arrangement vector under if sentence - Google Patents

Abstract

PURPOSE:To decide the definition reference relation of an arrangement element and to shorten the execution time of a program by fetching information on a condition and quotation to the arrangement where the elements are defined in order under an IF sentence. CONSTITUTION:A compiler 2 reads a source program, and analyzes a syntax and a vector processing part 22 generating a first intermediate text 24 is constituted by containing a syntax analysis means 221 which reads the first intermediate text 24 and analyzes the flow of control in the loop of the source program 1, a definition arrangement analysis means under IF sentence 222 analyzing the definition quotation state of arrangement where the elements are defined in order under the IF sentence in the loop, a data depending relation judgement means 223 judging whether there is contradicted data depending relation which is contradicted as against parallel execution in the loop or not and a vector text generation means 224 generating a second intermediate text for vector processing 25 for a part which is judged to be executed in parallel by the definition arrangement analysis means under IF sentence 222 and the data depending relation judgement means 223.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an IF statement definition array vectorization compilation method.

[Conventional technology]

In a vector processing processor that has vector instructions that perform operations on data arranged regularly in a storage area at once, it is generally possible to increase the proportion of the part of the target program that is executed by vector instructions. The more you do this, the more the program execution time can be reduced. Therefore, it is desirable for a compiler for such a vector processing processor to convert a given source program into a target program in a form that can be executed in parallel as much as possible.

By the way, conventional compilers for vector processing processors with vector instructions include a syntax analysis unit that reads a source program written in a high-level language, performs syntax analysis, and generates a first intermediate text, and a syntax analysis unit that reads a source program written in a high-level language and generates a first intermediate text. a vectorization processing unit that detects the loop structure of the vector and recognizes vectorizable portions and generates a second intermediate text for vector processing; and a code generation unit that generates and outputs a target program from the second intermediate text. ,
The main part was composed of

For example, in a conventional compiler of this type, when a source program as shown in FIG. Intermediate text (steps 31-3
4), the vectorization processing unit generates a second intermediate text (steps 41 and 42) as shown in the flowchart of FIG. 4 in which the first intermediate text is changed, and the code generation unit changes the second intermediate text. The target program was generated by vectorizing the part that can be read and executed in parallel.

However, with conventional compilers of this type, when a source program as shown in Figure 5 is given, the definition and reference to array C are not linear, so this range and the entire IF statement that includes this range are It was processed as a group of sentences that cannot be vectorized. For this reason, the vector processor is forced to sequentially execute the range in which the array C is defined and referenced, and the entire IF statement that includes this range, using scalar instructions.

[Problems to be Solved by the Invention] In the conventional compiler described above, for an array whose elements are defined in order under an IF statement in a DO loop,
- If there is a quotation outside the IF statement, the definition reference relationship cannot be determined, and generally the range in which the definition and reference to the array exists and the entire IF statement that includes this range cannot be vectorized, making parallel execution impossible. However, in a vector processing processor, there is a reference to an array element whose definition reference relationship cannot be determined, and it is executed using a scalar instruction, which has the disadvantage that the program execution time cannot be shortened.

An object of the present invention is to enable definition reference relationships of array elements to be determined, to be processed in a manner that can be executed in parallel through vectorization, and to
An object of the present invention is to provide a vectorization compilation method for an array defined under an IF statement that can shorten the execution time of a program in a vector processor.

[Means for Solving the Problems] The IF statement below definition array vectorization compilation method of the present invention includes a syntax analysis unit that reads a source program, performs syntax analysis, and generates a first intermediate text; A vectorization processing unit that detects loop structures in the source program, recognizes vectorizable parts, and generates second intermediate text for vector processing; and code that generates and outputs the target program from the second intermediate text. a generation unit, and the vectorization processing unit includes a structure analysis unit that reads the first intermediate text and analyzes the control flow in the loop of the source program, and extracts an array defined by an IF statement in the loop. , check the subscript of the retrieved array, check whether the shape of the subscript is linear under the IF statement, check the definitions and citations for the array that is considered linear, and arrange the citations after definition in the order of appearance. An IF statement definition array analysis means that examines the definition citation relationship using the subscript at the time of definition as a key for the array, assuming that there is a possibility of vectorization, and a data dependency relationship that contradicts parallel execution in the loop. and a data dependency relationship determination unit that processes the array as having no dependency relationship for the array for which the IF statement below definition array analysis unit determines that there is no problem with the definition citation relationship, and a data dependency relationship determination unit that processes the array as having no dependency relationship. 2. Vector text generation that generates a second intermediate text for vector processing for the parallel executable part and the IF statement definition array, and a second intermediate text necessary for vector processing the parallel executable part. Including means.

[Function] Based on the sequence searched by the IF text below definition sequence analysis means and the information collected, it is possible to clearly determine the part that was determined to be a definition reference relationship by the data dependency relationship determination means, based on the sequence searched by the IF text below definition sequence analysis means and the information collected. Parallel execution is possible by applying vector instructions when possible. Therefore, the execution time of the program in the vector processing processor can be shortened.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram of a compiler 2 to which an IF statement fixed array vectorization compilation method according to an embodiment of the present invention is applied.

This compiler 2 converts a source program 1 written in a given high-level language into a target program for a vector processing processor with hector instructions that perform operations on data arranged regularly in a storage area at once. It is a compiler that generates and outputs the source program 1, a syntactic analysis unit 21 that reads the source program 1, performs syntax analysis, and generates the first intermediate text 24, and detects a loop structure in the source program 1 from the first intermediate text 24. to recognize vectorizable parts and generate second intermediate text 25 for vector processing.
, and a code generation section 23 that generates and outputs the target program 3 from the second intermediate text 25.

The vectorization processing unit 22 includes a structure analysis unit 221 that reads the first intermediate text 24 and analyzes the flow of control in the loop of the source program 1, and a structure analysis unit 221 that reads the first intermediate text 24 and analyzes the flow of control in the loop of the source program 1, and a structure analysis unit 221 that reads the first intermediate text 24 and analyzes the flow of control in the loop of the source program 1, and IF to analyze definition citation status
A statement upper/lower definition array analysis unit 222, a data dependency relationship determination unit 223 that determines whether or not there is a data dependency relationship inconsistent with parallel execution in a loop, an IF statement upper/lower definition array analysis unit 222, and a data dependency relationship determination unit. Vector text generation means 22 that generates second intermediate text 25 for vector processing of the portion determined to be executable in parallel by 223;
4.

Referring to FIG. 9 (1), 1. The array table 910 created by the F upper and lower definition array analysis means 222 and referred to by the data dependency determination means 223 and the vector text generation means 224 has a pointer 911 to the next array daple.
, IF statement upper/lower definition array flag 912, definition reference skip flag 913, IF statement] Pointer 914 to definition array dataple 920, pointer 915 to subscript expression, number of elements 916, and array base 917. It is configured.

Also, referring to FIG. 9(2), the IF statement upper and lower definition array table 920 contains a pointer 921 to the next IF statement upper and lower definition array diple, and a pointer 92 to the array daple 910.
2, a pointer 923 of the working array table CW1,
Pointer 924 of work array table CW2, pointer 925 to mask array table, subscript information/initial value of each dimension 926, subscript information/increment value of each dimension 927
It is composed of...

Next, the operation of the IF statement upper/lower definition array vectorization compilation method of this embodiment configured as described above will be described.

Furthermore, here, given a source program 1 that quotes array elements as shown in FIG. As illustrated in FIG. 7, by using a working array, definition reference relationships can be analyzed, and processing can be performed as a loop group as shown in FIG. the result,
The second intermediate text 25 (steps 1101 to 1120), which can be vectorized, as shown in the flowchart of Figure S11
This will be explained with reference to an example of generating .

When the source program 1 is given and the compiler 2 is started, the syntax analysis unit 21 first reads the source program 1 and generates the first intermediate text 24 as shown in the flowchart of FIG.
(Steps 81 to 89).

Next, when the vectorization processing unit 22 inputs the first intermediate text 24, (1) First, the structure analysis means 221 is activated and performs the following processes ① to ②.

(2) The structure analysis means 221 first divides the first intermediate text 24 into blocks with branches as units.

■Next, divide the target loop into statement blocks.

(2) Next, the flow of control of the entire blockram is analyzed using the first intermediate text 24 to determine the relationship between each block.

■Finally, collect life/death information (expressing the population of the block and life/death status (definition or bow status) at the exit) for the arrays and variables referenced by definition in each block.

(2) Next, the IF statement upper and lower definition array analysis means 222 is activated, and the following processes 1 to 2 are performed.

■IF statement bottom definition array analysis means 222 First, the arrays defined above and below the IF statement in the loop are taken out.

■Next, place the subscript of the extracted array in the key, place the IF statement above and below, and check whether the value of the subscript is linear.

Check the order of definitions and citations for arrays that are considered linear in ■■, and only those that are cited after definition in the order of appearance may be vectorized, and the IF statement upper and lower definition array flag 912 of the array table 910 is turned on. do.

In ■■, for the IF statement upper and lower definition array flags 912 of the array table 910 that are on, check the definition/citation relationship using the subscript at the time of definition as the key, and for those that have no problems,
The definition reference skip flag 913 of the array table 910 is turned on. In addition, other information (pointers to IF statement upper and lower definition array tables in the array table, triat of subscript expression) is also set to Vti, and an IF statement definition array table 920 is also created at the same time.

In the case of the first intermediate text 24 shown in FIG. 8, C(J)
=A (1) +B (1) (step 86) is registered as the upper and lower definition array of the IF statement (see FIG. 10).

(3) Next, the data dependency determining means 223 is activated and determines whether there is a data dependency in the loop that is inconsistent with parallel execution. At this time, an array for which the definition reference skip flag 913 of the array table 910 is on is processed as having no dependency relationship.

In the case of the first intermediate text 24 in FIG. 8, since array C satisfies the condition in box 1, it is processed as having no dependency relationship.

(4) Subsequently, the vector degist generating means 224 is activated and performs the following processes ① to ②.

(1) The hector text generation means 224 first generates the second intermediate text 25 for setting the hector text length, which is necessary for vector processing of the parallel executable portion. In the case of the second intermediate text 25 shown in FIG. 11, the number of loop turns is set as the vector length vl = 100
(Steps 1102, .1113) are generated.

■Next, "52 intermediate text 25 for parallel processing is generated for the part that can be executed in parallel. In the case of the second intermediate text in FIG. 11, steps 1105 to 1107.1
114 is generated. At this time, work array 2 is used for the array defined under the IF statement (in the case of Figure 11, CWW is used instead of array C).6 In step 1105, the value of A(I) is less than 00. If it is larger, the first mask information M1 is turned on, and if it is equal or smaller, it is turned off. This is done for each element of the array. Step 11
06 is mask information M if the value of B(1) is greater than 00
Turn on the first of 2 and turn it off if they are equal or smaller. Do this for each element of the array. Step 1107 performs a logical product of the first mask information M1 and the first mask information M2, and sets the result as the first mask information M3.

Do this for each element. Steps 1108 and 1109 perform calculations only on the array element whose mask information M3 is on.

Here, setting mask information means determining conditions for each array element, and if the conditions are satisfied, the mask corresponding to the element is turned on, and if not, it is set to off. . When a vector operation is executed, if the mask is on, the operation is performed on the corresponding array element.

(2) Next, a second intermediate text 25 for vector processing is generated for the IF statement definition array. In the case of the second intermediate text in FIG. 11, processes (a) to (e) are performed.

(a) C assigning 1.0 to mask array CWM
WM (I)=1.0 (step], 1.03) is generated.

(b) Assign the first element in the loop of the IF statement definition array to the work array CWI CWl (I) = C (1
) (step 1104.) is generated.

(c) CWM that assigns OlO to the mask array CWM under the same conditions as the IF statement definition array (I) = 0
．． 0 (step 1108) is generated.

(d) Assignment process CWT of the IF statement definition array to the work array CW1, (I)=A(I)+B(I) (step 1109) is generated.

(e) Register the values to be set for each loop in the work array CW2 (steps 1111 to 1112)
.

Here, when the masking array satisfies the conditions for each array element, the array element with the same element number has a value of 0.0.
If the condition is not satisfied, the value is 1.0, and by applying this array to the temporary tidalization formula shown in FIG. 6, the elements that do not satisfy the condition can maintain their previous state. As a result, the fifth
As shown in the figure, the o-loop can be vectorized.

■ Generate second intermediate text for post-processing required to vector process the parallel executable portion. At this time,
For the IF statement definition array, steps 1115 to 1120 are generated in the case of the second intermediate text 25 in FIG. 11.

Vector text generation means 22 of vectorization processing section 22
When the process in step 4 is completed, the code generation unit 23 is started and the target program 3 is started based on the second intermediate text 25.
is generated.

As a result, the vector processor can use vector instructions to execute portions that were conventionally executed using scalar instructions because defined reference relationships could not be determined, and the program execution time is shortened.

[Effects of the Invention] As explained above, the present invention incorporates condition information and citation information for an array in which elements are defined in order under an IF statement, thereby improving definition reference relationships of array elements. This has the effect of enabling determination and shortening the program execution time in the vector processing processor.

[Brief explanation of the drawing]

Fig. 1 is a functional block diagram of a compiler to which the IF statement upper and lower definition array vectorization compilation method is applied according to an embodiment of the present invention, Fig. 2 is a diagram showing an example of the source program 1 in Fig. 1, and Fig. 3 is a flowchart showing an example of the first intermediate text illustrated in FIG. 2, FIG. 4 is a flowchart showing an example of the second intermediate text generated from the first intermediate text illustrated in FIG. 3, and FIG. FIG. 6 is a diagram showing another example of the source program 1 in FIG. 1. In the IF statement definition array vectorization compilation method of this embodiment, the compiler performs a 2. Diagram illustrating the format of the transformation source program performed at the time of intermediate text/creation, Part 7
The figure shows an example of the transformation performed by the compiler in the form of a source program when processing the source program illustrated in Figure 5 as being able to be executed in parallel. 1 is a flowchart showing an example of intermediate text. FIG. 9 is a diagram showing the structure of an array table 910 and an IF statement upper and lower definition array table 920 used in the IF statement upper and lower definition array vectorization compilation method of this embodiment. A diagram illustrating the contents of an array table and an IF statement upper and lower definition array table when the source program illustrated in FIG. 5 is processed using the IF statement upper and lower definition array vectorization compilation method of the embodiment, and FIG. 11 is illustrated in FIG. 8. 3 is a flowchart showing second intermediate text generated from the first intermediate text. 1... Source program, 2... Compiler, 3...
・Target program, 21 ・ 22 ・ 23 ・ 24 ・ 25 ・ 221 ・ 222 ・ 223 ・ 224 ・ 910 φ 911 ・ 912 ・ ・ 913 ・ ・ 914 ・ ・ 915 ・ ・ 916 ・ ・ 920 ・ ・ 921 ・ ・ ・parsing・Vectorization processing unit, ・Code generation unit, ・First intermediate text, ・Second intermediate text, ・Structure analysis means, ・IF statement upper and lower definition array analysis means, ・Data dependency relationship determination means, ・Vector text generation Means, ・Array table, ・Pointer to the next array table 910, ・IF statement F definition array flag, ・Definition reference skip flag, ・Pointer to IF statement upper and lower definition array tables 920, ・Subscript triat, ・Number of elements , 917... Array name, - IF statement upper and lower definition array table - Pointer to the next IF statement upper and lower definition array table 20, 922... Pointer to array table 910, 923
...Pointer to the working array table CWI, 924... Pointer to the working array table CW2, 925... Pointer to the masking array table CWM, 926... Subscript information/initial value of each dimension , 927...
Subscript information/incremental value of each dimension.

Claims (1)

[Claims] 1. Generates and outputs a target program from a given source program to a vector processing processor having vector instructions that perform operations on data regularly arranged in a storage area at once. A compiler that reads a source program, performs syntax analysis, and generates a first intermediate text; a syntax analysis unit that reads a source program, performs syntax analysis, and generates a first intermediate text; detects a loop structure in the source program from the first intermediate text and recognizes a vectorizable portion; It has a vectorization processing unit that generates a second intermediate text for vector processing, and a code generation unit that generates and outputs a target program from the second intermediate text, and the vectorization processing unit generates a first intermediate text. A structure analysis means that reads and analyzes the flow of control in a source program loop, extracts the array defined by the IF statement in the loop, examines the subscripts of the extracted array, and determines whether the subscript shape is linear under the IF statement. Check the order of definition and citation for arrays that are considered linear, and consider only the arrays that are cited after definition in the order of appearance as having the possibility of vectorization. The IF statement below definition array analysis means examines the definition citation relationship using the subscript as a key, and the IF statement below definition array analysis means determines whether there is a data dependency relationship that contradicts parallel execution in the loop, and the IF statement below definition array analysis means examines the definition citation relationship. For arrays that are found to have no problems, there is a data dependency determination means that processes them as having no dependencies, and for vector processing for second intermediate text for setting vector length, parallel executable parts, and arrays defined under IF statements. An IF statement definition array vectorization compilation method including a vector text generation means for generating second intermediate text for vector processing and a second intermediate text necessary for vector processing a parallel executable part.