JPH04259167A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To allow the generator to cope with various signal sources stably by extracting a change in the scanning frequency even when the scanning frequency is changed and implementing feedback loop control controlling the pulse width in response to the change. CONSTITUTION:A signal whose scanning frequency fH1 is fed to an input terminal 1 to be fed to a pulse width control section 2. The control section 2 uses a feedback loop to set a pulse width. The output whose pulse width is made constant is fed to a frequency - voltage conversion section 4, in which scanning frequency information is converted into voltage information. A conversion signal from the conversion section 4 is fed to a comparator 5, in which the signal is compared with a reference potential to obtain a change and the output is fed to a time constant setting section 3 to set a pulse width and a signal whose duty ratio is a prescribed percentage is outputted from the control section 2. When a synchronizing signal whose scanning frequency is fH2 is applied to the terminal 1, similarly the signal of the same pulse duty is outputted from the control section 2. Thus, the pulse signal with equal pulse duty ratio is obtained at all times.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a device for setting various timings of the screen phase and retrace period of color television receivers, etc., and relates to a synchronization signal generating device that is stable and compatible with various signal sources. be.

0002

[Prior Art] In general television receivers, the display area and position differ depending on the various signal sources, so the display screen is controlled by controlling the phases of various timing pulses. It was necessary to make optimal adjustments each time. Therefore, as a method that can be used with various signal sources, there is a method that discriminates the input signal and generates an optimal timing pulse based on this discrimination signal, and a method that is compatible with a multi-frequency display device with display screen adjustment data storage function that performs digital processing. A method has been proposed in Japanese Patent Publication No. 1-314291.

The conventional synchronous signal processing device will be explained below. FIG. 8 shows a block diagram of a multi-frequency compatible synchronization signal generator. The timing control circuits 53 and 59 are control means for setting various timings for two systems, and this switching is performed by a multiplexer 64 in response to a discrimination signal from a signal discriminator 66, and optimal timing data is output. The monostable multivibrators 52, 54, 58, and 60 each delay the synchronizing signal by half a period, and the total delay amount is one period. A control signal is inputted from the outside to the control terminals 55 and 61 to control a minute amount of delay. In addition, monostable multivibrators 57, 6
2, the pulse width is set, and the minute pulse width is controlled by external control signals from control terminals 57 and 63. The optimal timing data for each frequency mode from the two systems of timing control circuits 53 and 59 is supplied to a multiplexer 64, which is switched based on the discrimination signal from the signal discriminator 66, and the optimal timing data for each frequency mode is supplied to the output terminal 65. is output. As described above, synchronization signals corresponding to a plurality of types of synchronization signals are configured.

Another conventional synchronizing signal generator has been proposed, for example, in Japanese Patent Laid-Open No. 1-314291. FIG. 9 shows a block diagram of this conventional synchronization signal generator. The scanning frequency digital converter 68 shown in the figure can know the interval between pulse trains, counts the number of pulse trains with a binary counter, and uses the output as the address of the digital memory 69, thereby converting the pulse train from the input terminal 67. It is possible to separate data storage locations for each horizontal synchronization signal period. When adjusting the display screen to the optimum state with respect to the display signal at that time, the data switch 72 is turned to the DC side and the adjustment function 70 is varied while looking at the display screen. At this time, the data from the adjustment function is converted into a digital signal by the A/D conversion 71 and sent to the digital memory 69 and data switch 72. The data sent to the data switch 72 is D/A converted 73
is converted back into an analog signal and becomes an output signal. The display screen is adjusted based on the output signal. By closing the memory switch 75 when the adjustment to the optimum state is completed, the data of the adjustment function section at that time is stored in the digital memory 69.
is memorized. This allows it to accommodate many frequencies without increasing adjustment functions.

[0005]

[Problems to be Solved by the Invention] However, in the synchronizing signal generator configured as described above, adjustment is required for each scanning frequency mode, which takes time for adjustment, and the adjustment function for each scanning frequency mode is not sufficient. The problem is that the circuit size becomes very large because it requires a signal discrimination function to discriminate between the two. In addition, adjustments are required each time due to various changes in timing control system elements such as variations in temperature characteristics and the like.

The present invention takes this point into consideration, and by configuring a feedback control loop that automatically generates a constant timing signal in response to various scanning frequencies, various timings for setting the screen phase and retrace period can be adjusted. No adjustment of settings,
It is an object of the present invention to provide a synchronization signal generator for a color television receiver or the like that is stable and compatible with various signal sources.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides means for controlling the pulse width of an input synchronizing signal, conversion means for frequency-voltage conversion of the signal from the control means, Feedback control means is provided for controlling by feeding back the signal from the conversion means to the control.

[0008] Furthermore, the feedback control means is provided with a control means for controlling the pulse width using an external control signal.

[0009]

[Operation] The present invention extracts the amount of change in the scanning frequency even when the scanning frequency changes, and performs feedback loop control to control the pulse width according to this amount of change, thereby automatically changing the pulse duty ratio. Since equal pulse signals are obtained, it is possible to accommodate various scanning frequencies without the need for adjustment, and to perform stable and highly accurate timing control. Furthermore, since only one control system is required, the circuit scale can be significantly reduced. Furthermore, highly accurate timing control can be achieved by controlling the pulse width using an external control signal in the feedback control section.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a block diagram of a synchronizing signal generator according to a first embodiment of the present invention. In FIG. 1, 2 is a pulse width control unit for controlling the pulse width of the synchronization signal from input terminal 1, and 4 is a frequency-voltage unit for converting the output signal from pulse width control unit 2 from frequency to voltage information. A conversion unit 5 is a comparator for comparing the conversion signal from the frequency-voltage conversion unit 4 with a reference potential, and 3 changes the time constant of the pulse width control unit 2 based on the output from the comparator 5 to adjust the pulse width. This is a pulse width control section for controlling the pulse width. Hereinafter, the control system constituted by the above means will be referred to as the feedback control section 20.

In order to explain the operation of the synchronizing signal generator of this embodiment constructed as described above, the operation waveform diagrams shown in FIGS. 2(a), (b), (c) and (d) will be used below. A synchronizing signal having a scanning frequency fH1 shown in FIG. 2(a) is applied to the input terminal 1, and is supplied to the pulse width control section 2. In the pulse width control section 2, the pulse width is set by a feedback loop. The output from the pulse width control section 2 with a constant pulse width is supplied to a frequency-voltage conversion section 4, which converts scanning frequency information into voltage information. That is, frequency-voltage analysis is performed by keeping the pulse width constant and extracting changes in the average value of the output signal. The conversion signal from the frequency-voltage converter 4 is supplied to the comparator 5 and compared with the reference potential to determine the amount of change.The comparison output is fed back to the time constant setting unit 3 to set the pulse width, A signal with a pulse duty of 40% as shown in (b) is taken out from the pulse width control section 2 as an output signal.

Similarly, when a synchronizing signal of scanning frequency fH2 (fH1>fH2) shown in FIG. 2(c) is applied to the input terminal 1, the pulse width from the pulse width controller 2 is kept constant. The output is supplied to the frequency-voltage converter 4, which extracts the change in scanning frequency as voltage information.The comparator 5 compares this signal with a reference potential to determine the amount of change, and this comparison output is used to set the time constant. The signal is fed back to the pulse width controller 3 to set the pulse width, and a signal with a pulse duty of 40% as shown in FIG. 3(d) is taken out as an output signal from the pulse width controller 2.

The time constant of the pulse width of a monostable multivibrator etc. is determined by the time constant elements such as capacitor C and resistor R, and the power supply voltage. Therefore, by changing the above items, the pulse width can be set arbitrarily. In this embodiment, C for setting the time constant is fixed, and the resistance value and power supply voltage are controlled by the output from the comparator 5.

As described above, even when the scanning frequency changes, the amount of change in the scanning frequency is extracted and the pulse width is controlled according to this amount of change using feedback loop control, so the pulse duty ratio is always maintained. Equal pulse signals are obtained.

Next, the operating range of the feedback control loop will be explained in detail. The operating range is determined by the dynamic range for voltage comparison and the conversion accuracy of frequency-voltage conversion. The frequency-voltage converter 4 is composed of an integrating circuit such as a CR, and the lower the frequency, the more a conversion error occurs, which means that a stable DC potential cannot be obtained. Therefore, an error occurs in the comparator 5 that performs comparison with the reference potential and appears in the output signal as pulse jitter. Furthermore, since a feedback control loop is formed, there is a limit to the operating range, and when the operating range is exceeded, the pulse duty of the output signal changes. The operating range will be limited by the contents of the above two items.

Next, the stability of the pulse width will be explained in detail. Basically, feedback loop control is performed, so
Since no change in pulse width occurs due to changes in the monostable multivibrator for pulse width control, time constant, etc., stable pulse width control is possible. However, the stability of the reference potential of the comparison means is entirely attributable to the accuracy of this device.

As described above, according to this embodiment, even when the scanning frequency changes, the amount of change in the scanning frequency is extracted and the feedback loop control is performed to control the pulse width according to this amount of change. Since pulse signals with the same pulse duty ratio are automatically obtained, it is possible to correspond to various scanning frequencies without the need for adjustment, and to perform stable and highly accurate timing control. Furthermore, since only one control system is required, the circuit scale can be significantly reduced.

FIG. 3 shows a block diagram of a synchronization signal generator according to a second embodiment of the present invention. The difference from the configuration of the first embodiment is that the feedback control section controls the pulse width using an external control signal. In FIG. 3, 6 and 7 are feedback control units for generating a delay pulse of 1/2 period of the input synchronization signal, 8 is a feedback control unit for setting the pulse width, and 9 is the pulse width of the feedback control unit 7. An input terminal 10 receives a delay control signal for externally controlling the delay amount (delay amount), and an input terminal 10 receives a pulse width control signal for externally controlling the pulse width of the feedback control section 8 . Note that the feedback control section in the same figure has the same configuration as that in FIG. 1, so a description thereof will be omitted.

In order to explain the operation of the synchronizing signal generating device of this embodiment configured as above, the following will be explained.
The operation waveform diagrams in FIGS. 4(a), (b), (c), and (d) are used. A synchronizing signal having a scanning frequency shown in FIG. 4(a) is applied to the input terminal 1, and is supplied to the feedback control section 6. In the feedback control section 6, the pulse width is set by the same feedback loop as described above using the rising edge of the input synchronization signal shown in FIG.
The pulse width (1/2) of the horizontal scanning period shown in FIG.
/2H) signal is output. The signal from the feedback control section 6 shown in FIG. 2(b) is supplied to the feedback control section 7, and the pulse width is set by a feedback loop similar to the above using the falling edge as a trigger, and the horizontal scanning shown in FIG. 1/2 of the period
A signal with a pulse width (1/2H) is output. That is, the feedback control units 6 and 7 perform a delay of one horizontal scanning period (1H). The signal delayed by 1H is supplied to the feedback control unit 8, and the pulse width is set by the same feedback loop as above using the rising edge as a trigger, and as shown in FIG. A signal with a pulse width is output.

Further, a delay control signal is inputted to the feedback control section 7 from the input terminal 9, and this control signal causes the delay control signal as shown in FIG.
The amount of delay is controlled as shown by the arrow. Similarly, a pulse width control signal is inputted to the feedback control section 8 from the input terminal 10, and the pulse width is controlled by this control signal as shown by the arrow in FIG. 2(d). The pulse width can be controlled by the external control signal in the feedback control section by changing the reference potential of the comparator shown in FIG. 1, for example.

Next, a control method using an external control signal will be explained in detail. A DC potential for changing the reference potential is supplied to the input terminals 9 and 10, and an output obtained by adding the reference potential and the control signal is supplied to the reference potential terminal of the comparator. Therefore, the timing is finely adjusted by forcibly converting the reference potential. The delay and pulse width control signals supplied to the input terminals 9 and 10 are adjusted to high levels by reading out digitally stored optimum correction data from memory and correcting it using DC potential data obtained by converting the digital data into analog data. Accuracy can be corrected. Further stability and accuracy can be achieved by using analog feedback control for rough timing control and digital control for fine adjustment timing control.

As described above, by arbitrarily delaying the synchronizing signal and controlling the pulse width, the timing of the video signal and the synchronizing signal can be changed to control the screen phase, and the blanking period can be changed to display the display. It can be said that the system is suitable for a synchronization signal generator that controls a region. Further, it can be said that the system is very suitable for a multi-scan type display device that can handle various signal sources because it can be automatically controlled.

As described above, according to this embodiment, stable and highly accurate timing control can be performed by controlling the pulse width using an external control signal to the feedback control section.

FIG. 5 shows a block diagram of a synchronizing signal generator according to a third embodiment of the present invention. 1st~
The difference from the configuration of the second embodiment is that the response speed of the frequency-voltage converter is controlled by a synchronization signal. This eliminates pulse jitter when the synchronizing signal frequency is low, thereby expanding the operating range. In FIG. 5, 12 is the frequency - due to the frequency of the synchronization signal.
response speed control section for controlling the response speed of the voltage conversion section; 11;
is a frequency-voltage conversion section that converts frequency information of the output signal from the pulse width control section controlled by the response speed control section into voltage information. Note that the feedback control section in the same figure has the same configuration as that in FIG. 1, so a description thereof will be omitted.

In order to explain the operation of the synchronizing signal generating device of the embodiment configured as described above, FIG.
Use the operating waveform diagrams a), (b), (c), and (d). A synchronizing signal having a different frequency as shown in FIG. 6(a) or (c) is applied to the input terminal 1 and supplied to the pulse control section 2. The output whose pulse width is set by the pulse width controller 2 is supplied to the frequency-voltage converter 4, which converts scanning frequency information into voltage information. This output is shown in (b) or (d) of the same figure. At this time, when the frequency of the input synchronizing signal is high and the pulse interval is narrow as shown in FIG. 13(c), the converted voltage signal exhibits a constant value as shown in FIG. 4(d). However, if the frequency of the input synchronization signal is low and the pulse interval is wide as shown in (a) of the same figure,
The converted voltage signal changes as shown in FIG. 6(b), and a stable DC potential cannot be obtained. Therefore, an error occurs in the comparator 5 that performs comparison with the reference potential and appears in the output signal as pulse jitter. In order to reduce such errors, the third embodiment shown in FIG. 5 is provided with a response speed control section 12 for controlling the response speed in accordance with the synchronization signal frequency. . This response speed control section 12 converts the frequency of the input synchronization signal into a voltage, and creates a control signal for controlling the response speed based on this signal. The means for performing frequency-voltage conversion is composed of an integrating circuit such as a CR, and the converted voltage signal is used to create a control signal optimal for controlling the response speed of the frequency-voltage converter 11. , is supplied to the frequency-voltage converter 11. The frequency-voltage converter 11 is composed of, for example, an integrating circuit including an FET and a capacitor, and a voltage signal is supplied from the response speed controller 12 to the FET to change the response speed by changing the internal resistance. FIG. 7 will be used to explain this frequency-voltage converter in detail. Assume that the cutoff frequency of the integrating circuit of the frequency-voltage converter 11 is f2. At this time, since the response speed of the integrating circuit is fast, if the frequency of the input synchronizing signal is low, the level of the output signal of the frequency-voltage converter 11 changes rapidly, making it impossible to obtain a stable voltage. Therefore, by lowering the cut-off frequency of the integrating circuit and slowing down the response speed, the level of the converted signal hardly changes over time, and a stable output can be obtained.

In this way, when the input synchronizing signal frequency is high, the response speed of the frequency-voltage converter 11 is increased, and when it is low, the response speed is decreased, so that the frequency-voltage conversion is always performed at the optimal response speed, and the frequency-voltage conversion section 11 is A stable output signal can be obtained over a wide frequency range.

As described above, according to this embodiment, by changing the response speed of the frequency-voltage converter according to the frequency of the synchronization signal, stable and high precision can be achieved for synchronization signal input over a wide frequency range. timing control can be performed.

In the first to third embodiments, the input synchronization signal is a horizontal synchronization signal.
It goes without saying that a vertical synchronization signal or other synchronization signal may also be used.

Furthermore, in the first to third embodiments, the method of controlling the pulse width was explained by changing the resistance value of the time constant and the power supply voltage. Needless to say, it's a good thing.

In addition, in the first to third embodiments, a case has been described in which a constant timing signal is used to set the screen phase and retrace period of a television receiver in accordance with the scanning frequency. Needless to say, it may also be used as various timing signals, test signals, and reference signals for generating correction waveforms.

Furthermore, in the first embodiment, the frequency -
Although the voltage conversion section has been described with reference to the case where it integrates a signal with a constant pulse width using a CR or the like, it goes without saying that other conversion means may be used.

Furthermore, in the second embodiment, the pulse width is controlled by changing the reference potential of the comparator, but other control means may be used.

Furthermore, in a third embodiment, the frequency -
Although a case has been described in which the voltage conversion section uses an FET to change the response speed, it goes without saying that the response speed may be changed using a photocoupler, an active filter, or the like.

[0034] Furthermore, in a third embodiment, the frequency -
Although the case where the response speed of the voltage converter is changed has been described, it goes without saying that the response speed of the comparator may also be changed.

[0035]

[Effects of the Invention] As explained above, according to the present invention,
Even when the scanning frequency changes, a pulse signal with an equal pulse duty ratio can be automatically obtained by extracting the amount of change in the scanning frequency and performing feedback loop control to control the pulse width according to this amount of change. , it is possible to support a wide variety of scanning frequencies without adjustment, and to perform stable and highly accurate timing control. Furthermore, since signal discrimination is not required and only one control system is required, the circuit scale can be significantly reduced, which has a great practical effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronization signal generator device in a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the first embodiment of the present invention.

FIG. 3 is a block diagram of a synchronization signal generator device in a second embodiment of the present invention.

FIG. 4 is an operation waveform diagram of a second embodiment of the present invention.

FIG. 5 is a block diagram of a synchronization signal generator according to a third embodiment of the present invention.

FIG. 6 is an operation waveform diagram of a third embodiment of the present invention.

FIG. 7 shows frequency characteristics of a frequency-voltage converter according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a first conventional synchronization signal generator.

FIG. 9 is a block diagram of a second conventional synchronization signal generator.

[Explanation of symbols]

1 Sync signal input terminal 2 Pulse width control section 3 Time constant setting section 4,11 Frequency-voltage conversion section 5 Comparator 12 Response speed control section

Claims (3)

[Claims] 1. A control means for controlling the pulse width of an input synchronization signal, a conversion means for frequency-to-voltage conversion of a signal from the control means, and a signal from the conversion means for feeding back to the control means. 1. A synchronizing signal generating device comprising feedback control means for controlling the synchronizing signal. 2. The synchronizing signal generating device according to claim 1, wherein the feedback control means controls the pulse width using an external control signal. 3. A control means for controlling the pulse width of an input synchronization signal, a conversion means for frequency-voltage conversion of the signal from the control means, and a signal from the conversion means for feeding back to the control means. 1. A synchronization signal generating device comprising: feedback control means for controlling the input synchronization signal; and response speed control means for controlling the response speed of the feedback control means in accordance with the frequency of an input synchronization signal.