JPH04257943A - Information processor - Google Patents

Abstract

PURPOSE:To design a hardware ignoring access time by composing the information processor of a semiconductor memory cell equipped with a terminal, which shows that data is valid when reading the data, and a microprocessor. CONSTITUTION:An address decoder 4 inputs address information outputted by a microprocessor 1. Then, semiconductor memory cells 2 and 3 are selected by activating any one of signal lines connected to the CE (chip enable) terminals of the respective semiconductor memory cells 2 and 3. When the CE terminals are activated, the semiconductor memory cells 2 and 3 input the address information outputted by the microprocessor 1 and outputs the data of the relevant inside cell to a data bus 20. A VD terminal is provided, a VD signal is wired- ORed connected to the READY terminal of the microprocessor 1, and connected to a constant potential through a resistor 22. The VD terminal is activated when the data is correctly outputted in the case of reading the data.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to information processing devices, and more particularly to an interface circuit between a microprocessor and a semiconductor memory.

0002

2. Description of the Related Art A microprocessor-semiconductor memory interface circuit in a conventional information processing device, as shown in FIG. It consists of a weight generation circuit 104 and a decoder 105 that generates chip enables for the memories 102-103.

Next, a specific example in which the microprocessor 101 reads data from the memories 102 to 103 will be described.

[0004] Microprocessor 101 outputs address information for accessing address bus 21 . The decoder 105 inputs part of this address information and selects the memories 102 to 103 based on the decoding result. The selected memory receives address information from the microprocessor 101 and outputs data at the corresponding address within the memory to the data bus 21. When the microprocessor 101 takes in the data on the data bus 21, the operation of reading data from the memories 102 to 103 is completed.

At this time, the timing at which the microprocessor 101 takes in the data is predetermined, but if a memory whose access time does not meet that timing is used, the wait generation circuit 104
will be designed.

[0006] Generally, the memory used in an information processing device is ROM, SPAM, DRAM, etc., and the access time often varies.

Therefore, a hardware designer should design the wait generation circuit 104 so that the decoder 105 detects which access time the memory is accessed and generates the number of waits corresponding to the access time. become.

[0008]

SUMMARY OF THE INVENTION In such a conventional information processing device, it is difficult to use memories with various access times and to satisfy the basic access time required by the microprocessor 101. The weight generation circuit 104 was inevitably required.

[0009] Furthermore, the circuit designer has the trouble of having to fully consider the access time of various memories, the delay time due to buffers, etc. when designing the circuit.

[0010] The purpose of the present invention is to solve the above problems,
To provide an information processing device that does not require a weight generation circuit and can be easily designed.

[0011]

Means for Solving the Problems An information processing apparatus according to the present invention is configured to include at least a microprocessor, a semiconductor memory, and a decoder, in which the microprocessor performs a data read cycle in a first The semiconductor memory has a function of stretching with a signal input to a terminal, and the semiconductor memory has a second terminal that is activated when the data is correctly output when reading the data;
A second terminal of the semiconductor memory is connected to a first terminal of the microprocessor.

0012

Embodiment FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

In FIG. 1, the information processing apparatus of this embodiment includes a microprocessor 1, a plurality of semiconductor memory elements 2 and 3, and semiconductor memory elements 2 and 3.
and an address decoder 4 for selecting.

The address decoder 4 inputs the address information output from the microprocessor 1, activates one of the signal lines connected to the CE (chip enable) terminal of each semiconductor memory element 2, 3, and activates the semiconductor memory element. Select element.

When the CE terminal is activated, the semiconductor memory elements 2 and 3 receive the address information output from the microprocessor 1, and transfer the data of the corresponding internal cells to the data bus 2.
Output to 0. Further, the present semiconductor memory elements 2 and 3 are specially equipped with a VD terminal, which is connected to the READY terminal of the microprocessor 1 by wire-ORing the VD signal, and is also connected to a constant potential via a resistor 22. .

The VD terminals of the present semiconductor memory elements 2 and 3 are connected to each other when data is correctly output when reading data.
This is the terminal to be activated.

Note that the CE terminal, VD terminal, and READY terminal all operate with negative logic signals.

[0018]

As described above, the present invention provides an information processing device that includes a semiconductor memory element and a microprocessor, which has a terminal that indicates that data is valid when reading data. This enables hardware design that ignores element access time, eliminates the need for a wait generation circuit, and has the effect of further improving performance with fewer components.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an information processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional interface circuit.

[Explanation of symbols]

1,101 Microprocessor 2,3
Semiconductor memory elements 102 and 103 having VD terminals
Semiconductor memory element 1,105 without VD terminal
Address decoder 104 Wait generation circuit

Claims (1)

[Claims] 1. An information processing device comprising a microprocessor, a semiconductor memory, and a decoder, wherein the microprocessor performs a data read cycle in a first
The semiconductor memory has a second terminal that is activated when the data is correctly output when reading the data, and the semiconductor memory has a second terminal that is activated when the data is correctly output when reading the data, and the semiconductor memory has a second terminal that is activated when the data is correctly output when reading the data; An information processing device characterized in that a second terminal of the semiconductor memory is connected to.