JPH04257266A - Electrostatic induction thyristor - Google Patents

Abstract

PURPOSE:To provide an SI thyristor which has an excellent turn-off characteristic, a large current-carrying capacity and a great withstand strength by increasing a factor of utilization of a cathode area of the SI thyristor which employes a cathode shorted structure. CONSTITUTION:P<+> gate layers 2, 2' of an SI thyristor are of buried structure. On the cathode-side surface of the SI thyristor, P<+> shorted layers 3 are formed above the gate layers 2, 2'. The other region of the cathode-side surface than the region where the layers 3 are formed is an N<+> cathode layer 1. A region which will be a channel on the cathode-side surface is the N<+> cathode layer 1 and therefore this device has such a structure that a coefficient of effective utilization of area may be increased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SI thyristor (static induction thyristor), and particularly to its structure.

0002

[Prior Art] Conventionally, methods for increasing the switching speed of power semiconductors include methods such as diffusing heavy metals such as gold, shortening the lifetime of the base region by irradiating electron beams or protons, and short-circuiting anode structures. was used.

[0003] In particular, with regard to SI thyristors, it is possible to short-circuit the cathodes due to their structure to improve the switching speed, and such SI thyristors have a double short-circuit structure that combines an anode short-circuit structure and a cathode short-circuit structure. SI thyristors are known.

FIG. 2 is a cross-sectional view of an example of the above-mentioned SI thyristor. On the cathode side of this SI thyristor, an N+ cathode layer 1 and a P+ gate layer 2 are formed on the main surface of an N- base layer 4, and an N+ gate layer 2 is formed on the main surface of an N- base layer 4. - It has a structure in which a P+ shorting layer 3 is formed separated from the P+ gate layer 2 by a base layer 4, and the N+ cathode layer 1 and the P+ shorting layer are short-circuited by a metal electrode 7a.

[0005] Also, on the other main surface of the N- base layer 4, a P+ anode layer 5 is formed as in the usual anode short-circuit structure.
and N+ shorting layer 6 are formed adjacent to each other at a constant ratio, and are connected by a metal electrode 7c. Furthermore, in the figure, 7b represents a gate electrode, and 8 represents an insulating layer.

[0006] In this text, P and N indicate a semiconductor containing a P-type impurity and a semiconductor containing an N-type impurity, respectively, and the subscripts + and - indicate high and low impurity contents, respectively.

In the SI thyristor with the above configuration, N
- The holes and electrons injected into the base layer 4 are transferred to the P+ shorting layer 3 on the cathode side and the N+ shorting layer 6 on the anode side, respectively.
Since it is discharged to the outside, high-speed turn-off can be realized.

[0008] Furthermore, in an SI thyristor, the main junction is formed between the P+ gate region and the N- base, so in order to increase the withstand voltage, it is necessary to form the P+ gate region deeply, and the withstand voltage is generally about 1000V. In the SI thyristor, the P+ gate is 10 to 20
It is formed in the order of μm.

[0009]

However, when forming a P+ gate layer in an SI thyristor as described above, the P+ gate region is formed to a depth of about 0.7 to 0.8 in the lateral direction. Therefore, if the P+ gate layer of the SI thyristor is formed deeply, its surface area also increases proportionally. Therefore, in the prior art, when the withstand voltage of the SI thyristor is increased, the area ratio of the N+ cathode layer to the P+ gate layer becomes smaller, resulting in a problem that the cathode area utilization rate decreases.

Furthermore, as shown in FIG. 2, in the SI thyristor using the cathode short-circuit structure, it is necessary to provide a P+ short-circuit layer on the surface in addition to the P+ gate layer 2, which further reduces the cathode area utilization rate. . Therefore, there was a problem in that the current capacity had to be reduced.

The present invention has been made based on the above background, and an object thereof is to provide an SI thyristor with a cathode short-circuit structure that has a large current capacity and high withstand voltage by improving the cathode area utilization rate. do.

0012

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an electrostatic induction thyristor having an N+ cathode layer and a P+ shorting layer on one main surface of the N-base layer. The P+ gate layer is divided into a plurality of parts and arranged in a direction parallel to the main surface and embedded in the P+ gate layer, and the N+ cathode layer is formed at a position facing the channel region between the P+ gate layers, and the P+ short-circuit The layer is characterized in that it is formed at a position facing at least a portion of the divided P+ gate layer.

[0013]

[Function] When an SI thyristor has a cathode short-circuit structure, the size of the N+ cathode layer region on the main surface on the cathode side, that is, the area utilization rate, is important. If this ratio is low, the current capacity decreases, etc., resulting in the performance of the SI thyristor. decreases.

The location where the N+ cathode layer is formed is also important, and the N+ cathode layer is formed on the main current path of the SI thyristor.
If no cathode layer is formed, the actual area utilization rate will decrease.

Generally, in an SI thyristor, P+
A region formed between gate layers (channel region), and S
The regions facing the channel regions on both main surfaces of the I thyristor serve as the main current path, but in the present invention, the region facing the channel region on the anode side main surface, which is the main current path, is the N+ cathode layer. This increases the effective area utilization rate.

[0016]

Embodiment In this embodiment, an SI thyristor with a buried gate type double short circuit structure is used, and a cross-sectional view thereof is shown in FIG. In this figure, parts having the same names or functions as those in FIG. 2 are given the same symbols as in FIG. 2, and their explanations are omitted.

In the present invention, the conventional P+ gate layer 2 shown in FIG. 2 is buried in the N- base layer 4 instead of in the main surface on the cathode side to form a P+ gate layer 2'. It is characterized by the arrangement of the N+ cathode layer and the P+ shorting layer facing each other.

That is, the P+ gate layer 2' is divided into a plurality of parts and arranged in the N- base layer 4 in a direction parallel to the main surface on the cathode side. The N+ cathode 1 is formed on the main surface of the cathode side facing the channel region formed in the adjacent P+ gate layers 2', and the P+ shorting layer 3 is formed on the main surface of the P+ gate layer 2'.
P+ gate layer 2 is formed on the main surface on the cathode side opposite to
A region made of a P-type semiconductor is formed in at least a portion of the position opposite to '. The N+ cathode layer 1 and the P+ shorting layer 3 are short-circuited by a metal electrode 7a.

Further, the main surface of the N- base layer 4 on the anode side is formed with an N+ shorting layer 6 formed in a portion facing the channel region, and a P+ anode layer 5 formed in the other portion, These N+ shorting layer 6 and P+ anode layer 5 are short-circuited by a metal electrode 7c, similar to the main surface on the cathode side.

In the above-mentioned SI thyristor, the N+ cathode layer 1 is formed in the portion of the main surface on the cathode side, which is the main current path, facing the channel region, so that the effective area utilization rate is increased.

Furthermore, since this embodiment adopts the double short-circuit structure as described above, the holes and electrons injected into the N- base layer 4 are transferred to the P+ short-circuit layer 3 on the cathode side and the P+ short-circuit layer 3 on the anode side, respectively. It is discharged to the outside by the N+ shorting layer 6. Therefore, high-speed turn-off can be realized, and as mentioned above, the effective area utilization rate of the N+ cathode layer 1 is high.

The cathode shorting rate can be easily changed by forming the N+ cathode layer 1 larger or smaller than in the above embodiment.

In addition, although an anode short-circuit structure was also used in this embodiment, the structure of the main surface on the anode side of the N- base layer was changed to a structure in which a P+ anode layer was formed on the entire surface, and a structure in which a P+ anode layer and an N- base layer were formed. The effective area utilization rate of the N+ cathode layer 1 can also be increased by a configuration in which an N+ buffer layer is provided between the N+ cathode layer 1 and the N+ buffer layer.

Furthermore, even if the P-type semiconductor and the N-type semiconductor are replaced in the above embodiment, an SI thyristor with a high effective area utilization rate can be obtained.

[0025]

Effects of the Invention In the present invention, in an SI thyristor using a cathode short circuit structure, the P+ gate layer is a buried structure and the P+ short circuit layer is a P+ gate layer on the main surface on the cathode side.
It is formed in a region facing the gate layer. Therefore, N
Since the positive cathode layer is formed on the main current path, the effective area utilization rate is improved, and the current capacity can be increased.

Therefore, according to the present invention, it is possible to obtain an SI thyristor which has excellent turn-off characteristics due to the cathode short-circuit structure, has a high breakdown voltage, and has a large current capacity.

[Brief explanation of the drawing]

[Fig. 1] Cross-sectional view of one embodiment of the present invention

[Fig. 2] An explanatory diagram of an SI thyristor with a double short circuit structure according to the prior art

[Explanation of symbols]

1 N+ cathode layer 2, 2' P+ gate layer 3 P+ shorting layer 4 N-base layer 5　P+Anode layer 6 N+ shorting layer

Claims (1)

[Claims] 1. A static induction thyristor having an N+ cathode layer and a P+ shorting layer on one main surface of an N- base layer, in which a P+ gate layer is divided into a plurality of parts in the N- base layer. The N+ cathode layer is arranged and buried in a direction parallel to the plane, and the N+ cathode layer is formed at a position facing the channel region between the P+ gate layers, and the P+ shorting layer is buried in at least one of the divided P+ gate layers. An electrostatic induction thyristor characterized by being formed at a position facing the part.