JPH04257258A - Mos static memory - Google Patents

Abstract

PURPOSE:To reduce the size of a memory cell. CONSTITUTION:A diffusion layer for a storage node part (n<+> type diffusion layer 6 which is a drain region of a transfer transistor T1, as cited as an example in the Figure) and a gate electrode (polycrystalline silicon layer 3 which is a gate electrode of a driving transistor Q1, as cited as an example in the Figure) are connected through a crystalline silicon layer 7 which is formed by the selection growth method. A source region of the driving transistor (n<+> type diffusion layer 6) and a ground potential interconnection 9 are also connected through the crystalline silicon layer 7 which is formed by the selection growth method.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type static memory, and more particularly to the structure of its memory cell.

0002

2. Description of the Related Art FIG. 4 is a circuit diagram of a memory cell of a resistive load type MOS static memory. In the same figure, T1 and T2 are transfer transistors, Q1
, Q2 are drive transistors, R1, R2 are load resistances, D, D* (* mark is a substitute for an upper line. In other words, a signal line with * is a signal with the opposite phase of the signal transmitted to the signal line without *) ) is a pair of digit lines.

FIG. 5 is a plan view of a conventional static memory that integrates the circuit shown in FIG.
c) are cross-sectional views taken along line AA, line BB, and line CC in FIG. 5, respectively. However, the load resistance and digit line are omitted in FIGS. 5 and 6.

In FIG. 5, 3 (dotted chain line) is a polycrystalline silicon layer constituting the gate electrode, 6 (solid line) is an n+ type diffusion layer, and 9 (double-dotted line) is composed of polycrystalline silicon, silicide, etc. A ground potential wiring 11 is a contact hole 12 formed in the SiO2 film to connect the n+ type diffusion layer 6 and the polycrystalline silicon layer 3, which are storage node portions.
is made of Si to connect the diffusion layer 6 and the ground potential wiring 9.
This is a contact hole formed in the O2 film.

In FIGS. 6(a) and 6(b), 1 is a p-well, 2 is an SiO2 film serving as a gate insulating film, 2a is an SiO2 film serving as a field insulating film, and 6 is an n+ well formed by ion implantation. The type diffusion layer 6a is an n+ type diffusion layer formed by impurity diffusion from the polycrystalline silicon layer 3. In the conventional example, as shown in FIGS. 6A and 6B, the connection between the storage node portion and the gate electrode was achieved by impurity diffusion from the gate electrode (polycrystalline silicon layer 3).

The connection between the diffusion layer 6 and the ground potential wiring 9 is made through a contact hole formed in the interlayer insulating film 8 on the polycrystalline silicon layer 3, as shown in FIG. 6(c). .

[0007]

[Problems to be Solved by the Invention] In the conventional static memory, the connection between the diffusion layer of the storage node portion and the gate electrode was made through the diffusion layer formed by the diffusion of impurities in the gate electrode. was there.

[0008] Since it is necessary to secure a space adjacent to the ion-implanted diffusion layer on the semiconductor substrate for the polycrystalline silicon layer to contact, the conventional example wastes space.

■ Diffusion layer made by different processes [
6 and 6a in FIGS. 6A and 6B] have a lower breakdown voltage than the diffusion layers formed by ion implantation, so it was necessary to widen the interval between the diffusion layers in order to obtain the necessary breakdown voltage.

FIG. 7 is a characteristic diagram for explaining this point. The figure shows the relationship between the distance between two adjacent diffusion layers and the voltage applied between the two diffusion layers when a current of 1 μA flows between the diffusion layers. The white circles indicate the normal characteristics between the diffusion layers. Also, the black circles are (normal diffusion layer) and (diffusion layer due to impurity diffusion from the gate electrode + normal diffusion layer)
It shows the characteristics between each.

As shown in the figure, in the conventional example, in order to ensure the same level of breakdown voltage as between normal diffusion layers,
It was necessary to provide an additional spacing of about 0.2 μm compared to the usual spacing between the diffusion layers.

■ Diffusion layer made by different processes [
6 and 6a in FIGS. 6A and 6B] have a larger leakage current to the substrate (in this case, the p-well) than a normal diffusion layer.

Furthermore, in the conventional static memory, the contact hole for connecting the diffusion layer and the ground potential wiring is
As shown in FIG. 6C, the hole is drilled to a depth equal to the thickness of the gate electrode plus the thickness of the interlayer insulating film, but such a contact structure causes the following problems.

[0014] In order to drill such a deep hole and to grow polycrystalline silicon or the like in this contact hole with high reliability, a certain amount of space must be secured for the contact hole. That is, (
In c), it was not possible to bring the two polycrystalline silicon layers 3 very close together.

[0015] Due to the above-mentioned reasons, the distance between the gate electrode and the source contact increases, which increases the source resistance, and the source resistance tends to become unbalanced, which may cause unstable operation.

As mentioned in (1), (2), and (2) above, in the conventional example, the memory cell size had to be large, which was a major obstacle to miniaturization and high integration.

[0017]

In the MOS type static memory of the present invention, the storage node diffusion layer and the gate electrode are connected through a single crystal silicon layer formed by a selective growth method.

Furthermore, in the MOS type static memory of the present invention, the source diffusion layer of the drive transistor and the ground potential wiring are connected through a single crystal silicon layer formed by a selective growth method.

[0019]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. (a) of FIG. 1 is a plan view showing the connecting portion between the drain diffusion layer of the first transfer transistor T1 and the gate electrode of the first drive transistor Q1, and (b) of FIG. FIG. Further, FIG. 1C is a cross-sectional view of a connection portion between a common source region of a first drive transistor and an adjacent drive transistor and a ground potential wiring. That is, (b) in FIG. 1 is similar to (b) in FIG.
FIG. 1(c) is a sectional view showing a portion corresponding to FIG. 6(c).

In FIG. 1, 1 is a p-well, 2 is a SiO2 film which is a gate insulating film, 3 is a polycrystalline silicon layer forming a gate electrode, 4 is a SiO2 film formed on the surface of the polycrystalline silicon layer 3, 6 is an n+ type diffusion layer formed by ion implantation, 7 is a single crystal silicon layer formed by selective growth, 8 is an interlayer insulating film, and 9 is a ground potential wiring made of polycrystalline silicon, silicide, or the like.

Next, a method for manufacturing the portion (b) in FIG. 1 will be described with reference to FIG. 2. First, as shown in FIG. 2(a), a field insulating film and a gate insulating film (SiO2 film 2) are formed on the p-well 1 by a normal process, and a gate electrode (a polycrystalline silicon layer) is formed on the p-well 1. 3), an n+ type diffusion layer 6 is formed by ion-implanting an n type dopant. At this time, the MOS transistor is
If a D structure is used, a process for that purpose is added.

Next, as shown in FIG. 2(b), the LPC
SiO2 is formed around the polycrystalline silicon film 3 using the VD method.
Grow film 4. Subsequently, the portion of the SiO2 film other than the removed portion is covered with a photoresist 5 [FIG. 2(c)], and the portion of the SiO2 film not covered with the photoresist 5 is removed by a plasma etching method [FIG. 2(c)]. d)]
.

Next, SiH2 Cl2 is used as a growth gas.
-H2 -HCl as doping gas, PH3
using S at about 900°C and a pressure of 30 to 80 Torr.
Silicon is selectively grown in the area where the iO2 film has been removed. The state after this selective growth step is shown in FIG. 1(b). Note that the single crystal silicon layer 7 in FIG. 1(c) is also formed at the same time by the same process.

As shown in FIGS. 1(a) and 1(b),
In this embodiment, since the diffusion layer (6a) formed by impurity diffusion from the gate electrode is not used to connect the n+ type diffusion layer 6 and the gate electrode, space for this is saved.

In addition, since the diffusion layer is formed only by ion implantation, leakage current is reduced, and
Since the breakdown voltage between the diffusion layers is improved, the margin for the distance between the diffusion layers can be reduced. Note that the situation of this improvement in breakdown voltage is shown by white triangles in the characteristic diagram of FIG.

Furthermore, since the contact hole for connecting the diffusion layer 6 and the ground potential wiring 9 is formed in a thin SiO2 film, the hole can be easily formed even in a narrow place, and can be selectively formed. Since the growth method allows for reliable connections, the spacing between the gates of adjacent drive transistors can be made narrower than in the past.

FIG. 3 is a plan view showing another embodiment of the present invention. In this embodiment, the n+ type diffusion layer 6 and the gate electrode (
3) is the same as in the previous embodiment, but the single crystal silicon layer 7 for connecting the n+ type diffusion layer 6, which is the source region, to the ground potential wiring (not shown in the figure) is It is formed integrally with layer 6 so as to back it up. According to this embodiment, the source parasitic resistance can be further reduced. In FIG. 3, reference numeral 10 indicates a contact hole formed in an interlayer insulating film for connecting the single crystal silicon layer 7 and the ground potential wiring.

The present invention is applicable not only to resistive load type memories but also to MOS transistor load type MOS static memories.

[0029]

As explained above, in the MOS type static memory of the present invention, the connection between the storage node diffusion layer and the gate electrode, and the connection between the common source region and the ground potential wiring can be made using a selective growth method. Since this is performed using a crystalline silicon layer, the following effects can be achieved.

■ There is no need to provide a diffusion layer formed by impurity diffusion from the gate electrode adjacent to a normal diffusion layer, and diffusion layers formed by impurity diffusion from the gate electrode do not coexist. Since the margin of the interval can be reduced and there is no need to form a deep contact hole in the common source region, the memory cell size can be reduced and the memory can be highly integrated.

(2) Since diffusion layers formed in different formation processes are not used together, leakage current can be reduced.

(2) Since the distance from the gate electrode to the source contact is shortened, the source parasitic resistance can be reduced. Further, since the unbalance of the resistance within the memory cell is suppressed, the operational stability of the memory cell can be increased.

[Brief explanation of the drawing]

FIG. 1 is a plan view and a sectional view showing an embodiment of the present invention.

FIG. 2 is a process sectional view for explaining the manufacturing process of the part (b) in FIG.

FIG. 3 is a plan view showing another embodiment of the present invention.

FIG. 4 is a memory cell circuit diagram of a resistive load type MOS static memory.

FIG. 5 is a plan view of a conventional example.

FIG. 6 is a partial cross-sectional view of FIG. 5;

FIG. 7 is a characteristic diagram showing breakdown voltage between diffusion layers.

[Explanation of symbols]

1 P well 2, 2a, 4 SiO2 film 3 Polycrystalline silicon layer 5 Photoresist 6 N+ type diffusion layer 6a by ion implantation N+ type diffusion layer by impurity diffusion of gate electrode (polycrystalline silicon layer 3)
Type diffusion layer 7 Single crystal silicon layer 8 formed by selective growth method
Interlayer insulating film 9 Ground potential wiring 10, 11, 12 Contact hole

Claims (2)

[Claims] 1. The gate electrode of the first drive transistor is connected to the drain diffusion layer of the first transfer transistor and the drain diffusion layer of the second drive transistor, and the gate electrode of the second drive transistor is connected to the drain diffusion layer of the first transfer transistor and the drain diffusion layer of the second drive transistor. In a MOS type static memory in which a drive transistor and a second transfer transistor are connected to a common drain diffusion layer, and the source diffusion layers of the first and second drive transistors are respectively connected to a ground potential wiring, respective gate electrodes and A MOS type static memory characterized in that each drain diffusion layer is connected to a single crystal silicon layer formed by a selective growth method. 2. The gate electrode of the first drive transistor is connected to the drain diffusion layer of the first transfer transistor and the drain diffusion layer of the second drive transistor, and the gate electrode of the second drive transistor is connected to the drain diffusion layer of the first transfer transistor. In a MOS type static memory, the first drive transistor is connected to a common drain diffusion layer of the drive transistor and the second transfer transistor, and the source diffusion layers of the first and second drive transistors are respectively connected to a ground potential wiring. A MOS type static memory characterized in that the source diffusion layer of the second driving transistor and the source diffusion layer of the second driving transistor are connected to a ground potential wiring through a single crystal silicon layer formed by a selective growth method.