JPH05114714A - Semiconductor device - Google Patents

Abstract

PURPOSE:To bring a Vcc line, with which source voltage will be maintained, into a reliable low resistance state, and to increase a data access speed. CONSTITUTION:In a semiconductor device which can be applied to an SRAM and the like provided with a flip flop, constituted by a pair of transistors 82 and 83 and a pair of high resistance loads 89 and 90, and a Vcc line 85 with which source voltage is maintained by connecting it to the above-mentioned pair of high resistance loads, the high resistance loads 89 and 90 and the Vcc line 85 have a semiconductor layer 50, and on this semiconductor layer 50, the impurity density of the part 60, constituting the Vcc line 85, is higher than the impurity density of the part constituting the high resistance loads. Besides, by the formation of a conductive layer 56 of tungsten and the like on the high impurity density part 62 of the semiconductor layer 50, the Vcc line 85 is constituted by the above-mentioned layer 56 or the combination of the layer 56 and the semiconductor layer 60.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, a semiconductor LOGI.
The present invention relates to a semiconductor device improved to increase the data access speed of a semiconductor memory such as C or SRAM (static random access memory).

[0002]

2. Description of the Related Art As an example of a structure for increasing the data access speed of an SRAM, a power supply line having a two-layer structure of a semiconductor layer and a conductor layer is disclosed in Japanese Patent Publication No. 02-26067.
Japanese Patent Publication (published January 29, 1990). According to the invention described in this publication, polycrystalline silicon is used for the semiconductor layer and tungsten silicide is used for the conductor layer to form the power supply line into a two-layer structure.

[0003]

However, in the structure described in the above publication, since the high resistance semiconductor layer forming the resistance layer extends to the power supply layer, the value of the resistance layer becomes higher than the design value, The characteristics may not reach the expected values. Furthermore, since the conductor layer is directly formed on the high-resistance semiconductor layer, the resistance of the power supply layer may substantially contribute to the resistance of the high-resistance layer when the contact between the two is poor.
Also in the manufacturing method, when the power supply line is made, the power supply line is formed by patterning the conductor layer after forming the conductor layer on the semiconductor layer. There is a problem that the sizes of the resistances are likely to be different and it is very difficult to create the resistance value of the resistance layer to a desired value.

The present invention has been made based on the above circumstances, and a semiconductor device structure and a manufacturing method capable of manufacturing a semiconductor device capable of increasing the access speed as much as possible according to a design schedule. It is intended to provide.

[0005]

In order to achieve the above object, according to the present invention, there is provided a flip-flop having a pair of transistors and a pair of high resistance loads, and the pair of high resistance loads of the flip-flop. A semiconductor device having a power supply line to be connected includes: a semiconductor layer for forming the high resistance load and the power supply line, and an impurity concentration of a portion of the semiconductor layer forming the power supply line forms the high resistance load. And a conductive layer formed on a portion of the semiconductor layer having a high impurity concentration, and a power supply line is formed by cooperation between this conductive layer or this conductive layer and a semiconductor layer below the conductive layer. Yes. Further, the conductive layer contains a refractory metal. The refractory metal includes one of tungsten, titanium, or molybdenum.
The conductive layer contains a transition metal. The transition metal includes aluminum. The conductive layer includes refractory metal silicide. The refractory metal silicide includes one of tungsten silicide, titanium silicide, or molybdenum silicide. The conductive layer includes a polysilicon layer containing a high concentration impurity formed by selective epitaxial growth or solid phase epitaxial growth on the power supply wiring film.

Further, according to the present invention, a semiconductor device including a flip-flop configured with a pair of transistors and a pair of high resistance loads, and a power supply line connected to the pair of high resistance loads of the flip-flop, : Semiconductor layer,
The semiconductor layer has a first semiconductor layer forming the high resistance load and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer; and, formed on the second semiconductor layer. A conductive layer, a conductive layer, or a portion that constitutes the power supply line by cooperation of the conductive layer or the conductive layer and the second semiconductor layer. Further, the conductive layer contains a refractory metal. The refractory metal includes one of tungsten, titanium, or molybdenum. The conductive layer contains a transition metal. The transition metal includes aluminum. The conductive layer includes refractory metal silicide. The refractory metal silicide includes one of tungsten silicide, titanium silicide, or molybdenum silicide. The conductive layer includes a polysilicon layer containing a high concentration impurity formed by selective epitaxial growth or solid phase epitaxial growth on the power supply wiring film.

Further, according to the present invention, a semiconductor device having a circuit configuration in which a power supply line is connected to a transistor through a high resistance load is: a semiconductor layer which is connected to one terminal of a transistor and constitutes a layer of the high resistance load and the power supply line. The semiconductor layer has a first region having a certain impurity concentration and having a function of the high resistance load, and a region having a higher impurity concentration than the first semiconductor region and constituting a layer of the power supply line. And a conductive layer formed on the second region of the semiconductor layer. The semiconductor layer contains polycrystalline silicon. The conductive layer contains a refractory metal. The refractory metal includes one of tungsten, titanium, or molybdenum. The second region further has a third region forming a contact for connecting to one terminal of the transistor. The conductive layer further has a second conductive layer formed on the third region. The first region contains boron as an impurity. The second region contains phosphorus or arsenic as a high concentration impurity.

[0008]

According to the present invention, the sheet resistance is 400 to 600 Ω / cm as compared with the conventional one by introducing impurities into the film of the power source wiring and further providing a conductive layer made of a tungsten film or the like on the film after the impurity is introduced. ² to 5 to 15 Ω / cm
It becomes ² , and it becomes possible to reduce the resistance value of the power supply wiring to about 1/100 of the conventional value.

Further, the power supply wiring is made of a refractory metal film such as a titanium film, a molybdenum film, a tantalum film, or a tungsten silicide film, instead of the tungsten film.
A refractory metal silicide film such as a titanium silicide film, a molybdenum silicide film, or a tantalum silicide film can be used. Further, an aluminum film which has been conventionally used as an electrode wire of a semiconductor can be used for the purpose of obtaining conductivity. Further, for the purpose of lowering the resistance value of the power supply wiring by about one digit, not by about one hundredth, a polysilicon film in which a large amount of impurities are injected by selective epitaxial growth or solid phase epitaxial growth is used. However, similarly to the above, the resistance value of the power supply wiring can be reduced. Further, in the growth of the metal film, after forming a mask with a silicon dioxide film on the same film of the power supply wiring and the resistance portion, the power supply wiring portion of the silicon dioxide film is selectively opened and the opening is opened. By introducing impurities into the holes, the resistance value of the power supply wiring can be selectively lowered. As the mask, instead of the silicon dioxide film, a silicon nitride film,
The same purpose as described above can be achieved by using a BPSG film or a PSG film.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the SRAM cell shown in FIG. 1, the gate 81a of the first N-channel transistor 81 and the gate 84a of the fourth N-channel transistor 84 have a select line (word line).
ne) 85 connected to the drains 81b and 84 of the first and fourth N-channel transistors 81 and 84, respectively.
b is connected to two read lines (bit lines) (also serving as write lines) 86 and 87, respectively.
In addition, the source 8 of the first N-channel transistor 81
1c is connected to the drain 82b of the second N-channel transistor 82 and the gate 83a of the third N-channel transistor 83, and the source 84c of the fourth N-channel transistor 84 is the drain 83b of the third N-channel transistor 83. And a gate 82a of the second N-channel transistor 82.
Second and third N-channel transistors 82 and 83
The sources 82c and 83c are grounded (GND). Further, the first impedance element 89 is connected between the power supply line 88 and the drain 82b of the second N-channel transistor 82, and the power supply line 88 and the third N-channel transistor 82 are connected.
The second impedance element 90 is connected between the channel transistor 83 and the channel transistor 83.

When writing bit information into the memory cell configured as described above, first, the memory cell shown in this figure is selected by setting the select line 85 to the H level, and two read lines (write lines) 86 are selected. , 87 is set to the H level and the other is set to the L level, the bit information is written in this memory cell.

Here, the case where the read line (write line) 86 is at the L level and the read line (write line) 87 is at the H level will be described. First, when the selection line 85 becomes H level, the first and fourth transistors 81,
When the read line (write line) 86 is at the L level and the read line (write line) 87 is at the H level in this state, the contact 91 is at the H level. As a result, the second transistor 82 is turned on, the contact 92 is installed via this transistor 82, and the contact 92 becomes L level. This contact 9
2 becomes the L level, so that the third transistor 83
Is turned off. When the selection line 85 returns to the L level in this state, the first and fourth transistors 81 and 84 are turned off, and the contact 91 is kept at the H level and the contact 92 is kept at the L level. Here, the first and second impedance elements 89 and 90 are in the above memory state (a state in which one of the contact 91 and the contact 92 is at the H level and the other is at the L level) due to the leakage current of each transistor over time. In order to prevent the change, the current is supplied from the power supply line 88 by the leak current of each transistor. For example, a high impedance element of about teraohm is used. Contrary to the above description, the contact 9
In order to set 1 to the L level and the contact 92 to the H level, the write operation is performed by setting the read line (write line) 86 to the H level and the read line (write line) 87 to the L level, contrary to the above description. I'll do it.

FIG. 2 is a plan view showing the structure of the main part of the SRAM cell according to the present invention according to FIG. 1, that is, the power supply line 88, the impedance elements 89 and 90, and the contacts 91 and 92. As shown in FIG. 2, the SRAM of this embodiment corresponds to the power supply line 88 of FIG. 1 and has a low resistance power supply line 188 to which the power supply Vcc is applied, and the impedance elements 89 and 90 of FIG.
And a contact 19 corresponding to a contact 92 to which the load resistance sections 189, 190 of high resistance corresponding to the above and the transistors 81, 82, 83 in FIG.
2, the transistors 82, 83, 84 in FIG. 1 are provided with a contact 191 corresponding to the contact 91 connected to the impedance element 90. Also, contact 19
Inside 1,192, shown by broken lines 145 and 146 are contacts with the transistor corresponding to the contact hole 46 in FIG.

FIG. 3 shows the SRAM cell AA of FIG.
FIG. In FIG. 3, a P-type silicon substrate is used as the substrate 20. Element isolation films 32 and 34 are formed on the substrate 20, and the element isolation films 32 and 3 are formed.
4, a MOS type field effect transistor 30 corresponding to the transistor 82 of FIG. 1 is formed. This MOS
The field effect transistor 30 is composed of a drain 38, a source 40, and a gate 42 with an insulating film 36 in between. An interlayer insulating film 44 made of a silicon dioxide film is formed on the MOS field effect transistor 30 and the element isolation films 32 and 34. Then, contact holes 46 and 48 are formed in the interlayer insulating film 44 at positions facing the drain 38 and the source 40, respectively, and a polysilicon film 50 is formed in the contact hole 46 and an aluminum electrode 52 is formed in the contact hole 48. Has been formed. A tungsten layer 54 is selectively grown on the polysilicon film in the vicinity of the contact hole 46 to contact the contact 19 of FIG.
Make up 2. Further, the tungsten layer 56 is also formed on the polysilicon above the element isolation film 32 to form the power supply line 188 in FIG. In addition, the polysilicon layer 5
0 is doped with arsenic As or phosphorus P in the vicinity of the portions in contact with the tungsten layers 54 and 56 to reduce the resistance and facilitate the formation of tungsten on the polysilicon layer 50. Then, the polysilicon layers 58 and 6
The polysilicon region 62 sandwiched by 0s is left as a high resistance region to form the resistor 189 shown in FIG. Furthermore,
The tungsten layers 54 and 56 and the polysilicon region 62 are covered with an interlayer insulating film 66 made of an insulating material such as SiO.

Next, a method of manufacturing a semiconductor device having SRAM cells will be described with reference to FIGS. 4 to 9 by taking the case of manufacturing the structure of the embodiment shown in FIG. 3 as an example. 4 to 9, the same components as those in FIG. 3 have the same numbers. First, as shown in FIG. 4, element isolation films 32 and 34 and a MOS field effect transistor 30 are formed on a silicon substrate 20 using a known technique, and then an interlayer formed of a silicon dioxide film is used using a known CVD method. The insulating film 44 is formed. Next, as shown in FIG. 5, a contact hole 46 for electrically connecting to the drain 38 is formed in the interlayer insulating film 44 by using a well-known miniaturization technique, and then polysilicon is used by a well-known CVD method. The film 50 is formed. The thickness of the polysilicon film 50 is formed to be about 500Å to 1500Å.

As shown in FIG. 6, B ⁺ (boron) ions 6 are formed in the polysilicon film 50 by using a known ion implantation technique.
3 to 1 × 10 ¹² to 10 ¹³ ions / cm ² , energy 30 kev
Impurities are introduced by implanting under the condition of about 50 kev. At this time, the conditions are set so that the ions are almost uniformly distributed in the film.

Thereafter, as shown in FIG. 7, the polysilicon film 50 is patterned by using a known photolithography technique.

Next, as shown in FIG. 8, a silicon dioxide film 65 is formed on the order of 1000 Å to 3000 Å and patterned by a well-known fine processing technique. 6 of the polysilicon film 50 to be the load resistance portions 189 and 190
2 and the polysilicon film 50 is masked on the etched interlayer insulating film 44. After that, arsenic or phosphorus ions 67 are implanted by a known ion implantation technique to introduce impurities. In this process, the ion concentration in the polysilicon film 50 is 1 × 10 ²⁰ to 1 × 10 ²¹ atms.
It is necessary to perform it under the condition of about / cm ³ . The introduction of the impurities not only lowers the resistance value of the tungsten electrodes and the polysilicon films 58 and 60 formed below the power supply line, but also facilitates the selective growth of the tungsten.

Next, as shown in FIG. 9, the tungsten layer 54 is formed on the contacts 91 and 92 of the polysilicon film 50 shown in FIG. 2 and the portions 58 and 60 to be the Vcc lines 188 by using a known tungsten selective growth technique. , 56 to grow. At this time, it is desirable for flattening that the tungsten layers 54 and 56 have the same thickness as the insulating film mask 65. Next, as shown in FIG.
After growing 4, 56, the insulating film mask 65 is removed by using a known hydrofluoric acid etching technique.

Finally, as shown in FIG. 3, the interlayer insulating film 6
After forming 6, the source 40 is formed by using a known fine processing technique.
After forming the contact hole 48 for electrical connection with
The aluminum electrode 52 connected to GND in FIG. 1 is formed by using a known technique.

According to the above embodiment, the polysilicon film 50 is formed.
After selectively implanting an impurity into the portion 60 other than the portion 62 having a high resistance, the tungsten layer 56 is selectively grown to form the Vcc line 188 shown in FIG. The resistance can be easily reduced, and thus the access speed can be improved as compared with the conventional one.

Further, in the above-described embodiment, after the impurities are introduced into the film of the power supply wiring, the tungsten film is further formed on the film, so that the sheet resistance is 400 to 100%.
It becomes 600Ω / cm ² to 5 to 15Ω / cm ² , and it becomes possible to reduce the resistance value of the power supply wiring to about 1/100 of the conventional value.

Further, the power supply wiring is made of a refractory metal film such as a titanium film, a molybdenum film or a tantalum film, or a tungsten silicide film, instead of the tungsten film.
A refractory metal silicide film such as a titanium silicide film, a molybdenum silicide film, or a tantalum silicide film can be used. Further, an aluminum film which has been conventionally used as an electrode wire of a semiconductor can be used for the purpose of obtaining conductivity. Further, for the purpose of lowering the resistance value of the power supply wiring by about one digit, not by about one hundredth, a polysilicon film in which a large amount of impurities are injected by selective epitaxial growth or solid phase epitaxial growth is used. However, similarly to the above, the resistance value of the power supply wiring can be reduced. Further, in the growth of the metal film, after forming a mask with a silicon dioxide film on the same film of the power supply wiring and the resistance portion, the power supply wiring portion of the silicon dioxide film is selectively opened and the opening is opened. By introducing impurities into the holes, the resistance value of the power supply wiring can be selectively lowered. As the mask, instead of the silicon dioxide film, a silicon nitride film,
The same purpose as described above can be achieved by using a BPSG film or a PSG film.

As described above, according to the present invention, after the impurities are introduced into the film of the power supply wiring, a conductive layer such as a metal film or a polysilicon film is further grown, so that the power supply wiring is formed by a simple method. It is possible to provide a semiconductor device in which the resistance of the semiconductor device is reduced, and thus the access speed can be increased. In addition, after introducing impurities into the power wiring film, a tungsten film, a titanium film, a molybdenum film,
Refractory metal film such as tantalum film, aluminum film, tungsten silicide film, titanium silicide film, molybdenum silicide film, refractory metal silicide film such as tantalum silicide film, metal conductive film such as aluminum film or selective epitaxial growth, solid phase epitaxial growth By providing a polysilicon film containing a high concentration of impurities, a semiconductor device capable of lowering the resistance of the power supply wiring film by the same simple method as described above and thereby increasing the access speed is provided. can do. When growing a conductive layer such as a metal film or a polysilicon film, after forming a mask with a silicon dioxide film on the same film as the power supply wiring and the resistance portion, the power supply wiring portion of the silicon dioxide film is selectively A semiconductor device capable of increasing the access speed by selectively opening the hole and introducing impurities into the hole can selectively reduce the resistance value of the power supply wiring. can do.

[0025]

As described above, according to the present invention, the impurity is introduced into the film of the power supply wiring, and the conductive layer such as the metal film and the polysilicon film is further grown. It is possible to provide a semiconductor device in which the resistance of the wiring for use is reduced and thus the access speed can be increased.

After introducing impurities into the film of the power wiring, a tungsten film, a titanium film, a molybdenum film,
Refractory metal film such as tantalum film, aluminum film, tungsten silicide film, titanium silicide film, molybdenum silicide film, refractory metal silicide film such as tantalum silicide film, metal conductive film such as aluminum film or selective epitaxial growth, solid phase epitaxial growth By providing a polysilicon film containing a high concentration of impurities, a semiconductor device capable of lowering the resistance of the power supply wiring film by the same simple method as described above and thereby increasing the access speed is provided. can do.

Further, in growing a conductive layer such as a metal film or a polysilicon film, after forming a mask of a silicon dioxide film on the same film of the power supply wiring and the resistance portion, the power supply wiring portion of the silicon dioxide film is formed. By selectively opening holes and introducing impurities into the openings, it is possible to selectively reduce the resistance value of the power supply wiring, thereby increasing the access speed. A device can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a memory cell of an SRAM which is an embodiment of the present invention.

FIG. 2 is a plan view showing a schematic structure of a main part of the SRAM cell according to FIG.

FIG. 3 is a sectional view of the SRAM cell according to FIG. 1 taken along the line AA.

FIG. 4 is an explanatory diagram for explaining each step of the method for manufacturing the SRAM cell according to FIG.

FIG. 5 is an explanatory diagram for explaining each step of the method for manufacturing the SRAM cell according to FIG. 3;

6A and 6B are explanatory diagrams illustrating a method of manufacturing the SRAM cell according to FIG. 3 for each step.

FIG. 7 is an explanatory diagram for explaining each step of the method for manufacturing the SRAM cell according to FIG. 3;

FIG. 8 is an explanatory diagram for explaining, for each step, the method of manufacturing the SRAM cell according to FIG. 3;

FIG. 9 is an explanatory diagram for explaining each step of the method for manufacturing the SRAM cell according to FIG. 3;

FIG. 10 is an explanatory diagram for explaining each step of the method for manufacturing the SRAM cell according to FIG. 3;

[Explanation of symbols]

 20 substrate 30 MOS type field effect transistor 32, 34 element isolation film 36 insulating film 44 interlayer insulating film 50 polysilicon film 56 tungsten layer 58, 60 polysilicon layer 81 first N-channel transistor 82 second N-channel transistor 83 second 3 N-channel transistor 84 4th N-channel transistor 85 Select line 86, 87 Read line (also serves as write line) 88 Power line 89, 90 Impedance element

Claims (24)

[Claims] 1. A semiconductor device comprising: a flip-flop including a pair of transistors and a pair of high-resistance loads; and a power supply line connected to the pair of high-resistance loads of the flip-flop. Including: a semiconductor layer for forming the high resistance load and the power supply line,
In this semiconductor layer, the impurity concentration of the portion forming the power supply line is higher than that of the portion forming the high resistance load; and the conductive layer formed on the portion of the semiconductor layer having a high impurity concentration, A power supply line is formed by the cooperation of this conductive layer or this conductive layer and the semiconductor layer therebelow. 2. The semiconductor device according to claim 1, wherein the conductive layer contains a refractory metal. 3. The semiconductor device according to claim 2, wherein the refractory metal includes one of tungsten, titanium, and molybdenum. 4. The semiconductor device according to claim 1, wherein the conductive layer contains a transition metal. 5. The semiconductor device according to claim 4, wherein the transition metal contains aluminum. 6. The semiconductor device according to claim 1, wherein the conductive layer contains a refractory metal silicide. 7. The semiconductor device according to claim 6, wherein the refractory metal silicide includes one of tungsten silicide, titanium silicide, and molybdenum silicide. 8. The conductive layer includes a polysilicon layer containing high-concentration impurities formed on the film of the power supply wiring by selective epitaxial growth or solid-phase epitaxial growth. Semiconductor device. 9. A semiconductor device comprising: a flip-flop including a pair of transistors and a pair of high-resistance loads; and a power supply line connected to the pair of high-resistance loads of the flip-flop. Including: a semiconductor layer, the semiconductor layer having a first semiconductor layer forming the high resistance load and a second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer; and the second semiconductor layer. A conductive layer formed on the semiconductor layer, the conductive layer, or a portion forming the power supply line in cooperation with the conductive layer and the second semiconductor layer. 10. The semiconductor device according to claim 9, wherein the conductive layer contains a refractory metal. 11. The semiconductor device according to claim 10, wherein the refractory metal includes one of tungsten, titanium, and molybdenum. 12. The semiconductor device according to claim 9, wherein the conductive layer contains a transition metal. 13. The semiconductor device according to claim 12, wherein the transition metal contains aluminum. 14. The semiconductor device according to claim 9, wherein the conductive layer contains a refractory metal silicide. 15. The semiconductor device according to claim 14, wherein the refractory metal silicide includes one of tungsten silicide, titanium silicide, and molybdenum silicide. 16. The method according to claim 9, wherein the conductive layer includes a polysilicon layer containing a high concentration impurity formed on the film of the power supply wiring by selective epitaxial growth or solid phase epitaxial growth. Semiconductor device. 17. A semiconductor device having a circuit structure in which a power supply line is connected to a transistor through a high resistance load, including the following structure: a transistor connected to one terminal, and a layer of the high resistance load and the power supply line are connected to each other. A semiconductor layer to be formed, a first region having a certain impurity concentration and having a high resistance load function, and a higher impurity concentration than the first semiconductor region to form the power supply line layer. A second region having a region; and a conductive layer formed on the second region of the semiconductor layer. 18. The semiconductor device according to claim 17, wherein the semiconductor layer contains polycrystalline silicon. 19. The semiconductor device according to claim 17, wherein the conductive layer contains a refractory metal. 20. The semiconductor device according to claim 19, wherein the refractory metal includes one of tungsten, titanium, and molybdenum. 21. The semiconductor device according to claim 17, wherein the second region further has a third region forming a contact for connecting to one terminal of the transistor. 22. The semiconductor device according to claim 21, wherein the conductive layer further has a second conductive layer formed on the third region. 23. The semiconductor device according to claim 17, wherein the first region contains boron as an impurity. 24. The semiconductor device according to claim 17, wherein the second region contains phosphorus or arsenic as a high concentration impurity.