JPH04256349A - Cooling structure of board - Google Patents

Cooling structure of board

Info

Publication number
JPH04256349A
JPH04256349A JP3017362A JP1736291A JPH04256349A JP H04256349 A JPH04256349 A JP H04256349A JP 3017362 A JP3017362 A JP 3017362A JP 1736291 A JP1736291 A JP 1736291A JP H04256349 A JPH04256349 A JP H04256349A
Authority
JP
Japan
Prior art keywords
board
substrate
coolant
heat
cold plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3017362A
Other languages
Japanese (ja)
Inventor
Masahiro Mochizuki
優宏 望月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3017362A priority Critical patent/JPH04256349A/en
Publication of JPH04256349A publication Critical patent/JPH04256349A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F28HEAT EXCHANGE IN GENERAL
    • F28FDETAILS OF HEAT-EXCHANGE AND HEAT-TRANSFER APPARATUS, OF GENERAL APPLICATION
    • F28F3/00Plate-like or laminated elements; Assemblies of plate-like or laminated elements
    • F28F3/12Elements constructed in the shape of a hollow panel, e.g. with channels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Thermal Sciences (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide structure which cools, by a liquid cooling operation, a board on which a wafer-scale IC has been mounted by a method wherein the structure is constituted of a specific board a specific cold plate, a first specific coolant and the like and heat of the first coolant to which heat of the board has been conducted is exchanged with a second coolant. CONSTITUTION:The title structure is constituted of the following: a board 1 where a wafer-scale IC 3 provided with a plurality of IC's 7 has been mounted on a wafer; a cold plate 2 which is provided with water passages 8 for a second coolant 19 and with caps 10 so as to protrude into the water passages 8 and to correspond to the IC's 7 at the inside and which is sealed hermetically with reference to the board 1; and a first coolant 18 which is sealed in the space between the board 1 and the caps 10 at the cold plate 2. Heat of the first coolant 18 to which heat of the board 1 has been conducted is exchanged with the second coolant 19. For example, heat generated form a wafer-scale IC 3 is conducted to a silicone oil 18, the warmed silicone oil 18 is raised to the upper part at the inside of caps 10, the heat is exchanged with cooling water 19 flowing in water passages 8, and the IC is cooled.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、基板の冷却構造に係り
、特にウェハースケールICを実装した基板の冷却構造
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cooling structure for a substrate, and more particularly to a cooling structure for a substrate on which a wafer scale IC is mounted.

【0002】0002

【従来の技術】従来は図5に示すように、基板50上に
実装されたLSI54に対して、その上方から内部に冷
媒の供給路53と排出路52を有し、基板50に実装さ
れたLSI54の実装位置に対応して突出するノズル5
5および、LSI54の実装上のバラツキを許容するベ
ローズ56とを有するコールドプレート51を配置する
2. Description of the Related Art Conventionally, as shown in FIG. 5, an LSI 54 mounted on a substrate 50 has a refrigerant supply path 53 and a refrigerant discharge path 52 inside from above. Nozzle 5 that protrudes corresponding to the mounting position of LSI 54
5 and a bellows 56 that allows variations in mounting of the LSI 54.

【0003】そして、コールドプレート51内に冷媒を
供給すると、ノズル55から噴射された冷媒が伝熱板6
1を介してLSI54との熱交換を行い、基板50上に
実装されたLSI54の冷却が行われていた。
When refrigerant is supplied into the cold plate 51, the refrigerant injected from the nozzle 55 hits the heat transfer plate 6.
The LSI 54 mounted on the board 50 was cooled by exchanging heat with the LSI 54 through the board 50 .

【0004】しかし近年の高密度に伴い、基板上に実装
されるLSIの代わりに、図3に示す基板1の表面にウ
ェハー上に複数のIC7が形成されたウェハースケール
IC3を実装したものが考案されている。
However, with the recent trend toward higher density, instead of LSIs mounted on a substrate, a wafer scale IC 3, in which a plurality of ICs 7 are formed on a wafer, is mounted on the surface of the substrate 1 shown in FIG. 3. has been done.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来で
はウェハースケールICが実装された基板を冷却するも
の、特に高い冷却能力を有することが知られている液冷
にて冷却するものはなく、動作信頼性上問題があった。
[Problems to be Solved by the Invention] However, there is no conventional method for cooling a substrate on which wafer-scale ICs are mounted, especially liquid cooling, which is known to have a high cooling capacity, and the operation reliability is not high. There was a sexual problem.

【0006】従って、本発明はウェハースケールICが
実装された基板を液冷にて冷却することを目的とするも
のである。
[0006] Accordingly, an object of the present invention is to cool a substrate on which a wafer scale IC is mounted by liquid cooling.

【0007】[0007]

【課題を解決するための手段】上記目的は、ウェハー上
に複数のIC7を有するウェハースケールIC3が実装
された基板1と、内部に第2の冷媒19の水路8と、該
水路8内に突入する該IC7対応に設けられたキャップ
10とを有し、該基板1と密閉されるコールドプレート
2と、該基板1と該コールドプレート2の該キャップ1
0との空間に封止される第1の冷媒18と、から構成さ
れ、該基板1の熱が伝わった該第1の冷媒18を該第2
の冷媒19により熱交換することを特徴とする基板の冷
却構造、によって達成される。
[Means for Solving the Problems] The above object is to provide a substrate 1 on which a wafer scale IC 3 having a plurality of ICs 7 is mounted, a water channel 8 for a second coolant 19 inside, and a water pipe 8 that flows into the water channel 8. a cold plate 2 having a cap 10 provided to correspond to the IC 7 and sealed with the substrate 1; and the cap 1 of the substrate 1 and the cold plate 2.
a first refrigerant 18 sealed in a space between the substrate 1
This is achieved by a substrate cooling structure characterized by heat exchange using a refrigerant 19.

【0008】[0008]

【作用】本発明において、基板およびウェハースケール
ICが発する熱は、基板とキャップとの間を封止した第
1の冷媒へと伝達される。
In the present invention, heat generated by the substrate and wafer scale IC is transferred to the first coolant sealed between the substrate and the cap.

【0009】一方、コールドプレート内を流れる第2の
冷媒によって、キャップを介して第1の冷媒と熱交換が
行われる。
On the other hand, the second refrigerant flowing within the cold plate exchanges heat with the first refrigerant through the cap.

【0010】キャップ内(対流域)の第1の冷媒におい
ては、基板側に近い方が当然温度が高く、コールドプレ
ートに近い方(水路の内部)が温度が比較ため、両者間
に対流が発生し、このキャップ内でその冷却が能率よく
行われる。
[0010] Regarding the first refrigerant in the cap (convection area), the one closer to the substrate side is naturally higher in temperature, and the temperature closer to the cold plate (inside the water channel) is compared, so convection occurs between the two. However, cooling is efficiently performed within this cap.

【0011】[0011]

【実施例】以下、本発明の望ましい実施例を図1乃至図
4を用いて詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4.

【0012】図1は本発明の実施例を示す図である。図
2はコールドプレート斜視図である。
FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a perspective view of the cold plate.

【0013】図3は基板斜視図である。図4はコールド
プレート分解斜視図である。
FIG. 3 is a perspective view of the substrate. FIG. 4 is an exploded perspective view of the cold plate.

【0014】図1および図3に示すように、円形状の基
板1の表面に接着剤11を介してウェハースケールIC
3を実装し、そのウェハースケールIC3の表面には、
マトリクス状にIC7が形成されている。そして、ウェ
ハースケールIC3と基板1とはワイヤ5によって配線
がなされており、基板1の縁は基板取付ハウジング4に
ボルト孔15が穿孔され、ボルト20によって締結され
る。尚、基板1の背面には、電源供給用または信号供給
用のI/Oピン12が立植している。
As shown in FIGS. 1 and 3, a wafer scale IC is attached to the surface of a circular substrate 1 via an adhesive 11.
3 is mounted, and on the surface of the wafer scale IC3,
IC7s are formed in a matrix. The wafer scale IC 3 and the substrate 1 are wired by wires 5, and bolt holes 15 are formed in the substrate mounting housing 4 at the edge of the substrate 1 and fastened with bolts 20. Incidentally, I/O pins 12 for power supply or signal supply are set up on the back side of the board 1.

【0015】一方、上記ウェハースケールIC3を冷却
するコールドプレート3は、図2および図4に示すよう
に、基板1と対向する面の背面に凹部2bが形成され、
後述説明するキャップ10が挿入される孔2cがキャッ
プ10の挿入位置に対応して穿孔されている。尚、この
凹部2cは第2の冷媒19、例えば冷却水が流動する水
路8となるものである。更に、このコールドプレート2
の基板側面には基板1との気密性を高めるためにシール
6がその全周に渡って取りつけられるシールミゾ13が
形成されていると共に、上記凹部2bに対しては、水路
8の形成のために当該凹部2bを覆うように冷却水の供
給先或いは排出先となるニップル16,16を有するフ
タ2aが取りつけられる。尚、このコールドプレート2
とフタ2aとは図2の斜視図で示す如く、ボルト14に
よって締結されている。
On the other hand, as shown in FIGS. 2 and 4, the cold plate 3 for cooling the wafer scale IC 3 has a recess 2b formed on the back side of the surface facing the substrate 1.
A hole 2c into which a cap 10 (described later) is inserted is bored corresponding to the insertion position of the cap 10. Note that this recess 2c serves as a water channel 8 through which the second refrigerant 19, for example cooling water, flows. Furthermore, this cold plate 2
A seal groove 13 is formed on the side surface of the substrate to which a seal 6 is attached over the entire circumference in order to improve airtightness with the substrate 1, and a seal groove 13 is formed in the recess 2b to form a water channel 8. A lid 2a having nipples 16, 16 to which cooling water is supplied or discharged is attached so as to cover the recess 2b. Furthermore, this cold plate 2
and the lid 2a are fastened together with bolts 14, as shown in the perspective view of FIG.

【0016】キャップ10を有するコールドプレート2
に対し、第1の冷媒18、例えばシリコンオイル等を注
入する場合は、コールドプレート2を基板1側が上にな
るように引っ繰り返し、この状態でシリコンオイル18
を注入する。そして、図3に示す基板1をそのシリコン
オイル18内にウェハースケールIC3が浸るようにし
て、基板取付ハウジング4をコールドプレート2にボル
ト20にて締結することでシリコンオイル18の注入が
行われる。尚、シリコンオイル18を注入する場合、キ
ャップ10内に空気の混入をなくして完全に注入するの
ではなく、一部空気が混入されるようにして注入するこ
とが望ましい。この混入された空気は図1に示すように
、キャップ10内で気体9として残り、この気体9によ
ってシリコンオイル18の膨張等を抑止している。
Cold plate 2 with cap 10
On the other hand, when injecting the first coolant 18, such as silicone oil, turn over the cold plate 2 so that the substrate 1 side faces up, and in this state, inject the silicone oil 18.
inject. Then, the silicone oil 18 is injected into the substrate 1 shown in FIG. 3 by immersing the wafer scale IC 3 in the silicone oil 18 and fastening the substrate mounting housing 4 to the cold plate 2 with bolts 20. When injecting the silicone oil 18, it is desirable not to completely inject the silicone oil 18 into the cap 10 without any air being mixed in, but to inject it so that some air is mixed in. As shown in FIG. 1, this mixed air remains as gas 9 within the cap 10, and this gas 9 prevents the silicone oil 18 from expanding.

【0017】次に図1を用いて本発明の冷却作用を説明
する。上記のように構成された状態(通常の配置とする
ために再度引っ繰り返した状態)を図1に示す。
Next, the cooling effect of the present invention will be explained using FIG. FIG. 1 shows a state configured as described above (a state in which it has been turned over again to obtain a normal arrangement).

【0018】この状態において、冷媒供給側のニップル
16から冷却水19を注入する。一方、冷却水19が注
入された時点でウェハースケールIC3を動作させると
、そのウェハースケールIC3のIC7の動作に伴う熱
が発される。
In this state, cooling water 19 is injected from the nipple 16 on the coolant supply side. On the other hand, if the wafer scale IC 3 is operated at the time when the cooling water 19 is injected, heat is generated due to the operation of the IC 7 of the wafer scale IC 3.

【0019】ウェハースケールIC3から発された熱は
シリコンオイル18に伝達され、温まったシリコンオイ
ル18はキャップ10内におけるその上方へと上昇して
いく。このキャップ10は冷却水19内の水路8に突入
しているため、水路8を流動する冷却水19との間で熱
交換によって冷却され、再度そのキャップ10内におけ
るその下方へと下降していく。つまり、IC7に対応し
たキャップ10内が対流域17となってシリコンオイル
18対流される。従って、キャップ10内で積極的に自
然対流が発生し、ウェハースケールIC3の冷却が効率
良く行われるものである。
The heat generated from the wafer scale IC 3 is transferred to the silicone oil 18, and the heated silicone oil 18 rises upward within the cap 10. Since this cap 10 enters the water channel 8 in the cooling water 19, it is cooled by heat exchange with the cooling water 19 flowing in the water channel 8, and then descends downward in the cap 10 again. . That is, the inside of the cap 10 corresponding to the IC 7 becomes a convection area 17, and the silicone oil 18 is convected. Therefore, natural convection is actively generated within the cap 10, and the wafer scale IC 3 is efficiently cooled.

【0020】上記のように、ウェハースケールIC3の
場合は直接IC7が露出しているため、冷却水19を直
接当てると冷却水19内のゴミ等でショートする可能性
があるが、本実施例においては、直接冷却水19を当て
るのではなく、ウェハースケールIC3に悪影響を与え
ることのないシリコンオイル18を当て、更に冷却水1
9とはキャップ10を介して冷却するようにしているの
で、ショート等の心配がなく、信頼性が向上する。
As mentioned above, in the case of the wafer scale IC 3, the IC 7 is directly exposed, so if the cooling water 19 is applied directly, there is a possibility of a short circuit due to dust in the cooling water 19, but in this embodiment, Instead of applying cooling water 19 directly, apply silicone oil 18 that does not have a negative effect on the wafer scale IC 3, and then apply cooling water 19.
9 is cooled through the cap 10, so there is no fear of short circuits and the reliability is improved.

【0021】尚、上記例においては、図2乃至図4から
明白なように、基板1およびコールドプレート2自体が
円形となっていたが、特にこれに限定されるものではな
く、その他四角形であってもよい。
In the above example, as is clear from FIGS. 2 to 4, the substrate 1 and the cold plate 2 themselves are circular, but the shape is not limited to this, and other square shapes may be used. It's okay.

【0022】[0022]

【発明の効果】以上のように本発明によって、近年特に
見られるその表面にウェハースケールICを搭載してな
る基板に対して、冷却効率に優れた液例にて冷却するこ
とができ、動作信頼性が向上する。
As described above, according to the present invention, it is possible to cool a substrate having a wafer scale IC mounted on its surface, which has been particularly seen in recent years, with a liquid having excellent cooling efficiency, thereby improving operational reliability. Improves sex.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.

【図2】コールドプレート斜視図である。FIG. 2 is a perspective view of a cold plate.

【図3】基板斜視図である。FIG. 3 is a perspective view of a substrate.

【図4】コールドプレート分解斜視図である。FIG. 4 is an exploded perspective view of the cold plate.

【図5】従来例を示す図である。FIG. 5 is a diagram showing a conventional example.

【符号の説明】[Explanation of symbols]

1    基板 2    コールドプレート 3    ウェハースケールIC 7    IC 8    水路 10  キャップ 18  第1の冷媒(シリコンオイル)19  第2の
冷媒(冷却水)
1 Substrate 2 Cold plate 3 Wafer scale IC 7 IC 8 Water channel 10 Cap 18 First coolant (silicon oil) 19 Second coolant (cooling water)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  ウェハー上に複数のIC(7)を有す
るウェハースケールIC(3)が実装された基板(1)
と、内部に第2の冷媒(19)の水路(8)と、該水路
(8)内に突入する該IC(7)対応に設けられたキャ
ップ(10)とを有し、該基板(1)と密閉されるコー
ルドプレート(2)と、該基板(1)と該コールドプレ
ート(2)の該キャップ(10)との空間に封止される
第1の冷媒(18)と、から構成され、該基板(1)の
熱が伝わった該第1の冷媒(18)を該第2の冷媒(1
9)により熱交換することを特徴とする基板の冷却構造
[Claim 1] A substrate (1) on which a wafer scale IC (3) having a plurality of ICs (7) is mounted on the wafer.
The board (1) has a water channel (8) for the second refrigerant (19) therein, and a cap (10) provided to correspond to the IC (7) that plunges into the water channel (8). ), and a first refrigerant (18) sealed in a space between the substrate (1) and the cap (10) of the cold plate (2). , the first refrigerant (18) to which the heat of the substrate (1) has been transferred is transferred to the second refrigerant (1).
9) A substrate cooling structure characterized by heat exchange.
JP3017362A 1991-02-08 1991-02-08 Cooling structure of board Withdrawn JPH04256349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3017362A JPH04256349A (en) 1991-02-08 1991-02-08 Cooling structure of board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3017362A JPH04256349A (en) 1991-02-08 1991-02-08 Cooling structure of board

Publications (1)

Publication Number Publication Date
JPH04256349A true JPH04256349A (en) 1992-09-11

Family

ID=11941926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3017362A Withdrawn JPH04256349A (en) 1991-02-08 1991-02-08 Cooling structure of board

Country Status (1)

Country Link
JP (1) JPH04256349A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448108A (en) * 1993-11-02 1995-09-05 Hughes Aircraft Company Cooling of semiconductor power modules by flushing with dielectric liquid
US5777384A (en) * 1996-10-11 1998-07-07 Motorola, Inc. Tunable semiconductor device
CN105097733A (en) * 2015-08-27 2015-11-25 电子科技大学 Paraffin-based air-cooled and water-cooled combined cooling device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448108A (en) * 1993-11-02 1995-09-05 Hughes Aircraft Company Cooling of semiconductor power modules by flushing with dielectric liquid
US5777384A (en) * 1996-10-11 1998-07-07 Motorola, Inc. Tunable semiconductor device
CN105097733A (en) * 2015-08-27 2015-11-25 电子科技大学 Paraffin-based air-cooled and water-cooled combined cooling device

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