JPH04256332A - Inspection apparatus of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify the search operation of an electron-beam or ion-beam irradiation position and to enhance the inspection efficiency of the title apparatus by a method wherein a data is used in common between an apparatus which measures the internal voltage of a chip and an apparatus which performs a processing treatment to the chip. CONSTITUTION:An EB-tester control apparatus 23 executes an internal-voltage measuring treatment on the basis of a reflected electron amount from a DUT 21. The control apparatus 23 compares a measured voltage with an expected voltage value, decides the defective part of the DUT 21, decides a processing content regarding the defective part and stores these decided results in an external storage device 61. An FIB control apparatus 50 decides a processing content according to stored information in the external storage device 61 and executes it; after that, the content of a processing treatment and positional information on the processing treatment are stored in the external storage device 61. In addition, the information is utilized on the side of an EB tester 10 when a voltage waveform is measured again.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a testing device for semiconductor integrated circuits, and more specifically, a device (for example, an EB tester) that measures operating waveforms on a chip in a non-contact manner, and a device that physically tests patterns on a chip in a non-contact manner. Processing equipment (e.g. FIB equipment)
This invention relates to an inspection device intended for collaboration with.

[0002] Generally, circuits that have been simulated in the design process are passed on to the manufacturing process, and in this manufacturing process prototype ICs are created as engineering samples.
is made. A circuit designer obtains this IC and tests and evaluates whether its functions are correct (so-called prototype testing).

[0003] In prototype testing, the input vectors of the workstation's logic simulation are connected to the IC under test (hereinafter referred to as DUT).
), and while the DUT is actually operating, the output signal vector obtained from the DUT is compared with the output expected value vector to determine a malfunctioning DUT.

[0004] In such prototype tests, it is important not only to test using external terminals, but also to observe voltage signals of internal circuits of wafers and chips. This is because the cause of failure cannot often be determined by testing only from external terminals.

In this case, a metal probe is applied to a desired node on the wafer or chip of the DUT to extract an output vector from the internal circuit, and this output vector is compared with the expected value vector of logic simulation at the workstation. Find errors in logic design and malfunctions in manufacturing.

By the way, in such a metal probe method, the insulating coating on the surface of the wafer or chip must be removed using a solution or the like. In addition, it is necessary to press the metal probe strongly in order to reduce the contact resistance, and there is a drawback that the tip of the probe easily damages the wafer or chip surface, causing damage to the DUT.

[0007]

2. Description of the Related Art As a measuring device that does not cause damage to a DUT, for example, an electron beam tester (abbreviated as an EB tester) is known.

The EB tester irradiates the DUT with an electron beam and detects the DU based on the amount of secondary electrons reflected from the DUT.
It measures the potential of T wiring, electrodes, etc., and allows the actual internal operation waveform of the DUT to be observed without using metal probes or the like.

By the way, from the results of these waveform observations,
For example, processing is performed to cut or connect wiring, electrodes, etc. at specific parts of the DUT, or to make holes in an insulating film.

For example, a focused ion beam device (abbreviated as an FIB device) is known as a device that performs such processing in a non-contact manner. Performs physical processing on specific parts using ion beam irradiation energy.

[0011]

[Problems to be Solved by the Invention] However, in such conventional semiconductor integrated circuit testing equipment, the EB tester and the FIB equipment are configured to function independently. When a portion is searched by the FIB device, there are problems in that the work is very troublesome and the inspection efficiency is extremely low.

The present invention has been made in view of these problems, and includes a device for measuring the internal voltage of a chip (for example, an EB tester) and a device for processing the chip (for example, an FIB device). We aim to share data between
The purpose is to improve coordination between both devices.

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a measuring means for measuring the electric potential of wirings, electrodes, etc. on a chip, and a measuring means for measuring the electric potential of wirings, electrodes, etc. on a chip, as shown in FIG. identification means for identifying a defective part based on the measurement results of and specifying processing details for the defective part;
a first holding means for holding positional information and processing designation information of the defective part; and searching for a position on the chip according to the positional information, and performing physical processing on wiring, electrodes, etc. at the position according to the processing designation information. a processing means, a second holding means for holding information on the processed position and processing details, searching for a specific part on the chip according to the processed position information, measuring the electric potential of the specific part, and processing it; The present invention is characterized by comprising a verification means for verifying the chip operation associated with the chip operation.

[0014]

According to the present invention, the specifying means specifies the defective position on the chip and the processing contents related to the position according to the measurement result of the measuring means, and the specified information is held in the first holding means.

[0015] Then, the processing means refers to the information in the first holding means and performs processing on the defective position on the chip.

Next, after the information on the machining results is held in the second holding means, the verification means verifies the chip operation accompanying the machining process based on this information. That is, a predetermined device (
For example, an EB tester) and a predetermined device that functions as a processing means (for example, an FIB device) are information-linked via the first holding means and the second holding means, thus increasing the cooperation between the two devices. .

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. 2 to 4 are diagrams showing an embodiment of a semiconductor integrated circuit testing device according to the present invention, and are examples applied to an EB tester and an FIB device.

First, the configuration will be explained. In Figure 2, 1
0 is an EB tester that functions as a measurement means, identification means, and verification means; 30 is an FIB device that functions as a processing means; 60a and 60b are data transfer lines; and 61 is an external memory that functions as a first holding means and a second holding means. device (eg, a fixed disk device).

The EB tester 10 sequentially includes an electron gun 12, a blanker 13, a condenser lens 14, a scanning deflector 15, an objective lens 16, an energy analyzer 17, a secondary electron detector 18, etc. inside a lens barrel 11. Arrange and electron gun 1
An electron beam 19 from 2 is deflected and scanned while being guided onto a DUT (for example, a semiconductor chip) 21 placed on an XY stage 20, and irradiated onto an arbitrary position.

Here, the DUT 21 is given a drive signal from the drive circuit 22, and this drive signal is applied to the DUT 21.
21 (ie, power supply, input/output signals, etc.).

The EB tester control device 23 controls the operation of each part of the tester, and also executes internal voltage measurement processing based on the amount of reflected electrons from the DUT 21. Also EB
The tester control device 23 determines the defective part of the DUT 21 by comparing the measured voltage and the expected voltage value, and also determines the processing details for the defective part (for example, cutting unnecessary wiring, connecting unconnected wiring, or changing the insulation film). (drilling, etc.) and stores the determination result in the external storage device 61.

On the other hand, the FIB device 40 includes an ion gun 42, a blanker 43, and a condenser lens 4 inside a lens barrel 41.
4. A scanning deflector 45, an objective lens 46, an electron detector 47, etc. are arranged in sequence, and a focused ion beam 48 from an ion gun 41 is transmitted to a DUT (
(same as that used in the above-mentioned EB tester) 21 and performs physical processing on a predetermined position of the DUT 21.

The FIB control device 50 controls the operation of each part of the FIB device, and also controls processing details (for example, cutting unnecessary wiring, connecting unconnected wiring, or drilling holes in an insulating film) according to information held in an external storage device 61. ) is determined and executed, and the contents of the processing and processing position information are stored in the external storage device 61.

FIG. 3 is a diagram showing the data format in the external storage device 61, which employs a so-called card type database. One card can contain multiple items (#1 to #9)
Each item is assigned to the following content, for example.

#1: Processing content information specified by the EB tester (E$) E$=1: Voltage waveform measurement wiring E$=2: Wiring cutting required E$=3: Wiring connection required #2: FIB Processing information by equipment (F$) F$=1: Cutting the wire F$=2: Connecting the wire F$=3: Drilling a hole in the insulating film #3: Cutting, drilling, or location of connection source Coordinate information (P
1$) #4: Cutting, drilling, or connection source internet information (N1
$) #5: Cutting, drilling, or connection source layer number information (L1
$) #6: Location coordinate information of connection destination (P2$) #7: Net information of connection destination (N2$) #8: Layer number information of connection destination (L2$) #9: Comment field (C$) Here In a card-type database, you can select a specific item and specify its contents to search for the corresponding card.For example, you can generally specify a name as a search term and search for an address, phone number, etc. It is used for. That is,
According to the above example, select #1 item and get E$=2
If you specify (wire cutting required), information such as the wiring cutting position (P1$, N1
$, L1$) can be found.

FIG. 4 is an operational flow diagram of the system. In this flow diagram, first, the DUT 21 is set in the EB tester 10 and driven (step 70), and a data file (files of all cards) is read from the external storage device 61 (step 71). Search for cards with $>0 (ie, cards with F$ of 1, 2, or 3) (step 72).

If YES, it is determined that some processing has been performed in the process described later, and the information in the search card (P1$, N1$, L1$, P2$, N2$, L2$
), identify the position, net, and layer, measure the voltage waveform (step 73), and verify the circuit contents from changes in the voltage waveform due to processing (step 7).
4).

On the other hand, if step 72 is NO, that is, if no processing has been performed, first, the DUT2
A voltage waveform measurement is performed at an arbitrary position of 1 (step 75), and a defective location is identified from the measurement result (step 76). Next, the cause of the defect is estimated and a hypothesis is established (step 77), and a method for verifying the hypothesis is considered (step 78). That is, a cause that may cause the voltage waveform to be defective is found, and a processing method (such as cutting or connecting wiring) is determined to verify the cause (step 79).

The determined processing method is stored in the #1 item of the card at that processing position (or a new card if there is no card), and then the entire data file is written back to the external storage device 61 (step 80).

[0030] When the above processing is completed, the DUT 21 is
It is removed from the B tester 10 and set in the FIB device 40 (step 81), and then the external storage device 61 is accessed to read the data file (step 82). This data file is generated or updated on the EB tester 10 side, and holds information regarding the content to be processed and its processing position.

That is, after checking the E$ contents of all cards in the data file and searching for cards with E$=2 or 3 (that is, processing required) (step 83
), and according to the processing details (connection processing or cutting processing), the wiring connection processing by the FIB (step 84) or the wiring cutting processing by the FIB (step 85) is executed. Then, F$ is set to 1 or 2 for each processing content (steps 86, 87), and after writing the data file back to the external storage device 61, step 70 is executed again.

As described above, according to this embodiment, when a defective waveform is detected on the EB tester 10 side, information such as its position and the content to be processed is written to the external storage device 61, so this information is stored in the FIB device 40. Can be used on the side. Therefore, the work of searching for a processing position can be facilitated.

[0033] Furthermore, since the processing contents on the FIB device 40 side are written to the external storage device 61, this information can be
It can be used on the B tester 10 side. Therefore, when remeasuring the voltage waveform, positioning can be facilitated.

That is, the data file in the external storage device 61 can be shared between the EB tester 10 and the FIB device 40, simplifying the search work for the electron beam or ion beam irradiation position and improving the inspection efficiency. can.

[0035]

[Effects of the Invention] According to the present invention, data can be shared between a device that measures the internal voltage of a chip (e.g., an EB tester) and a device that processes the chip (e.g., an FIB device). It is possible to improve the coordination between both devices.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a system configuration diagram of one embodiment.

FIG. 3 is a conceptual diagram of a data file in one embodiment.

FIG. 4 is an operational flow diagram of one embodiment.

[Explanation of symbols]

10: EB tester (measurement means, identification means, verification means) 2
3: DUT (chip) 30: FIB device (processing means)

Claims (1)

[Claims] 1. Measuring means for measuring the potential of wiring, electrodes, etc. on a chip; and specifying means for identifying a defective part based on the measurement results of the measuring means and specifying the contents of processing for the defective part; a first holding means for holding positional information and processing designation information of the defective part; and searching for a position on the chip according to the positional information, and performing physical processing on wiring, electrodes, etc. at the position according to the processing designation information. a processing means, a second holding means for holding information on the processed position and processing details, searching for a specific part on the chip according to the processed position information, measuring the electric potential of the specific part, and processing it; A testing device for a semiconductor integrated circuit, comprising: verification means for verifying chip operation associated with the chip operation.