JPH04256179A - Logic verification device - Google Patents

Abstract

PURPOSE:To prevent the verification omission of a design error in a logic circuit. CONSTITUTION:A cover ratio measurement means 1 measures a cover ratio as the circuit model verification degree of an input pattern based on all signal. state value information 5 obtained as the simulating result of a logic circuit model concerning the input pattern. A fixed relation signal retrieving means 2 sequentially retrieves a signal relating to a fixed signal from fixed value signal information 7 generated by the cover ratio measurement means 1 and circuit information 11 of the logic circuit model to the input side and generates fixed relation signal information 8 being the input signal which has fixed signal- influence. A pattern generating means 3 generates an all input pattern 9 which is covering and is possible to be set as against fixed relation signal information 8. A simulation means 4 simulates the logic circuit through the use of the input pattern 9 and outputs partial circuit signal state value information 10.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification device.

0002

[Prior Art] A conventional logic verification device performs simulation by inputting a test pattern to a logic circuit model to be verified, and then analyzes the logic circuit model based on the discrepancy between the state value and the expected value, which is the simulation result. A design error was detected.

0003

[Problems to be Solved by the Invention] The conventional logic verification device described above performs simulation by inputting a test pattern to the logic circuit model to be verified, and compares the state value that is the result of the simulation with the expected value. However, it was difficult to check the comprehensiveness of the simulation for the logic circuit model to be verified, so if there is an unverified circuit part that has not been verified, However, there is a drawback that verification cannot be performed again, resulting in failure to detect errors in the design of the logic circuit.

0004

[Means for Solving the Problems] The logic verification device of the present invention calculates the coverage rate as a circuit model verification degree of an input pattern based on state value information of all signals obtained as a result of simulating a logic circuit model for an input pattern. A coverage measurement means to be measured, and signals related to the fixed signal are sequentially searched on the input side from the fixed signal information created by the coverage measurement means and the circuit information of the logic circuit model, and an input signal that affects the fixed signal is searched. fixed-related signal search means for creating certain fixed-related signal information; pattern generation means for creating a comprehensive all input pattern that can be set for the fixed-related signal information created by the fixed-related signal search means; and a simulation means for simulating a logic circuit model using the input pattern created by the generation means.

[0005]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

[0007] The coverage measuring means 1 determines, based on the total signal state value information 5 obtained as a result of the simulation, that signals whose state values are fixed as simulation results throughout all the simulated patterns are Calculate the percentage of all signals in the simulated circuit as the coverage rate of all simulated patterns,
A partial circuit signal state value obtained as a result of creating a signal name with a fixed state value as fixed signal information 7 and simulating the partial circuit from the input signal to the fixed signal that affects the fixed signal. Based on information 10,
The ratio of signals whose state value is fixed as a simulation result to all signals in the simulated circuit through all the simulated patterns is calculated as the coverage rate of all the simulated patterns, and the state value is The fixed signal name is created as completely fixed signal information 6.

The fixed related signal search means 2 sequentially searches for fixed signals on the input side based on the fixed signal information 7 and the circuit information 11 of the logic circuit model, and identifies signals on the input side that affect the fixed signals as fixed related signals. Create as information 8.

The pattern generating means 3 uses an exhaustive pattern that can be set for the fixed signal based on the fixed related signal information 8 in order to simulate the partial circuit from the input signal to the fixed signal that affects the fixed signal. All patterns are created as input patterns 9.

The simulation means 4 then sets an input pattern 9 for the fixed-related signal information 8, simulates the partial circuit from the input signal to the fixed signal that affects the fixed signal, and calculates the simulated part. The state values of all the signals in the circuit are created as partial circuit signal state value information 10.

Next, the operation of this embodiment will be explained using the example circuit diagram shown in FIG. 2 and the information flow chart shown in FIG. 3.

In FIG. 2, a to f represent elements, and A to H and P to S represent signals connected between the elements.

In FIG. 3, 12 represents all signal state value information indicating the state values of all signals as a result of simulation for the logic circuit model, and 13 indicates that the state values of all signals were fixed. Represents fixed signal information indicating a signal, 1
4 represents circuit information indicating the connection relationships of all signals and elements in the logic circuit model, 15 represents fixed related signal information indicating input signals that affect fixed signals, and 16 indicates coverage that can be set for fixed related signals. 17 represents the partial circuit signal state indicated by the fixed signal as a result of setting the input pattern, which is the comprehensive total pattern, to fixed related signals and performing simulation on the partial circuit. 18 represents complete fixed signal information indicating a signal whose state value is still fixed as a result of setting an input pattern that is a comprehensive all pattern among fixed signals and performing a simulation. . Further, 19 is a coverage rate measuring means, 20 is a fixed related signal searching means, 21 is a pattern generating means, and 22 is a simulation means.

First, the all signal state value information 12 holds the state values taken by all signals in the circuit for each input pattern as a result of simulating the circuit shown in FIG. "P (0, 0, 0, ... 0)" is the result of a simulation with the signal P setting the first pattern, which takes the state value "0", and a simulation with the second pattern set. As a result, the state value is "0", and as a result of setting the third pattern and performing the simulation, the state value is "0", and it is shown that this will be followed in sequence from now on.

The coverage rate measuring means 19 measures the coverage rate as a circuit model verification degree of all the set patterns based on the total signal state value information 12, and at the same time measures the coverage rate as a circuit model verification level of all set patterns based on the total signal state value information 12. Fixed signal information 13 indicating signals that were fixed throughout is created. That is, “P(0, 0, 0,...0
)", we recognize that the state value of signal P is only "0", and from "Q(1,1,0,...0)", we recognize that the state value of signal Q is "0". It recognizes that the state value of signal R is only “1” from “R (1, 1, 1, ... 1)”, and “S (0, 1, 0, ... 1)", it is recognized that the state value of the signal S is both "0" and "1", and the fixed signal information 13 is "P", " R”
Create.

Then, the fixed related signal search means 20 searches circuit information indicating connection relationships between all signals and elements in the circuit model shown in FIG. 2 for each of "P" and "R" in the fixed signal information 13. 14 is used to sequentially search on the input side and create fixed related signal information 15 indicating input side signals that influence each of "P" and "R" in the fixed signal information 13. That is, input signal D and signal E to element a,
Circuit information 14 indicating that signal P and signal S are output
"a-P, S-D, E" (hereinafter referred to as "a-P, S-D, E") in
is obtained. Furthermore, the circuit information 14 is searched based on the signal D, and the signals A and B are obtained as input signals related to the signal D by "b-D-A, B" in the circuit information 14.

Further, the circuit information 14 is searched based on the signal E, and the signal C is obtained as an input signal related to the signal E based on "c-E-C" in the circuit information 14. In this way, signals A, B, and C are obtained as input signals that affect signal P whose state value is fixed, and "P-A, B, C"
Fixed related signal information 15 is created. Similarly, signals F and G are obtained as input signals that affect signal R whose state value is fixed, and fixed related signal information 15 called "R-F, G" is created.

Then, the pattern generating means 21 generates all exhaustive patterns for input signals that affect the fixed signals in the fixed related signal information 15, and creates an input pattern 16. That is, signals A, B, and C, which are input signals related to fixed signal P, have state values of 0, 0, and 0, respectively.
"(A, B, C) = (0, 0,
0)'', and similarly, (0, 0, 1), (0, 1, 0)
, (0,1,1), (1,0,0), (1,0,1),
Eight input patterns 16 are created (1, 1, 0), (1, 1, 1), and for signals F and G, which are input signals that affect the fixed signal R, (0, 0), (0,1
), (1,0), (1,1), four input patterns 16 are created.

Then, by using the input pattern 16 and the fixed-related signal information 15, comprehensive all patterns are set for the input signals that affect the fixed signal, and all patterns from the input signal that affects the fixed signal to the fixed signal are set. Regarding the partial circuit,
A simulation is performed by the simulation means 22. As a result, when each pattern is set and a simulation is performed, the state values taken by the fixed signals P and R are sequentially saved to create partial circuit signal state value information 17.

That is, as a result of performing a simulation by setting the first pattern for signals A, B, and C, the state value of signal P is "1", and by performing a simulation by setting the second pattern, the result is “1” is the result of the simulation with the 3rd pattern set, “0” is the result of the simulation with the 4th pattern set, “0” is the result of the simulation with the 5th pattern set is “1”,
The result of running a simulation with the 6th pattern set is "1", the result of running the simulation with the 7th pattern set is "1", and the result of running the simulation with the 8th pattern set is "1". “P(1,
1, 1, 0, 1, 1, 1, 1)" is created.Similarly, the results of a simulation were performed by setting four exhaustive patterns for signals F and G. , "R (0, 0, 0, 0)" indicating the state value that signal R takes.
The partial circuit signal state value information 17 is created.

[0021] Then, the coverage rate measuring means 19 refers to the partial circuit signal state value information 17, searches for signals whose state values are still fixed as a result of comprehensive simulation using all patterns, and searches for signals whose state values are still fixed. Create 18. That is, for signal P, the state value is both "0" and "1" from "P (1, 1, 1, 0, 1, 1, 1, 1)" in the partial circuit signal state value information 17. Recognizing that the state value is only "0" for the signal R from "R (0, 0, 0, 0)", it sets "R" as the complete fixed signal information 18. Create.

[0022]

[Effects of the Invention] As explained above, the present invention detects a signal whose state value is completely fixed as a result of logic verification, and re-simulates the unverified circuit portion using all comprehensive patterns. This has the effect of preventing failure to verify design errors in logic circuits.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing an object of logic verification.

FIG. 3 is a flowchart showing the flow of information when performing logic verification and detecting a signal whose state value is completely fixed.

[Explanation of symbols]

1 Coverage rate measurement means 2 Fixed related signal search means 3 Pattern generation means 4 Simulation means

Claims (1)

[Claims] 1. Coverage rate measuring means for measuring a coverage rate as a degree of circuit model verification of an input pattern based on state value information of all signals obtained as a result of simulating a logic circuit model for the input pattern; A fixed-related signal search that sequentially searches for signals related to the fixed signal on the input side from the fixed signal information created by the means and the circuit information of the logic circuit model, and creates fixed-related signal information that is an input signal that affects the fixed signal. means, a pattern generating means for creating a comprehensive all input pattern that can be set for the fixed related signal information created by the fixed related signal searching means, and a logic generating means using the input pattern created by the pattern generating means. A logic verification device comprising a simulation means for simulating a circuit model.