JPH04254774A - Tester for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To accurately diagnose the rising and falling characteristics of the output signals of drivers. CONSTITUTION:A switching section is provided for sending the output signal of each driver 1 to a rising/falling time measuring section 6. The section 6 incorporates comparators 7 and 8 which measure the time until one voltage level is reached on the basis of the other voltage level with respect to arbitrary two voltage levels of the output signals, delay circuit 9, and data hold circuit 10. In addition to the section 6, a discrimination circuit section 11 is provided for discriminating the outputted results of the section 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a testing device (IC tester) for semiconductor integrated circuit devices.

0002

[Prior Art] A conventional IC tester uses an IC under test (hereinafter referred to as DUT).
The electrical characteristics of the DUT are tested by applying a power supply voltage or signal to the DUT and comparing the output signal from the DUT with an expected value. At this time, the signal applied to the DUT is generated by a driver in the pin electronics section inside the IC tester, but these circuit characteristics or signal propagation characteristics are not necessarily the same for each tester pin. , the rise and fall characteristics of the output signal of the driver are different. For this reason, the rise of the driver output signal,
It is necessary to diagnose whether the falling characteristic satisfies predetermined specifications. The diagnosis method is as shown in FIG. 4 (only the rising edge of the signal is shown. Only the rising edge will be explained below). , t2 using a comparator inside the pin electronics or a reference comparator inside the IC tester, or
It was found by step search, and the rise characteristics were diagnosed based on the time difference between t1 and t2.

0003

[Problems to be Solved by the Invention] In the conventional IC tester described above, according to the method for diagnosing the rise and fall characteristics of the output signal of the driver, the times t1 and t2 are determined by binary search or step search. It is necessary to repeat the process of outputting the signal, and for this reason, as shown in FIG.
-t23) timing errors occur, and pin electronics errors make it impossible to accurately diagnose the rise and fall characteristics of the output signal of the driver.

0004

[Means for Solving the Problems] The configuration of the IC tester of the present invention includes a switching section for sending the output signal of each driver to a rise/fall time measuring section, a comparator, a delay circuit, and a data holding circuit. It is characterized by having a measuring section and a determination circuit section that determines the output result of the time measuring section.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an IC tester according to a first embodiment of the present invention.

In FIG. 1, the present embodiment includes a driver 1, a comparator 2, a waveform forming section 3, a switching section 4,
It is configured to include a timing generation section 5, a time measurement section 6, comparators 7 and 8, a delay circuit 9, a data holding circuit 10, and a determination circuit section 11.

FIG. 2 is a timing diagram showing the signals of each part when the rise characteristic of the driver output signal in FIG. 1 is good, and FIG. 3 is a timing diagram showing the signals of each part when the rise characteristic of the driver output signal in FIG. 1 is not good.

[0008] Hereinafter, only the case of rising will be explained.

In FIGS. 1 to 3, a control section (not shown) causes the switching section 4 to select the signal path of the driver 1 to be diagnosed, and also causes the timing generation section 5 to select the rising and rising edges of the signals of the driver 1. Start signal (ta,
ta') is sent. The timing generating section 5 sends a reset signal (tb, tb') to the time measuring section 6 and the measuring circuit section 10.
) and set it to the initial state. The timing generator 5 also sends waveform forming signals (tc, tc
'), the waveform forming section 3 causes the driver 1 to generate a signal, and causes the time measuring section 6 to send out the signal via the switching section 4. Comparator 8 compares signal levels (TL) and sends comparison signals (td, td') to the delay circuit. The comparator 7 compares the signal levels (TH) and sends comparison signals (te, te') to the data holding circuit 10. The delay circuit is configured in advance to determine the rise time of driver 1 (from VL to V
The signal from the comparator 8 is set to be delayed by a predetermined time (up to H). Data holding circuit section 10
The comparison signal of the comparator 7 is held as the comparison signal (tf, tf') of the comparator 8 delayed by the delay circuit 9, and the held data is sampled (tg, tf') in the judgment circuit 11.
tg').

In the case of FIG. 2, since the rise time of the output signal of the driver 1 is within the predetermined time, the comparison signal of the comparator 7 is held at a high level (“H”).
In the case of FIG. 3, the rise time of the output signal of the driver 1 deviates from the predetermined time, so the comparison signal of the comparator 7 is held at a low level (“L”).

Next, an IC tester according to a second embodiment of the present invention will be explained.

As a second embodiment, when the rise time of the output signal of the driver 1 is fast, a capacitor circuit is provided in the path between the switching unit 4 and the comparators 7 and 8 to slow the rise of the signal. This can be realized by the delay circuit 9 having delay characteristics corresponding to the capacitance.

The above-mentioned embodiment focused on diagnosing the rising characteristic of a signal, but if the connections of the comparator for TL level comparison and the comparator for TH level comparison are reversed, it is also possible to diagnose the falling edge of the signal. It is. Furthermore, it is also possible to realize an IC tester having two time measuring sections capable of diagnosing both rising and falling edges.

The IC tester of this embodiment measures the time required to reach the other voltage level at any two voltage levels of the output signal of each driver circuit section, using one voltage level as a reference. By generating a signal once, it is possible to accurately diagnose the rise and fall characteristics of the driver's output signal.

[0015]

As explained above, the IC tester of the present invention includes a switching section for sending the output signal of each driver to the rise/fall time measuring section, two pairs of comparators,
By having a time measurement section having a delay circuit and a data holding circuit, and a judgment circuit section that judges the output result of the time measurement section, one voltage level can be determined from any two voltage levels of the output signal of each driver. By measuring the time it takes to reach the other voltage level based on the voltage level, it is possible to accurately diagnose the rise and fall characteristics of the output signal of the driver by generating the signal once.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an IC tester according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing good operating waveforms of the embodiment of FIG. 1;

FIG. 3 is a timing diagram showing an unfavorable state of the operating waveforms of the embodiment of FIG. 1;

FIG. 4 is a characteristic diagram showing a state in which the rise characteristic of the output signal of a driver of a conventional IC tester is diagnosed.

FIG. 5 is a characteristic diagram showing a timing error of an output signal due to jitter in the driver system.

[Explanation of symbols]

1 Driver 2, 7, 8 Comparator 3 Waveform forming section 4 Switching section 5 Timing generation section 6 Time measurement section 9 Delay circuit 10 Data retention circuit 11 Judgment circuit section

Claims (1)

[Claims] 1. A switching section is provided for sending an output signal of each driver to a rise/fall time measuring section, and the time measuring section uses one of the two arbitrary voltage levels of the output signal as a reference, A semiconductor integrated circuit device comprising a comparator, a delay circuit, and a data holding circuit for measuring the time until reaching the other voltage level, and a determination circuit section for determining the output result of the time measuring section. Test equipment.