JPH04254746A - Inspecting device of brightness - Google Patents

Abstract

PURPOSE:To increase a processing speed of inspection of the brightness of the surface of a body to be inspected without causing an increase in the capacity of a memory and complexity of a circuit construction, by utilizing the averaging of the lightness of each pixel in place of the brightness of each pixel of a reference image of the body to be inspected. CONSTITUTION:A defect emphasizing circuit 80 stores, as an image to be inspected, an image of the surface of a body to be inspected having two different brightness surface parts, which is picked up by a TV camera Tc, accumulates and counts the lightness and the number of pixels of the picked-up image for each pixel belonging to each pixel region corresponding to each different brightness surface part, in response to specification of an address by each pixel of a reference image stored in one of frame memories Mf1 to Mfn, and makes them be two brightness cumulative data and two-pixel count data. The circuit conducts divisions of each of the two-lightness cumulative data by each of the two-pixel count data, so as to make them be division data respectively, computes a lightness difference between the lightness of each pixel of the image to be inspected and each division data for each pixel region, and makes a defect part of the image to be inspected be lightness defect data on the basis of each lightness difference.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to the surface of the dial of a meter,
The present invention relates to a brightness inspection device suitable for inspecting the brightness of the surface of various objects to be inspected, such as the surface of an LSI wafer, by using image processing.

0002

[Prior Art] Conventionally, in this type of brightness testing device,
The surface of the object to be inspected under appropriate illumination is photographed as a photographed image by a television camera, and the brightness of this photographed image is compared for each pixel with the brightness of a reference image of the surface of the object to be examined, There is a method in which the suitability of the surface of the object to be inspected is inspected based on the respective brightness differences.

0003

[Problem to be Solved by the Invention] However, in such a configuration, there is generally a relative brightness difference between the photographed image and the reference image due to variations in the brightness of the illumination and variations in the surface of the object to be inspected. Because the values often change, differences in brightness may occur even on the surfaces of objects to be inspected that you would like to judge to be exactly the same.
As a result, it becomes necessary to perform correction to eliminate this brightness difference. In such a case, if there are multiple image parts to be corrected in a single captured image, the amount of correction is calculated for each image part in turn, and multiple corrected captured images are created from the single captured image according to each of these correction amounts. In addition, each of these corrected photographed images is compared with a reference image to determine whether the brightness is appropriate. This means that a complicated image processing process is required to determine whether the brightness of the surface of the object to be inspected is appropriate. As a result, not only the processing speed for inspecting the brightness of the surface of the object to be inspected decreases, but also
As the capacity of the memory increases, the circuit configuration becomes more complicated, leading to higher costs. In contrast, the present inventors confirmed the following. For example, the brightness of each pixel in the corresponding pixel area of the photographed image and the reference image is respectively Tsi and Msi, the corrected brightness of the brightness Tsi of each pixel of the photographed image is Tsai,
The number of pixels of the captured image belonging to the corresponding pixel area is N,
If Fi is the difference in brightness between each corresponding pixel between the defective pixel portion of the photographed image and the corresponding pixel portion of the reference image, the following Equations 1 and 2 hold true. However, i=1, 2,...,N
shall be.

[Math. 1] Tsai=Tsi-(1/N)・{(
Ts1-Ms1)+(Ts2-Ms2)+...
+(TsN-MsN)}

[
Equation 2: Fi=Tsai-Msi Here, if Mfix is the fixed value of the brightness of each pixel of the reference image in the above-mentioned corresponding pixel area, the following Equations 3 and 4 hold true.

[Math. 3] Tsai=Tsi-(1/N)・
(Ts1+Ts2+…+TsN)+Mfix

[Math 4] F
i=Tsai-Msi =Tsi-(1/N)・(Ts1+Ts2+...+TsN
) According to this number 4, Tsi and (1/N)・
(Ts1+Ts2+...+TsN), that is, Tsi
It can be seen that Fi is determined by the brightness difference between Tsi and the average value of each Tsi of the corresponding pixel area. In such case,
Since the second equation of Equation 4 does not involve the brightness Msi of the pixels of the reference image, it is understood that there is no need to take into account the variation in the brightness Msi of the pixels of the reference image when determining the brightness difference Fi. The above holds true for all corresponding pixels in the photographed image and the reference image. Based on the above-mentioned recognition, the present invention effectively utilizes the average brightness of each pixel of a photographed image in place of the brightness of each pixel of a reference image in a brightness inspection device. The purpose is to increase the processing speed for inspecting the brightness of the surface of an object to be inspected without increasing the memory capacity or complicating the circuit configuration.

0004

[Means for Solving the Problems] In order to solve the above problems, the configuration of the present invention is to image a surface of an object to be inspected having at least first and second surface portions having different brightnesses under appropriate illumination. a photographic image storage means for storing the photographed image as a test image; a reference image storage means for storing a normal image of the surface as a reference image; For each pixel belonging to one pixel area and a second pixel area corresponding to the second surface portion, the brightness of each pixel of the photographed image is accumulated according to the address designation by each pixel of the reference image, and the brightness of each pixel of the photographed image is accumulated and a brightness accumulating means for generating brightness cumulative data, and counting the number of each pixel of the photographed image according to address designation by each pixel of the reference image for each pixel belonging to the first and second pixel areas, respectively; pixel counting means for obtaining second pixel counting data; and pixel counting means for obtaining second pixel counting data;
division means for dividing by the pixel count data and dividing the second lightness cumulative data by the second pixel count data to obtain first and second divided data, respectively; The brightness difference between the brightness of each pixel and the first division data and the brightness difference between the brightness of each pixel of the test image belonging to the second pixel area and the second division data are calculated, and each of these and brightness difference calculation means for calculating the defective portion of the image to be inspected as brightness defect data based on the brightness difference.

[0005]

[Operation] By configuring the present invention as described above, when the surface of the object to be inspected is photographed as an image under appropriate illumination by the photographing means, the photographed image storage means stores the photographed image as an image. The brightness accumulating means stores the photographed image as a test image, and the brightness accumulating means stores the brightness of the photographed image for each pixel belonging to the first and second pixel areas, in accordance with the address designation by each pixel of the storage reference image of the reference image storage means. The brightness of each pixel is accumulated as first and second brightness cumulative data, and the pixel counting means performs addressing by each pixel of the storage reference image for each pixel belonging to the first and second pixel areas, respectively. Accordingly, the number of each pixel of the photographed image is counted as first and second pixel count data, and the dividing means
dividing the brightness cumulative data by the first pixel count data and dividing the second brightness cumulative data by the second pixel count data to obtain first and second divided data, respectively, and the brightness difference calculation means, Said first
A brightness difference between the brightness of each pixel of the test image belonging to the pixel region and the first division data, and a difference between the brightness of each pixel of the test image belonging to the second pixel region and the second division data. The brightness difference between them is calculated, and the defective portion of the image to be inspected is determined as brightness defect data based on these brightness differences.

[0006]

Effects of the Invention As described above, based on the calculation of each division data based on each brightness cumulative data and each pixel count data as described above, the brightness difference calculation means calculates the brightness difference. Instead of the brightness of each pixel of the test image and the corresponding brightness of each pixel of the reference image, either the brightness of each pixel of the test image and the corresponding division data (i.e., the The average value of the brightness of each pixel of the test image in any of the above pixel regions) is used.
Even if the brightness of each pixel of the photographed image or the reference image varies within the first or second pixel region, it is possible to form a plurality of corrected reference images as described in the above-mentioned problem to be solved by the prior art. As a result, the brightness of the object to be inspected can be quickly inspected without unnecessary increase in storage capacity and without complicating the image processing circuit configuration. In addition, as mentioned above, the reference image is only used for addressing, so as in the past, the brightness of each pixel of the reference image is compared with the brightness of each pixel of the test image. There is no need to manage variations.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a brightness testing device according to the present invention. This brightness inspection device has a television camera Tc, and this television camera Tc detects a plurality of different parts 12 (squares 13 and 13 in FIG. 4) of a dial 11 of a speedometer 10 (see FIG. 4). (Examples are shown in the enclosed area) are photographed based on their brightness distribution, and in response to the fall of each screen synchronization signal from the screen synchronization signal generation circuit 40, which will be described later, each of these images is photographed. The photographed images are output as serial data (hereinafter referred to as photographed image data) for each photographed image. However, dial 11
The background portion 11a, scale portion 11b, and character portion 11c are printed in different colors. This means that the background portion 11a, the scale portion 11b, and the character portion 11c have different brightness from each other. Therefore, each photographed image data includes the background part 11a, the scale part 11b, and the character part 1.
It is specified by one of the brightness values of 1c. The reset switch SW generates a reset signal by its reset operation. The A-D converter 20 converts each photographed image data from the television camera Tc into
Each pixel synchronization clock signal from the pixel synchronization clock circuit 30 is sequentially responded to and converted into digital data (hereinafter referred to as image data T(x,y)). However, T(x,
y), (x, y) represents the position coordinates of each pixel of each of the captured images. Therefore, T(x,y) is the coordinate (x
, y). The pixel synchronization clock circuit 30 repeatedly generates a pixel synchronization clock signal at a predetermined oscillation frequency. The screen synchronization signal generation circuit 40 is put into operation at the same time as the brightness inspection device starts operating, and counts each pixel synchronization clock signal from the pixel synchronization clock circuit 30, and counts each pixel synchronization clock signal by a predetermined period (for example, 33 (ms)).
A screen synchronization signal is repeatedly generated for each count corresponding to c).

[0008] The screen counter 50 has a reset switch S.
It is reset in response to a reset signal from W and counts each screen synchronization signal sequentially generated from the screen synchronization signal generation circuit 40. The pixel counter 60 is repeatedly reset in response to the fall of each screen synchronization signal from the screen synchronization signal generation circuit 40, counts each pixel synchronization clock signal from the pixel synchronization clock circuit 30, and calculates each count result as follows. It generates any one of the first to nth address signals necessary to designate any one of the frame memories Mf1 to Mfn. The decoder 70 decodes the count value of the screen counter 50,
According to this decoding result, each frame memory Mf1 to Mfn
A decode signal representing one of these is generated and applied to one of the enable terminals of each frame memory Mf1 to Mfn. Each of the frame memories Mf1 to Mfn stores in advance a normal reference image of each portion to be inspected 12 of the dial 11. Therefore, one of the frame memories Mf1 to Mfn is selected by the decode signal from the decoder 70, and the defect highlighting circuit 80 uses the reference image as serial data (hereinafter referred to as reference image data M(x, y)).
(See Figures 1 to 3). However, in M(x,y), (x,y) is the same as in the case of T(x,y) described above, and M(x,y) corresponds to T(x,y). Therefore, M(x, y) is the coordinate (x
, y).

The defect highlighting circuit 80, as shown in FIG.
It has a clock circuit 81a, and this clock circuit 8
1a repeatedly generates a clock signal at a predetermined oscillation frequency. The n-bit counter 81b is repeatedly reset in response to each screen synchronization signal from the screen synchronization signal generation circuit 40, and counts the clock signals sequentially generated from the clock circuit 81a. A binary signal is repeatedly generated from the output terminal QMSB corresponding to . The logic circuit 82 has an OR gate 82a, and this OR gate 82a receives each screen synchronization signal from the screen synchronization signal generation circuit 40 or the pixel synchronization clock circuit 3.
The inverted signal of each pixel clock signal from 0 is the gate signal G.
Occurs as a. The AND gate 82b is the counter 8
Each clock signal from the clock circuit 81a is sequentially outputted to the OR gate 82d under the high level of the inverted binary signal from 1b and the high level of each screen synchronization signal from the screen synchronization signal generation circuit 40. AND gate 82c
Under the high level of each screen synchronization signal from the screen synchronization signal generation circuit 40, the inverted signals of each pixel synchronization clock signal from the pixel synchronization clock circuit 30 are sequentially applied to the OR gate 82.
Output to d. The OR gate 82d has both AND gates 8
Either of the output signals from 2b and 82c is generated as the gate signal Gb. The AND gate 82e sequentially outputs each binary signal from the counter 81b to the OR gate 82g under the high level of each screen synchronization signal from the screen synchronization signal generation circuit 40. The AND gate 82f sequentially outputs an inverted signal of each pixel synchronization clock signal from the pixel synchronization clock circuit 30 to the OR gate 82g under the low level of each screen synchronization signal from the screen synchronization signal generation circuit 40. The OR gate 82g is connected to both AND gates 82e and 82f.
generates one of the output signals from the gate signal Gc as the gate signal Gc. The D-type flip-flop 82k is reset in response to the low level of each screen synchronization signal from the screen synchronization signal generation circuit 40, and is reset in response to each binary signal from the counter 81b. DC voltage (+
Vd) is generated at its inverted level from the inverted output terminal Qneg as an output signal Gd. The AND gate 82h sequentially ORs each clock signal from the clock circuit 81b under the high level of each binary signal from the counter 81b and the high level of each screen synchronization signal from the screen synchronization signal generation circuit 40. Output to. OR gate 82
i generates an inverted signal of each screen synchronization signal from the screen synchronization signal generation circuit 40 or each output clock signal from the AND gate 82h as a gate signal Ge. OR gate 8
2j generates each screen synchronization signal from the screen synchronization signal generation circuit 40 or each pixel clock signal from the pixel synchronization clock circuit 30 as a gate signal Gf.

The 3-state buffer 83 is the logic circuit 8
In response to the low level of the output signal Gd from the second flip-flop 82k, a low level output from the flip-flop (not shown) is given to both memories 83e and 83f, and the stored contents of these memories 83e and 83f are changed. Clear. However, the flip-flop outputs the inverted output when the screen synchronization signal from the screen synchronization signal generation circuit 40 is at high level to the three-state buffer 83 as a low level output, and also outputs the inverted output from the screen synchronization signal generation circuit 40 to the three-state buffer 83. An inverted output when the signal is at a low level is output as a high level output to an adder 83b, which will be described later. The adder 83a receives the gate signal Gf from the OR gate 82j,
That is, in response to each pixel clock signal sequentially generated from the pixel synchronization clock circuit 30 under the low level of the screen synchronization signal from the screen synchronization signal generation circuit 40, each test image data T( x, y), that is, the brightness of the pixel at each coordinate (x, y) is sequentially added to the latch data at the current stage of the latch 83c. The latch 83c responds to an inverted signal of each pixel clock signal sequentially generated from the pixel synchronization clock circuit 30 under the low level of the gate signal Ga from the OR gate 82a, that is, the screen synchronization signal from the screen synchronization signal generation circuit 40, The output stored brightness cumulative data from the memory 83e is latched repeatedly. memory 8
After clearing, the digital switch 8 is turned on under the low level of the gate signal Gb from the OR gate 82d.
5a, each reference image data M(x, y) sequentially output from one of the frame memories Mf1 to Mfn is received as an address signal, and each addition from the adder 83a specified by each of these address signals is performed. The data is transferred to the background part 11a, scale part 11b and character part 11c of the dial 11.
Each pixel region (hereinafter, each pixel region R1
, R2, R3) and accumulate the first, second and third
is stored as cumulative brightness data. On the other hand, the memory 83e
Under the low level of the gate signal Gc from the OR gate 82g, each reference image data M(x, y) sequentially output from any of the frame memories Mf1 to Mfn is sent to an address signal via the digital switch 85a. Then, the brightness cumulative data (that is, the first, second, or third brightness cumulative data) to which the pixel specified by each address signal belongs is read out and output to the latch 83c and the divider 84.

The adder 83b responds to each pixel clock signal sequentially generated from the pixel synchronization clock circuit 30 under the low level of the gate signal Gf from the OR gate 82j, that is, the screen synchronization signal from the screen synchronization signal generation circuit 40. , the high-level output from the flip-flop, that is, the digital value "1", is repeatedly added to the latch data at the current stage of the latch 83d. The latch 83d responds to an inverted signal of each pixel clock signal sequentially generated from the pixel synchronization clock circuit 30 under the low level of the gate signal Ga from the OR gate 82a, that is, the screen synchronization signal from the screen synchronization signal generation circuit 40, The output storage count data of the memory 83f is repeatedly latched. After the memory 83f is cleared, each reference image data M(x . It is stored as pixel count data of 3. On the other hand, the memory 83f receives each reference image data M (x, y ) as an address signal, the pixel count data (i.e., the first, second, or third pixel count data) to which the pixel specified by each address signal belongs is read out, and the latch 83d and the divider 8
Output to 4.

The divider 84 divides the first accumulated brightness data from the memory 83e by the first pixel count data from the memory 83f to obtain first division data, and divides the first accumulated brightness data from the memory 83e by the first pixel count data from the memory 83f.
The brightness cumulative data is divided by the second pixel count data from the memory 83f to obtain second division data, and the third brightness cumulative data from the memory 83e is divided by the third pixel count data from the memory 83f to obtain third division data. Sequential memory 86 as data
Output to. The digital switch 85a is alternately switched to a low level state L or a high level state H in response to a screen synchronization signal from the screen synchronization signal generation circuit 40. Each reference image data M(x,
y) is given to each memory 83e, 83f as an address signal. The frequency divider 85b sequentially responds to each screen synchronization signal from the screen synchronization signal generation circuit 40, divides the frequency of each of these screen synchronization signals by 1/2, and sequentially generates a divided signal. The counter 81b counts the clock signals sequentially generated from the clock circuit 81a, and uses these counting results as address signals for both digital switches 85a and 86a.
granted to. The digital switch 86a is switched to a low level state L (or a high level state H) in response to each screen synchronization signal from the screen synchronization signal generation circuit 40. Thus, this digital switch 86a, in its high level state H, sequentially applies each address signal from the counter 81b to the memory 86, while, in its low level state L, sends the address signals from both frames via the digital switch 88c. Storage data output from either memory Md1 or Md2 is applied to memory 86 as an address signal. The memory 86 stores an OR gate 82i under the high level of each screen synchronization signal from the screen synchronization signal generation circuit 40.
Under the generation of each gate signal Ge from , the first, second, or third divided data from the divider 84 is sequentially stored according to the designation by each address signal from the counter 81b via the digital switch 86a. Further, this memory 86 is connected to a digital switch 88c under the low level of each screen synchronization signal from the screen synchronization signal generation circuit 40.
According to the designation by each output data from either of the frame memories Md1 and Md2 via the frame memories Md1 and Md2, the first, second, or third stored division data related to this designation is sequentially output to the memory 89.

Digital switch 88a is frequency divider 8
5b, the reference image data M (x, y ) in the low level state L or high level state H, sequentially and alternately, the frame memory Md
1 or output to frame memory Md2. The digital switch 88b is alternately switched to a low level state L (or a high level state H) in response to each frequency division signal sequentially generated from the frequency divider 85b, and the test image from the A-D converter 20 is switched to a low level state L (or a high level state H). Data T(x, y) is sequentially and alternately stored in the frame memory M in a low level state L or a high level state H.
d3 or frame memory Md4. Both frame memories Md1 and Md2 are connected to a digital switch 88a.
The respective output data from are sequentially and alternately stored. Both frame memories Md3 and Md4 are digital switches 88b
The respective output data from are sequentially and alternately stored. The digital switch 88c is alternately switched to a low level state L (or a high level state H) in response to each frequency division signal sequentially generated from the frequency divider 85b, and the frame memory Md
1 or the data stored in the frame memory Md2 is output to the digital switch 86a in a low level state L or a high level state H. Digital switch 8
8d is alternately switched to a low level state L (or a high level state H) in response to each frequency division signal sequentially generated from the frequency divider 85b, and the data stored in the frame memory Md3 or the data stored in the frame memory Md4 is is output to the memory 89 in a low level state L or a high level state H. However, when both digital switches 88c and 88d are both in the high level state H (or low level state L), both the above-mentioned digital switches 88a and 88b are both in the low level state L (or high level state H). . The memory 89 has a subtraction function, and the memory 89 calculates and stores the subtraction difference between the output data from the digital switch 88d and the output data from the memory 86. The D-A converter 90 receives data from the memory 89 in response to each pixel clock signal from the pixel synchronization clock circuit 30 while the screen synchronization signal from the screen synchronization signal generation circuit 40 via the defect highlighting circuit 80 is at a low level. The subtraction difference stored data is sequentially converted into analog data and converted into analog data.
Output to display 100. This display 1
00 is constituted by a television and displays analog data from the DA converter 90.

[0014] In this embodiment configured as above,
When the device of the present invention is in operation, the screen synchronization signal generation circuit 40 repeatedly generates a screen synchronization signal in response to pixel clock signals sequentially generated from the pixel synchronization clock circuit 30. Further, when a reset signal is generated from the reset switch SW, the screen counter 50 is reset and sequentially counts each screen synchronization signal from the screen synchronization signal generation circuit 40. Further, the flip-flop 82k of the logic circuit 82 responds to the counting operation in response to the clock signal from the clock circuit 81a accompanying the reset of the counter 81b, and the gate signal Gd
will occur. When this gate signal Gd falls, the three-state buffer 83 applies its low level output to both memories 83e and 83f in order to clear their respective stored contents. At this time, digital switch 85
a is in the high level state H in response to the screen synchronization signal from the screen synchronization signal generation circuit 40. Therefore, both memories 8
3e and 83f output the respective stored contents from the counter 81b to the low level output from the 3-state buffer 83 based on the designation by each address signal sequentially generated via the digital switch 85a in cooperation with the clock circuit 81a. Clear accordingly.

[0015] Also, under appropriate lighting, a television camera T
When the screen synchronization signal currently being generated from the screen synchronization signal generation circuit 40 falls while photographing one part to be inspected 12 (see FIGS. 4 and 5(A)) of the dial 11 of the speedometer 10 using c. , the photographed image of the inspected part 12 is transferred from the television camera Tc to the A-D converter 2 as photographed image data.
0, which is digitally converted into test image data T(x,y) by this A/D converter 20 and output to the defect image enhancement circuit 80. At this time, in response to the generation of the frequency division signal from the frequency divider 85b accompanying the fall of the screen synchronization signal as described above, both digital switches 88a and 88
Both digital switches 88c and 88d become high level H. Further, it is assumed that the decoder 70 specifies the frame memory Mf1 according to the count value of the screen counter 50. However, this frame memory Mf1 has data in FIGS. 4 and 5 (
It is assumed that the normal image of the inspected portion 12 shown in A) (see FIG. 5(B)) is stored in advance as reference image data M(x, y). Accordingly, the frame memory Mf1 outputs the storage reference image data M(x,y) to the defective image enhancement circuit 80 based on the designation by the decoder 70. In the inspected part 12 shown in FIG. 5(A), the reference numeral 11
d indicates a defective portion in the background portion 11a of the inspected portion 12.

As described above, the test image data T(x,y)
and reference image data M (x, y) are sent to the defect image enhancement circuit 8.
0, the adder 83a controls the A-D converter 20 at the rising edge of the gate signal Gf from the logic circuit 82.
The memory 83e adds the test image data T(x,y) from the latch 83c to the latch brightness cumulative data (currently cleared as described above), and the memory 83e adds the added data to the logic circuit 82. In response to the rising edge of the gate signal Gb generated from Remember. Then, latch 8
3c latches the accumulated lightness data stored in the memory 83e at the rise of the gate signal Ga from the logic circuit 82. Hereinafter, at the rising edge of each gate signal Gf, the rising edge of each gate signal Gb, and the rising edge of each gate signal Ga sequentially generated from the logic circuit 82, the adder 83a performs an addition operation, and the memory 83e performs the first, second, or third Memory function and latch 8 for brightness cumulative data
The storage brightness cumulative data latching action by 3c causes each test image data T(x, y
) and the digital switch 85a in response to address designation by each reference image data M(x,y) from the frame memory Mf1.

On the other hand, at the rising edge of the gate signal Gf from the logic circuit 82, the adder 83b outputs a high level output from the flip-flop, that is, the digital value "1".
The latch count data of the latch 83d (currently cleared as described above) is added to the memory 83f, and the memory 83f adds the added data to the digital switch in response to the rise of the gate signal Gb generated from the logic circuit 82. 85
The data is stored as pixel cumulative data (for example, first pixel cumulative data) under addressing by reference image data M(x,y) from frame memory Mf1 via a. Then, the latch 83d latches the accumulated pixel data stored in the memory 83f at the rise of the gate signal Ga from the logic circuit 82. Hereinafter, at the rising edge of each gate signal Gf, the rising edge of each gate signal Gb, and the rising edge of each gate signal Ga sequentially generated from the logic circuit 82, the addition action by the adder 83b and the memory 83f are performed.
The storage function of the first, second, or third pixel cumulative data by the latch 83d and the latching function of the same pixel cumulative data by the latch 83d are used to store each reference image data M(x, y) from the frame memory Mf1 via the digital switch 85a.
The process is repeated in sequence according to the address specification by . Furthermore, when the digital switch 88a is switched to the low level state L as described above, the frame memory M
d1 is reference image data M from frame memory Mf1
(x, y), and on the other hand, when the digital switch 88b is switched to the high level state H as described above, the frame memory Md3 stores the image data T( x, y).

In this way, a photographed image (see FIG. 5(A)) and a normal image (see FIG. 5(B)) of the inspected part 12 are obtained.
Test image data T(x, y) corresponding to
and storage of the first to third brightness cumulative data and the first to third pixel cumulative data of the reference image data M (x, y), and the test image data T (x, y) and the reference image data M
After the storage of (x, y) is completed, when the screen synchronization signal from the screen synchronization signal generation circuit 40 rises, the digital switch 85a goes to the high level state, and at the same time, the digital switch 86a goes to the high level state H. Then, the memory 83e receives the gate signal Gc from the logic circuit 82.
At the falling edge of , the first, second and third stored brightness cumulative data are sequentially outputted to the divider 84 in accordance with the designation by each address signal from the counter 81b via the digital switch 85a; When the gate signal Gc from the logic circuit 82 falls, the memory 83f operates the counter 81 via the digital switch 85a.
According to the designation by each address signal from b.
and the third stored pixel accumulated data are sequentially output to the divider 84. Then, the divider 84 divides the first stored brightness cumulative data by the first stored pixel count data, divides the second stored brightness cumulative data by the second stored pixel count data, and divides the third stored brightness cumulative data by the first stored pixel count data. 3 divided by the memory pixel count data,
The memory 86 sequentially stores the first, second and third division data.
Output to. Thus, the memory 86 performs the first, second, and third division operations described above at the rising edge of each gate signal Ge from the logic circuit 82, in accordance with the designation by each address signal from the counter 81b via the digital switch 86a. Store data. Thereafter, when the output QMSB of the counter 81b rises, the contents of the memories 83e and 83f are cleared in the same manner as described above.

Furthermore, in the same manner as described above, the television camera Tc
Accordingly, other parts to be inspected 12 of the dial 11 of the speedometer 10 (for example, parts to be inspected 1 shown in FIGS. 4 and 5(A))
When the screen synchronization signal from the screen synchronization signal generation circuit 40 falls, the captured image of the other inspected section 12 is taken as other captured image data from the television camera Tc. It is output to the D converter 20 and converted into other test image data T (x, y
) and output to the defect image enhancement circuit 80. At this time, in response to the generation of the frequency division signal from the frequency divider 85b accompanying the fall of the screen synchronization signal as described above, each digital switch 88a, 88b both becomes a high level state H, while each digital switch 8
8c and 88d both become low level state L. Further, it is assumed that the decoder 70 specifies the frame memory Mf2 according to the count value of the screen counter 50. However, it is assumed that the above-mentioned normal image of the other inspected portion 12 is stored in advance in this frame memory Mf2 as other reference image data M(x, y). However, frame memory M
f2 outputs the storage reference image data M(x, y) to the defect highlighting circuit 80 based on the designation by the decoder 70.

As mentioned above, other test image data T(x,
y) and other reference image data M(x, y) are output to the defect highlighting circuit 80, the adder 83a
At the rise of the gate signal Gf from
The memory 83e adds the latch brightness cumulative data of 3c (currently cleared as described above), and the memory 83e sends the added data to the digital switch 85a in response to the rise of the gate signal Gb generated from the logic circuit 82. Other reference image data M from frame memory Mf2 via
It is stored as other cumulative brightness data (for example, another first cumulative brightness data) under addressing by (x, y). Then, at the rise of the gate signal Ga from the logic circuit 82, the latch 83c latches the other accumulated lightness data stored in the memory 83e. Below, logic circuit 8
The rising edge of each gate signal Gf, the rising edge of each gate signal Gb, and the rising edge of each gate signal G, which occur sequentially from 2.
At the rising edge of A, the addition action by the adder 83a, the storage action of each other first, second, or third brightness cumulative data by the memory 83e, and the latching action of the stored brightness cumulative data by the latch 83c are performed on the subsequent A. - In response to addressing by each other test image data T (x, y) from the D converter 20 and each other reference image data M (x, y) from the frame memory Mf2 via the digital switch 85a, It is repeated in sequence.

On the other hand, at the rising edge of the gate signal Gf from the logic circuit 82, the adder 83b outputs a high level output from the flip-flop, that is, the digital value "1".
The latch count data of the latch 83d (currently cleared as described above) is added to the memory 83f, and the memory 83f adds the added data to the digital switch in response to the rise of the gate signal Gb generated from the logic circuit 82. 85
It is stored as other pixel count data (for example, another first pixel count data) under addressing by other reference image data M(x,y) from frame memory Mf2 via a. Then, the latch 83d activates the memory 83 at the rise of the gate signal Ga from the logic circuit 82.
Latch other stored pixel count data of f. Hereinafter, at the rising edge of each gate signal Gf, the rising edge of each gate signal Gb, and the rising edge of each gate signal Ga sequentially generated from the logic circuit 82, the adder 83b performs an addition operation, and the memory 83f performs an addition operation on each of the other first and second gate signals. Alternatively, the storage action of the third pixel count data and the latching action of the same pixel count data by the latch 83d are used for subsequent addressing by each other reference image data M(x, y) from the frame memory Mf2 via the digital switch 85a. Depending on the situation, the process is repeated in sequence. Furthermore, when the digital switch 88a is switched to the high level state H as described above, the frame memory Md2 is switched to the frame memory Md2.
Store other reference image data M(x,y) from f2;
On the other hand, when the digital switch 88b is switched to the high level state H as described above, the frame memory M
d4 is other test image data T from the A-D converter 20
Store (x, y).

[0022] Furthermore, as mentioned above, a digital switch
Since the digital switch 86a is in the low level state L and the digital switch 88c is in the high level state H, the memory 86 is The memory reference image data M(x,y) of the frame memory Md1 is received as an address signal via each digital switch 88c, 86a, and the first to third divided data are sequentially outputted to the memory 89 and provided as an address. Further, as described above, since the digital switch 88d is in the high level state H, the memory 89 sequentially outputs the stored test image data T(x, y) from the frame memory Md3 via the digital switch 88d. 89 addresses, and each of these test image data T(x
, y) and the above-mentioned first, second, or third division data, and outputs the result. In such case,
The subtraction is performed on the test image data T belonging to the pixel region R1.
(x,y) and the first division data, between the test image data T(x,y) belonging to the pixel region R2 and the second division data, and between the test image data T(x, y) belonging to the pixel region R3.
, y) and the third division data. The memory 89 outputs each subtraction data to the DA converter 90 as data representing a defect emphasized image (hereinafter referred to as defect emphasized image data). In such case,
Then, this DA converter 90 converts the defect emphasis image data from the memory 89 into analog data and outputs it to the display 100 as analog data. Therefore, the display 100 displays the defective portion 11d in the background portion 11a of the portion to be inspected 12 as shown in FIG. 5(C) based on the analog data from the DA converter 90.

As explained above, when inspecting the part 12 to be inspected (see FIG. 5(A)) of the dial 11 for defects, a series of images representing the part 12 to be inspected taken by the television camera Tc are used. Image data T (x, y) is stored in frame memory M
The memory 8 stores the first, second, and third brightness cumulative data for each pixel region R1, R2, and R3 under the address designation using the series of storage reference image data M(x, y) of f1.
3e, and the number of test image data T(x, y) of the same series is stored in each frame memory Mf1 under the address specification by the memory reference image data M(x, y) of the series. Pixel area: 1st, 2nd for each R1, R2, and R3
and the third pixel count data are counted and stored in the memory 83f, and the test image data T(x, y
) is stored in the frame memory Md3, and a series of storage reference image data M(x,y) of the frame memory Mf1 is stored in the frame memory Md1. Next, memory 8
The first, second, and third stored brightness cumulative data of 3e are divided by the first, second, and third stored pixel count data of the memory 83f as first, second, and third divided data by the divider 84, respectively. The first, second, and third division data are stored in the memory 86.
The first, second, and third stored division data of frame memory Md1 are read out and stored in memory 89 under addressing by a series of stored reference image data M(x, y), and are stored in frame memory Md3. Each stored test image data T(x
. The data is displayed on a display 100 via a DA converter 90. In such a case, in the memory 89, the object to be subtracted from each stored test image data T(x,y) of the frame memory Md3 is the first, second, or third stored division data, that is, each test image data T. (
Since the brightness is averaged for each pixel region R1, R2 or R3 of pixel area M(x, y),
It is possible to display a stable defect-enhanced image with high accuracy regardless of the brightness variations in each pixel region R1,
This method eliminates the problem of preparing multiple corrected reference images by correcting the reference image data for each R2 and R3 according to their brightness variations, and also avoids increasing memory capacity and complicating the circuit configuration. The inspected part 12 without inviting
The processing speed for inspecting the brightness of the surface can be increased. Furthermore, as mentioned above, the reference image data is used only for address specification, so even if there is variation in the brightness of each pixel in the reference image data or test image data, it will not be affected by this. As a result, when comparing with the test image data in the memory 89, there is no need to appropriately manage the brightness of each pixel of the reference image, unlike in the conventional case.

In carrying out the present invention, the present invention is not limited to the dial of the speedometer 10, but can be applied to inspecting the quality of the dial surfaces of various instruments, surfaces of LSI wafers having abnormally bright surface parts, etc. applicable.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a logic circuit in the defect highlighting circuit of FIG. 1;

FIG. 3 is a diagram showing the remaining circuit configuration of the defect highlighting circuit.

FIG. 4 is a cutaway front view of the dial of the speedometer.

FIG. 5 is a diagram illustrating a partially enlarged image, a partially enlarged reference image, and a defect highlighting section on the same dial.

[Explanation of symbols]

Mf1 to Mfn, Md1 to Md4...Frame memory, T
c...TV camera, 10...Speedometer, 11...Dial, 11a...Background section, 11b...Scale section, 11c...Character section, 30...Pixel synchronization clock circuit, 40...Pixel synchronization signal generation circuit, 50...Screen counter, 60...pixel counter, 7
0... Decoder, 80... Defect highlighting circuit, 81a... Clock circuit, 81b... Counter, 82... Logic circuit, 83a, 8
3b...Adder, 83c, 83d...Latch, 83e, 83
f, 86, 89...memory, 84...divider, 85a, 86
a, 88a to 88d...digital switch, 85b...frequency divider.

Claims (1)

[Claims] 1. Photographing means for photographing a surface of an object to be inspected having at least first and second surface portions having different brightnesses as an image under appropriate illumination, and storing the photographed image as a test image. a photographed image storage means for storing a normal image of the surface as a reference image; a first pixel region corresponding to the first surface portion and a second pixel region corresponding to the second surface portion. a brightness accumulating means for accumulating the brightness of each pixel of the photographed image according to the address designation by each pixel of the reference image for each pixel belonging to each pixel to obtain first and second brightness cumulative data;
pixel counting means for counting the number of each pixel of the photographed image according to the address designation by each pixel of the reference image for each pixel belonging to the pixel area of the pixel area, and calculating the number of each pixel of the photographed image as first and second pixel count data; a division means that divides the brightness cumulative data by the first pixel count data and divides the second brightness cumulative data by the second pixel count data to obtain first and second divided data, respectively; and the first pixel area. The brightness difference between the brightness of each pixel of the test image belonging to the test image and the first division data, and the brightness difference between the brightness of each pixel of the test image belonging to the second pixel area and the second division data. Brightness difference calculation means for calculating brightness differences and using these brightness differences as brightness defect data for the defective portion of the image to be inspected.