JPH042543Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a receiver for high-definition television signals, and is particularly suitable for decoding a band-compressed high-definition television signal into the original broadband high-definition television signal. Regarding.

[Background of the idea]

NHK Giken Monthly Report, Vol. There is a method discussed in a document entitled "New Transmission Method for High-Definition Television (MUSE)" by Ninomiya in Volume 27, No. 7, July 1984.

As described in this document, this method applies sub-Nyquist sampling to a wideband high-definition television signal in 4 fields, compresses the spatial frequency to 1/4, and transmits the signal. , generally MUSE (Multiple Sub−Nyquist
It is called the Sampling Encoding method.

Figure 2 shows a receiver that uses field and frame memory to interpolate a high-definition television signal (hereinafter referred to as MUSE signal) band-compressed by this MUSE method and returns it to the original wideband high-definition television signal. An example of a decoder portion of the figure is shown.

In Figure 2, 1 is the MUSE signal input terminal;
2, 3, and 4 are output terminals for broadband R, G, and B signals, 5 and 6 are HD and VD synchronization signal output terminals, and 7 is an A/D that converts the analog MUSE signal into a digital signal. Converter, 8 is MUSE
Phase comparator to detect phase error of signal HD and frame pulse (FPP), 9 is horizontal frequency _H
A VCO that oscillates at a frequency (approximately 32MHz) 960 times that of
10 is a frame pulse detector that detects frame pulses and each synchronization signal, 11 is a data detector that detects each control signal and block data of the MUSE signal, and 12 is an HD for monitoring and
A synchronous generator that generates VD, 15 is a noise reducer circuit (hereinafter referred to as NR circuit), 14, 1
5 is a first and second switch circuit switched by the sub-sample clock; 16 is a first field memory; 17 is a second field memory for motion compensation; 18 is an LPF; 19 and 20 are first and second switch circuits, respectively. ,
The second HPF, 21, is the first HPF 19 output and the second
a first adder for adding the HPF output 20 of 2;
3 is a selection circuit that selects the smallest one among the outputs of the first HPF 19, the second HPF 20, and the first adder;
22 is a second adder that adds the outputs of the LPF 18 and the selection circuit 23, 24 is a 1H delay circuit, and 25 is a 1H
A third adder adds the input signal and output signal of the delay circuit 24; 26, 27, and 28 are first, second, and third interpolation filters, respectively; 29 is a first interpolation filter 26 and a second interpolation filter; a fourth adder 30 that adds the output of the interpolation filter 27; 30 is a third switch circuit that guides the output of the fourth adder 29 for still images and the output of the third interpolation filter 28 for moving images; 31 is a chroma decoding circuit that returns a chroma signal whose time axis has been compressed to 1/4 to its original time axis, and 32 and 33 are chroma signals that have been digitally processed ( _CW and _CN ), respectively.
and a D/A converter that converts the luminance signal Y into an analog signal, and 34 is an inverse matrix circuit that converts the Y, _CW , and _CN signals decoded into the original wideband signal into R, G, and B signals. .

The features of this MUSE signal receiver decoder are:
In order to digitally interpolate four fields' worth of images sequentially and return them to the original wideband signal, it is necessary to have a memory for four fields.

Therefore, by using the memory for these four fields and constantly reading out the four fields' worth of signals written in the memory, it is possible to freeze the image.

However, the MUSE signal includes horizontal and vertical motion vectors that indicate screen movement, Y subsample phase that indicates the sample point of the luminance signal, C subsample phase that indicates the sample point of the chroma signal, and Re-subsample phase that indicates the degree of noise reduction. Izuri reducer control, inter-field interpolation control that indicates that inter-field interpolation is not forcibly performed, full-scale 1-frame detection that indicates that full-screen 1-frame detection is forcibly used as motion detection, and motion detection sensitivity. Motion area detection sensitivity control to switch, motion area detection temporal filter time constant switching indicating the selection of a time constant to temporally extend the motion area detection signal, forced space to control so that the threshold level of movement area detection does not fall below a certain value. Control signals such as the interpolation usage ratio, and block controls that divide the screen into approximately 500 blocks to distinguish between static and moving parts, and indicate whether or not to use 1 frame detection for each block as motion area detection. Even if the signals written in the memory for 4 fields are read out cyclically as described above, the signals read out from the memory may not be normal due to the influence of control signals that differ in time. Can't get frozen images.

[Purpose of invention]

The purpose of this invention is to solve the above problems,
An object of the present invention is to provide a high-definition television receiver having a normal freeze function in a decoder part that returns a band-compressed high-definition television signal such as a MUSE signal to an original wide-band signal.

[Summary of the idea]

In order to achieve the above object, the present invention includes a switch circuit at the input stage of the field memories 16 and 17 of the decoder section to switch the current signal from the A/D converter 7 and the field memory output between normal mode and freeze mode. At least in the freeze mode, the horizontal and The input of the vertical motion vector is stopped, and no motion correction is performed in the motion correction field memory 17 in the freeze mode.

[Example of idea]

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, numeral 35 is an input terminal for the control signal of the freeze mode, and 36 is the input terminal for the control signal of the freeze mode, and the numeral 36 is for the output of the NR circuit 13 during normal operation, and the output of the field memory 17 from the second switch circuit 15 during freezing, through the first switch circuit 14. The fourth leading to field memory 16
The switch circuit 37 normally guides the horizontal and vertical motion vectors in the control signal to the motion compensation field memory 17, and when frozen, cuts off the motion vectors and stops motion compensation in the field memory 17. The fifth switch circuit and others are the same as the embodiment shown in FIG. 2 described above.

First, the operation of the embodiment shown in FIG. 1 will be briefly explained.

The MUSE signal from the input terminal 1 is converted into a digital signal of, for example, 8 bits and a _480H sample rate by the A/D converter 7, one of which is sent to the video signal processing circuit system on the NR circuit 13 side, and the other is sent to the phase comparator 8. , a VCO 9, a frame pulse detector 10, a data detector 11, a synchronous generator 12, and the like. In the synchronous signal processing circuit system, the phase comparator 8 compares the phase with the synchronous signal in the MUSE signal, the detected phase error signal controls the VCO 9, and a clock signal whose phase is synchronized with the MUSE signal is obtained at the output of the VCO 9. . The frame pulse detector 10 detects each synchronization signal, and also obtains a _480H subsample clock signal in accordance with the Y and C subsample phases detected by the data detector 11. Switch circuits 14, 15 and each interpolation filter 2
6, 27, 28. The data detector 11 detects the aforementioned control signals, and the motion vectors therein are guided to the motion correction field memory 17 through the fourth switch circuit 37. On the other hand, in the video signal processing circuit system, the MUSE signal is led to the NR circuit 13 at one end, and is then led to the field memory 1 through the second switch circuit 15.
Noise reduction is performed using the signals from two frames earlier from 6 and 17. Normally, the fourth switch circuit is connected in the opposite direction to that in FIG. 1, and the output of the NR circuit 13 is guided to the first switch circuit 14. The first and second switch circuits 14, 15 are switched by a _480H sub-sample clock signal, and the current MUSE signal from the fourth switch circuit 36 and the current The one frame previous signal from the two field memories 17 is alternately led to the first field memory 16 through the first switch circuit 14. Therefore, two field memories 1
6 and 17, two frames worth of signals at a sample rate of 480 _H are stored, and the current signal and the two fields (one frame) previous signal are output from the first switch circuit 14 at the sub-sampling phase period. The signals of one field before and three fields before are output to the field memory 16 of the second field memory 17.
The signals of two fields (one frame) before and four fields (two frames) before are respectively led to the output.
Each signal obtained in this way is a two-dimensional LPF consisting of the current signal and the signal two fields before.
18, a vertical filter consisting of a 1H delay line 24 for the 1st field and 3rd field pre-signals and a third adder 25, each interpolation filter 26, 27,
28 and the fourth adder 29 to add the original 1920 _H (approximately
64MHz) sample rate signal. Third
The switch circuit 30 switches between a still area and a moving area, and in the still area, the luminance signal from the fourth adder 29 interpolated in these four fields is received, and in the moving area, the luminance signal is sent from the third interpolation filter 28. The luminance signal processed within the same field is guided to the second D/A converter 33, where it is converted back to the original analog signal. On the other hand, the chroma signal is sent to the chroma decoder 31
Here, the chroma signal that was line-sequential and time-compressed to 1/4 is returned to the original time axis and into two color difference signals C _W and C _N , and the first D/A conversion is performed. The signal is converted into the original analog signal at the converter 32. Broadband luminance signal Y and color difference signal obtained in this way
C _W and C _N are the inverse matrix circuit 34, and the original R, G,
The signal is returned to the original B signal and sent to a monitor, resulting in a high-quality television image.

The above is an explanation of the normal operation.

Next, it will be explained that a normal frozen image can be obtained by the present invention.

In the freeze mode, the fourth switch circuit 3
6 Connected as shown in the diagram, the first switch circuit 1
4 and the input of the first field memory 16.
The current signal from the NR circuit 13 is suddenly cut off, and the 4-field previous signal of the second field memory 17 output is passed through the 15a terminal of the second switch circuit 15 and the fourth switch circuit 36 due to the sub-sampling phase. Then, the 2-field pre-signal is led through the 15b terminal of the second switch circuit 15. Therefore, in freeze mode, the 1st field, 2nd field, 3rd field, 4th field at the time of freezing start
The four signals before the field circulate within the first and second field memories 16 and 17 and the first, second and fourth switch circuits 14, 15 and 36. Therefore, the decoder output terminals 2, 3, and 4 always output a high-quality television signal obtained by decoding the signals of the same four fields, resulting in a frozen image. However, the signal guided to the synchronous signal processing circuit system is not the signal for four fields circulating in the field memories 16 and 17, but the current MUSE signal from the A/D converter, which is detected by the data detector 11. Each control signal is that of the current MUSE signal. Therefore, when a horizontal or vertical motion vector guided to the second field memory 17 for motion compensation is input during freezing, the signals circulating in the field memories 16 and 17 have already undergone motion compensation. Despite being
Erroneous motion correction is performed, resulting in the inconvenience that the frozen image moves horizontally or vertically along with the motion vector.

Therefore, in the present invention, as shown in the figure, the fifth
A switch 37 is provided to cut off the motion vector guided to the motion correction field memory 17 in the freeze mode. Thereby, it is possible to prevent erroneous motion correction due to the motion vector after freezing, and the above-mentioned problem can be solved.

FIG. 3 shows another embodiment of the present invention.

In FIG. 3, 38 is a latch circuit which latches the freeze control signal with a frame pulse of a field period or a frame period, for example. 39
is a switch circuit which normally leads the sub-sample clock signal as a control signal to the first and second switch circuits 14 and 15, and which cuts off the sub-sample clock signal in the freeze mode. The rest is the same as the embodiment shown in FIG.

This embodiment has the following features due to the latch circuit 38. In other words, by latching the freeze control signal with a frame pulse, for example, the freeze mode starting point can be set to the V blanking period, so even if the freeze occurs at the point where the screen changes, the contents of the freeze screen will be different at the top and bottom. does not cause such problems. It is also effective to use the technique of latching this freeze mode signal with a frame pulse or field pulse as described above in the present invention shown in FIG.

Further, in the embodiment shown in FIG. 3, a switch circuit 39 for controlling the sub-sample clock signal with a freeze mode signal is provided in place of the fourth switch circuit 36 shown in the embodiment shown in FIG. That is, under normal conditions, the first and second switch circuits 14 and 15 are switched by the subsample control signal as in the embodiment shown in FIG.
The current signal from the converter 7 and the two-field previous signal from the second field memory 17 are switched in subsample phase, and the signal from the first field memory 16
And it is led to LPF18 and HPF19. on the other hand,
In the freeze mode, the subsample clock signal is cut off, the first and second switch circuits 14, 15 are always connected as shown, and the first
Field memory 16 and LPF 18, HPF
The 2nd field previous signal and the 4th field previous signal from the second field memory 17 are led to 19 to obtain a frozen image. In this way, the third
In the embodiment shown in FIG. 1, there is no need to provide a switch circuit 36 for switching, for example, an 8-bit digital signal during the freeze mode, as in the embodiment in FIG. 37, the circuit configuration becomes simpler.

FIG. 4 shows a specific embodiment of the first and second switch circuits 14, 15 of FIG. 3 and a switch circuit 39 for switching the subsampling clock signal. In FIG. 4, 40 is an input terminal for the _960H sample clock signal, 41 is an input terminal for the sub-sample clock signal, 42 is an input terminal for the freeze control signal, 43 is an input terminal for the current signal from the NR circuit 13, 44 is an input terminal for the 2-field previous and 4-field previous signals from the second field memory 17, 45 is an output terminal for signals guided to the first field memory 16, LPF 18, and HPF 19, and 46 is guided to the NR circuit 13. The output terminal 47 for the 4-field pre-signal is a flip-flop circuit for cutting off the sub-sample clock signal in the freeze mode, and corresponds to the switch circuit 39 in the embodiment shown in FIG. 48 and 49 are multiplexer circuits, which are connected to the first and second switch circuits 1, respectively.
It corresponds to 4.15. In this embodiment, in the freeze mode, for example, the output of the flip-flop 47 becomes "Low", and two "Low" signals are input to the selector terminals of the multiplexers 48 and 49.
The 2-field and 4-field pre-signals from input B and the zero value are led to output terminals 45 and 46, respectively.

Furthermore, in the present invention, it is possible to improve the frozen image by doing the following.

FIG. 5 shows an embodiment for improving the frozen image obtained by the present invention, and shows, for example, a portion of the synchronization signal processing circuit system of the embodiment of the present invention shown in FIG. The feature of this embodiment is that the internal frame pulse generator 51 is controlled by the frame pulse from the frame pulse detector 10, and the subsample clock is controlled by the Y subsample phase and the C subsample phase from the data detector 11. two switch circuits 5 comprising a generator 52 and controlled by a freeze mode signal from an input terminal 50;
3 and 54, in the freeze mode, the frame pulse from the frame pulse detector 10 and the Y and C subsample phases from the data detector 11 are interrupted, respectively, and the internal frame pulse generator 51 and subsample clock generator 52 is operated in free mode, and the frame pulse and sub-sample clock signals obtained in this free mode are used. Thereby, it is possible to prevent deterioration of the frozen image due to a frame pulse error caused by temporary stopping of the current signal during the freeze mode, for example. For example, when the current signal is panning, Y, C
When the sub-sample phase changes, the phase of the sub-sample clock signal also changes, causing freeze image deterioration. However, because of the above, the phase of the sub-sample clock signal in freeze mode does not change due to the current signal. The above frozen image deterioration can be prevented.

Furthermore, as shown in an embodiment in FIG. 5, by providing a switch circuit 55 that cuts off the output of the phase detector 8 led to the VCO circuit 9 in the freeze mode, the VCO circuit 9 can be turned off at 960 _H in the freeze mode. By operating in free mode, it is possible to prevent deterioration of the frozen image due to phase detection malfunction of the current signal.

Although not shown in the drawings, the present invention uses a block control that divides the screen into approximately 500 blocks during freeze mode, distinguishes between static parts and moving parts, and indicates whether or not to use 1 frame detection for each block as moving area detection. The frozen image can be improved by stopping the signal or by accumulating block control signals for four fields and sequentially reading out the block control signals for the same field.

Furthermore, if the frozen image is a still image, the image can be improved by stopping the block control signal or stopping the motion area detection operation and forcibly performing field interpolation for four fields.

Furthermore, as the simplest method, detection of various control signals in the data detector 11 may be stopped during the freeze mode, or control signal output may be interrupted.

FIG. 6 shows another embodiment of the present invention. 7th
In the figure, the synchronization signal system and each filter are omitted.

In FIG. 7, 72 stops the sub-sample clock signal guided to a switch circuit 73 that switches between the current signal from the A/D converter 7 and the 2-field previous signal from the second field memory 17 in the freeze mode. The switch circuits 74 and 75 are flip-flops for latching, and the others are as shown in FIGS. 1 and 3.
Same as the figure.

In this embodiment, the NR circuit 13 is provided after the switch circuit 73 which switches between the current signal and the output of the field memory 17 using a sub-sample clock signal or a freeze control signal. By doing so, the configuration of each switch circuit becomes simpler than that of the embodiment shown in FIG.

FIG. 7 shows another embodiment of the present invention in which the memory configuration is different from that in FIG. 6.

In FIG. 8, 76 indicates the current signal from the A/D converter 7 in normal mode, and 4 fields (2 frames) from field memory 80 in freeze mode.
A flip-flop 74 for latching the previous signal and
The switch circuits 77 to 80 leading to the NR circuit 13 are
This memory is equivalent to one field at a sampling rate of _480H , of which 78 and 80 are field memories for motion correction. Other details are the same as in Figure 7.

The feature of this embodiment is that the field memory 77
~80 as a memory for one field at a sampling rate of 480 _H , the A/D converter 7, each latch circuit (not shown), and the memory 77
-80 can be driven with a _480H clock signal, and the driving speed can be reduced to half that of the _960H clock drive shown in FIGS. 1 and 3.
Therefore, the stability of the circuit configuration and circuit operation can be improved.

As described above, in the present invention, the field memories 16, 1
Although the embodiment in which dynamic memory is used as the field memories 16, 17 or 77-80 has been described, for example, in the case where static memory is used as the field memories 16, 17 or 77-80, the embodiment shown in FIG. The fourth switch circuit 36 is not necessary, and it is sufficient to stop writing to each field memory and only perform reading in the freeze mode.

The present invention is not limited to the circuit configurations of the embodiments shown in FIGS. 1, 3, and 5 to 7, and is not limited to the MUSE signal alone. , and is applied to a television signal receiver that performs motion compensation using motion vectors.

[Effect of idea]

According to the present invention, a freeze function can be easily provided using the 4-field memory provided in the decoder section of a high-definition television receiver, and deterioration of freeze image quality due to each control signal is suppressed, resulting in a good freeze function. You can get the image.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, FIG. 2 is a circuit block diagram showing an example of a conventional MUSE signal decoder, and FIG. 3 is a circuit block diagram showing another embodiment of the present invention. FIG. 4 is a circuit diagram showing a specific embodiment of the switch circuit used in the embodiment of the present invention shown in FIG. 3, and FIG. 5 is a circuit block diagram showing an embodiment of the present invention for improving frozen images. , FIG. 6 is a circuit block diagram showing another embodiment of the present invention, and FIG. 7 is a diagram showing another embodiment of the present invention different from FIG. 6. Explanation of symbols, 7...A/D converter, 8...Phase comparator, 9...960 _H VCO, 10...Frame pulse detector, 11...Data detector, 12...Synchronization generator, 13 ...NR circuit, 14...First switch circuit, 15...Second switch circuit, 16
...First field memory, 17...Second field memory, 26, 27, 28...Interpolation filter, 30...Third switch circuit, 31...Chroma decoder, 32, 33...D/ A converter, 3
4... Inverse matrix circuit, 36... Fourth switch circuit, 37... Fifth switch circuit, 38...
Latch circuit, 51...Frame pulse generator, 5
2...Subsample clock generator, 53,5
4, 55, 72, 73, 76... switch circuit,
74, 75...flipflop, 77~80...
...field memory.

Claims (1)

[Scope of utility model registration request] A high-definition television signal that has been band-compressed by subsampling that goes around at least four fields and is equipped with a motion vector for motion compensation and a control signal for the subsampling phase is converted into the original wideband high-definition television signal that has not been band-compressed. A decoder for demodulating includes at least a circuit for detecting each control signal and a field memory for four fields, and returns the field memory output to the field memory input or stops writing to the field memory in a freeze mode. At the same time, input of the motion vector to the field memory to which the motion correction is to be performed is stopped, or
or a high-definition television receiver characterized by stopping motion compensation.