JPH04252690A - Video signal coding method and video signal encoder - Google Patents

Abstract

PURPOSE:To decrease the predictive error of a static area in a field, in an interlacing scanning. CONSTITUTION:A field sequence changing means 2 moves the second field of N frames of an input 1 so as to be positioned behind the first field of (N+1) frames, a signal subjected to this field sequence change is inputted to a predictive error arithmetic circuit 3 and a predictive error signal being an error to a predictive signal is derived, and coded by an encoding circuit 4. A local decoding means decodes this predictive error code, predicts the first field of the N frames from the first field of (N-1) frames, and predicts a second field of the N frames from the first field of the N frames and the first field of (N+1) frames.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal encoding method and apparatus for highly efficient encoding of video signals during transmission or recording of video signals.

0002

[Background Art] In recent years, with the development of video telephones and video conference systems, video signal encoding devices have been
Various high-efficiency encoding techniques have been put into practical use. In particular, techniques using interframe prediction are often used in video signal encoding devices.

The above-mentioned conventional video signal encoding device will be explained below with reference to the drawings. FIG. 6 shows a block diagram of a conventional video signal encoding device. In Figure 6,
1 is an input of the video signal encoding device, 3 is a prediction error calculation circuit, 4 is an encoding circuit, 5 is a local decoder, and 6 is an output of the video signal encoding device. 401 is a DCT circuit (discrete cosine transform circuit), 402 is a quantization circuit, and these constitute the encoding circuit 4. 403 is a prediction error code output from the encoding circuit 4, and 501 is a prediction signal input to the prediction error calculation circuit 3. 504 is a field memory, 506 is an adder circuit, 507 is an IDC
T circuit (inverse discrete cosine transform circuit), 508 is an inverse quantization circuit, 509 is a motion vector detection circuit, these constitute a local decoder, and the inverse quantization circuit 508
The prediction error code 403 is input to the IDCT circuit 5.
The reproduced prediction error signal 510 outputted through 07 is added to the predicted signal 501 outputted from the field memory 504 in an adder circuit 506, and the reproduced prediction error signal 510 is
This field memory 504 obtains a prediction signal 501 by applying the motion vector determined by the motion vector detection circuit 509 to the pixel coordinates.

Reference numeral 7 denotes a variable length encoding circuit to which the prediction error code 403 is input, and 8 denotes a buffer memory to which the output of the variable length encoding circuit 7 is input and outputs the output 6 of the video encoding apparatus. Reference numeral 9 denotes a code amount control circuit, which controls the quantization circuit 402 so that the remaining amount of data in the buffer memory 8 becomes a predetermined value.
and the value of the quantization step size 91 given to the inverse quantization circuit 508.

[0005] The operation of the video signal encoding device configured as described above will be explained below. A video signal to be encoded is input to input 1 of the video signal encoding device. This video signal is based on an interlace scanning method. This video signal is encoded by an inter-field predictive encoding circuit comprising a prediction error calculation circuit 3, an encoding circuit 4, and a local decoder 5.

FIG. 7 shows a video signal at input 1 of the video signal encoding device and a prediction method for each field. Using the interlaced scanning method, one frame consists of the first field f(
n, 1) and a second field f(n, 2). Each field is predicted from the previous field. For example, field f(n+1,1) is field f
Predicted from (n, 2).

When field f(n, 1) is input to input 1 of the video signal encoding device, local decoder 5 outputs fp(n, 1) as prediction signal 501. The predicted signal fp(n, 1) is obtained by motion compensation performed by the motion vector detection circuit 509 when reading out the reproduced signal fr(n-1, 2) recorded in the field memory 504. fr (n-1, 2) is a reproduced signal one field before field f (n, 1). Prediction error calculation circuit 3
is the predicted signal fp(n,
1) Obtain the prediction error signal that is the error. This prediction error signal is encoded by the encoding circuit 4 and is encoded by a prediction error code 403.
is output as The prediction error code 403 is an inverse quantum circuit 508 and IDCT
The reproduced prediction error signal 5 is decoded through the circuit 507.
Output as 10. The adder circuit 506 adds the reproduced prediction error signal 501 and the predicted signal fp(n, 1) and outputs fr(n, 1) as the reproduced signal 511. The reproduced signal fr (n, 1) is obtained by encoding and decoding the field f (n, 1). Reproduction signal fr (n, 1)
is recorded in field memory 504.

The variable length encoding circuit 7 uses a prediction error code 403
is variable-length coded and then output to the buffer memory 8. The code amount control circuit 9 controls the value of the quantization step size 91 given to the quantization circuit 402 and the inverse quantization circuit 508 so that the remaining amount of data in the buffer memory 8 becomes a predetermined value. A signal whose code amount has been controlled is outputted from the buffer memory 8 to an output 6 of the video signal encoding device.

[0009]

[Problems to be Solved by the Invention] However, in the above configuration, since the field to be encoded is predicted from the field one field before, in a video signal using the interlaced scanning method, the odd field is an even field and the even field is an odd field. Therefore, there is a problem in that the prediction error becomes large in static areas within the field.

SUMMARY OF THE INVENTION The present invention solves the above problem, and aims to provide a video signal encoding method and apparatus that can reduce prediction errors in static areas within a field.

[0011]

[Means for Solving the Problems] In order to solve the above problems, the video signal encoding method of the present invention uses the first field of the current N frames when predictively encoding a video signal using an interlace scanning method. Predict from the first field of the previous N-1 frame, and predict the second field of the current N frame by predicting the first field of the current N frame and the next N+
Predict from the first field of one frame or from the current N
The first field of a frame is predicted from the second field of the current N frame and the second field of the previous N-1 frame, and the second field of the current N frame is predicted from the second field of the previous N-1 frame. It is predicted from two fields.

The video signal encoding device of the present invention further includes a field order changing means for changing the time order of fields of an input video signal, and a video signal whose time order is changed by the field order changing means and a prediction described later. prediction error calculation means for calculating a prediction error signal by comparing the prediction error signal with the prediction error signal; encoding means for encoding the prediction error signal and outputting a prediction error code; and local decoding for decoding the prediction error code to obtain a prediction signal. It is equipped with the means.

[0013]

[Operation] With the above-described configuration, the present invention provides the first
field or the second frame to the first one frame before
Since the prediction is made from the field or the second frame, the prediction error can be reduced in a still area within the field. In other words, encoding efficiency can be improved.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A video signal encoding apparatus according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a video signal encoding apparatus according to an embodiment of the present invention. In FIG. 1, 1 is an input of a video signal encoding device, 2 is a field order change circuit, 3 is a prediction error calculation circuit, 4 is an encoding circuit, 5 is a local decoder,
6 is the output of the video signal encoding device. 201 ,20
2 is a field memory, 203 is a switching circuit, 20
5 is a control circuit, and these control the field order change circuit 2.
The input 1 is directly input to the switching circuit 203 through the field memories 201 and 202, and the switching circuit 203 switches these and outputs them.The output field order change signal 204 is sent to the prediction error calculation circuit 3. is input. 401 is a DCT circuit (
402 is a quantization circuit, and these constitute the encoding circuit 4. 403 is a prediction error code output from the encoding circuit 4, and 501 is a prediction signal input to the prediction error calculation circuit 3.

502 is a switching circuit, 503 is a field interpolation circuit, 504 and 505 are field memories, 506 is an addition circuit, 507 is an IDCT circuit (inverse discrete cosine transform circuit), 508 is an inverse quantization circuit, 509
is a motion vector detection circuit, these constitute the local decoder 5, the prediction error code 403 is input to the inverse quantization circuit 508, and the reproduced prediction error signal 510 outputted through the IDCT circuit 507 is input to the addition circuit 506.
The prediction signal 501 output from the switching circuit 502
is added to the field memories 504 and 505 as a reproduced signal 511. field memory 50
The playback signal 511 recorded in 4,505 is
The motion vector detection circuit 509 to which input 1 is input performs motion compensation and is read out, and is input to the switching circuit 502 directly and through the field interpolation circuit 503, respectively.

7 is a variable length encoding circuit to which the prediction error code 403 is input; 8 is a buffer memory to which the output of the variable length encoding circuit 7 is input and outputs the output 6 of the video signal encoding device; 9 is a buffer A quantization circuit 402 and an inverse quantization circuit 508 are operated so that the remaining amount of data in the memory 8 becomes a predetermined value.
This is a code amount control circuit that controls the value of the quantization step size 91 given to the quantization step size 91, and is the same as the conventional circuit shown in FIG.

The operation of the video signal encoding apparatus configured as described above will be explained with reference to FIG. A video signal to be encoded is input to input 1 of the video signal encoding device. This video signal is based on an interlace scanning method. This video signal is input to the field order changing circuit 2. The field order changing circuit 2 changes the time order of the input signal on a field-by-field basis and outputs the changed time order.

The operation of the field order changing circuit 2 will be explained with reference to FIG. FIG. 2(a) shows a video signal input to the field order changing circuit 2. With the interlaced scanning method,
One frame consists of a first field f(n, 1) and a second field f(n, 2). The field reordering circuit 2 moves the second field f(n,2) after the first field f(n+1,1) in the next frame. FIG. 2(b) shows the output signal of the field order changing circuit 2.

FIG. 4 is a timing diagram of the video signal encoding device. 4(a) shows the input signal of the video signal encoding device, FIG. 4(b) shows the input/output signal of the field memory 201, FIG. 4(c) shows the input/output signal of the field memory 202, and FIG. 4(d) shows the switching. FIG. 4(e) shows the output signal 204 of the field reordering circuit 2, which is the input selected by the circuit 203. In the field memory input/output signals shown in FIGS. 4(b) and 4(c), W indicates that the field memory is in an input state, and R indicates that the field memory is in an output state.

The control circuit 205 controls the switching circuit 203 and the field memory. At time t1,
The switching circuit 203 selects input A, and the input signal of the video signal encoding device becomes the output signal of the field order changing circuit 2. At time t2, the switching circuit 203 selects the input C, and the field f(n-1, 2) read from the field memory 202 becomes the output signal of the field order changing circuit 2. At this time, field f(n, 2) of the input signal of the video signal encoding device is written into the field memory 201. At time t3, the switching circuit 203 selects input A, and the input signal of the video signal encoding device becomes the output signal of the field order changing circuit 2. At time t4, the switching circuit 203 switches the input B
The field f(n, 2) read from the field memory 201 becomes the output signal of the field order changing circuit 2. At this time, the field f(n+1, 2) of the input signal of the video signal encoding device is stored in the field memory 20.
2 is written. By repeating the above operations from t1 to t4, the field order changing circuit 2 changes the field order of the input signal and outputs it as shown in FIG. 4(e).

The prediction error calculation circuit 3, the encoding circuit 4, and the local decoder 5 constitute an inter-field predictive encoding circuit. First, a method of inter-field prediction will be explained with reference to FIG. FIG. 3 shows a video signal at input 1 of the video signal encoding device and a prediction method for each field. The first field of each frame is predicted from the first field of the previous frame. For example, field f(n+
1,1) is predicted from field f(n,1). Further, the second field of each frame is predicted from two adjacent first fields. For example, field f(n,2) is equal to field f(n,1) and f(n+1).
, 2).

Next, the operation of the inter-field prediction circuit will be explained with reference to FIG. 4(f) shows the prediction signal 501, FIG. 4(g) shows the input/output signal of the field memory 504,
FIG. 4(h) shows input/output signals of the field memory 505. In the input/output signals of the field memory in FIGS. 4(g) and (h), W indicates that the field memory is in the input state;
R indicates that the field memory is in the output state.

At time t1, when field f(n, 1) is output as the output signal 204 of the field order changing circuit 2, the local decoder 5 outputs f as the predicted signal 501.
Output p(n, 1). The prediction error calculation circuit 3 obtains a prediction error signal which is the error of the prediction signal fp(n,1). The prediction error signal is encoded by the encoding circuit 4 and a prediction error code 403 is output. The prediction error code 403 is decoded by an inverse quantum circuit 508 and an IDCT circuit 507 to obtain a reproduced prediction error signal 510. The adder circuit 506 adds the reproduced prediction error signal 510 and the predicted signal fp(n, 1) and outputs the reproduced signal fr(n, 1). playback signal fr
(n, 1) is the encoded and decoded field f(n, 1). The reproduced signal fr(n,1) is written into the field memory 505. Prediction signal fp(n,
1), the playback signal fr(n-1,1) recorded in the field memory 504 is transmitted to the motion vector detection circuit 509.
The motion is compensated by This predicted signal fp(
n, 1) is output as the prediction signal 501 when the switching circuit 502 selects the input a.

At time t2, when field f(n-1, 2) is output as the output signal 204 of the field order change circuit 2, the local decoder 5 outputs fp(n-1, 2) as the prediction signal 501. Output. Prediction error calculation circuit 3
calculates a prediction error signal that is the error of the prediction signal fp(n-1, 2). The prediction error signal is encoded by the encoding circuit 4 and outputs a prediction error code 403. field memory 5
The field fr (n-1, 1) recorded in 04 and the field fr (n-1, 1) recorded in field memory 505
n, 1) are each subjected to motion compensation by a motion vector detection circuit 509 and input to a field interpolation circuit 503. Field interpolation circuit 503 obtains a prediction signal fp(n-1, 2) from these signals and outputs it. This predicted signal fp(n-1, 2) is output as a predicted signal 501 by the switching circuit 502 selecting input b.

At time t3, when field f(n+1,1) is output as the output signal 204 of the field order changing circuit 2, the local decoder 5 outputs fp(n+1,1) as the prediction signal 501. Prediction error calculation circuit 3
calculates a prediction error signal which is the error of the prediction signal fp(n+1,1). The prediction error signal is encoded by the encoding circuit 4 and outputs a prediction error code 403. Prediction error code 403
is decoded by the inverse quantum circuit 508 and the IDCT circuit 507 to obtain a reproduced prediction error signal 510. The adding circuit 506 outputs the reproduction prediction error signal 510 and the prediction signal fp.
(n+1,1) is added to produce the reproduced signal fr(n+1,1)
Output. The reproduced signal fr(n+1,1) is obtained by encoding and decoding the field f(n+1,1). The reproduced signal fr (n+1, 1) is stored in the field memory 504
will be written to. The predicted signal fp(n+1,1) is the reproduced signal fr(n+1,1) recorded in the field memory 505.
n, 1) is subjected to motion compensation by the motion vector detection circuit 509. This predicted signal fp(n+1,1) is output as a predicted signal 501 by the switching circuit 502 selecting input c.

At time t4, when field f(n, 2) is output as the output signal 204 of the field order changing circuit 2, the local decoder outputs fp(n, 2) as the prediction signal 501.
n, 2). The prediction error calculation circuit 3 receives the prediction signal f
A prediction error signal, which is the error of p(n, 2), is obtained. The prediction error signal is encoded by the encoding circuit 4 and becomes a prediction error code 40.
Outputs 3. Field fr(n+1,1) recorded in field memory 504 and field memory 5
The fields fr(n, 1) recorded in 05 are each subjected to motion compensation by a motion vector detection circuit 509 and input to a field interpolation circuit 503. Field interpolation circuit 503 outputs a prediction signal fp(n,2). This predicted signal fp(n,2) is output as a predicted signal 501 by the switching circuit 502 selecting input b.

Encoding is performed by repeating the above steps t1 to t4. A motion vector detection circuit 509 obtains a motion vector used for motion compensation from a video signal input to input 1 of the video signal encoding device. The encoding circuit 4 performs a discrete cosine transform on the input prediction error signal using a DCT circuit 401 , quantizes the obtained coefficient value using a quantization circuit 402 , and outputs a prediction error code 403 . The variable length encoding circuit 7 outputs the variable length encoded code 403 to the buffer memory 8. The code amount control circuit 9 controls the value of the quantization step size 91 given to the quantization circuit 402 and the inverse quantization circuit 508 so that the remaining amount of data in the buffer memory 8 becomes a predetermined value. A signal whose code amount has been controlled is outputted from the buffer memory 8 to an output 6 of the video signal encoding device.

As described above, according to this embodiment, a field order changing circuit changes the time order of fields of an input video signal, and a video signal whose time order is changed by the field order changing circuit is compared with a predicted signal. and a prediction error calculation circuit for calculating a prediction error signal, an encoding circuit for encoding the prediction error signal and outputting a code, and a local decoding circuit for decoding the code and obtaining a prediction signal. Since the first field is predicted from the first field one frame before, prediction errors can be reduced in a still area within the field in a video signal based on the interlaced scanning method. Furthermore, in encoding the second field, prediction can be made using two reproduced signals of the first field that have been encoded adjacently before and after the encoded signal. Coding efficiency can be improved for the above two reasons.

Note that in the first embodiment, the first field is predicted from the first field one frame before, and the second field is predicted from the first field one frame before.
Although the fields are predicted from the adjacent first fields, the second field may be predicted from the second field one frame before, and the first field may be predicted from the adjacent second fields. At this time, the field order change circuit changes the first field f(n,
1) after the second field f(n,2) of this frame. FIGS. 5A and 5B show the input video signal and output video signal of the field order changing circuit at this time.

[0031]

[Effects of the Invention] As described above, the field order changing means for changing the time order of fields of an input video signal;
prediction error calculation means for calculating a prediction error signal by comparing a video signal whose time order has been changed by the field order changing means with a prediction signal to be described later; and an encoding means for encoding the prediction error signal and outputting a code. and a local decoding means for decoding the code to obtain a predicted signal, so that the first field or the second field to be encoded is predicted from the first field or the second field one frame before, In a video signal based on an interlaced scanning method, prediction errors can be reduced in a still area within a field.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video signal encoding device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing input and output signals of a field order changing circuit according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram illustrating a field prediction method according to an embodiment of the present invention.

FIG. 4 is a timing diagram of a video signal encoding device according to an embodiment of the present invention.

FIG. 5 is a timing diagram of a video signal encoding device according to another embodiment of the present invention.

FIG. 6 is a block diagram of a conventional video signal encoding device.

FIG. 7 is an explanatory diagram illustrating a field prediction method of a conventional video signal encoding device.

[Explanation of symbols]

1 Input 2 of video signal encoding device
Field order change circuit 201 Field memory 202 Field memory 203 Switching circuit 204 Output 205 of field order change circuit
Control circuit 3 Prediction error calculation circuit 4 Encoding circuit 401 DCT circuit (discrete cosine transform circuit)
402 Quantization circuit 403 Prediction error code 5 Local decoder 501 Prediction signal 502 Switching circuit 503 Field interpolation circuit 504 Field memory 505 Field memory 506 Addition circuit 507 IDCT circuit (inverse discrete cosine transform circuit) 508 Inverse quantization circuit 509 Motion vector Detection circuit 510
Reproduction prediction error signal 511 Reproduction signal 6 Output 7 of video signal encoding device
Variable length encoding circuit 8 Buffer memory 9 Code amount control circuit

Claims (6)

[Claims] Claim 1: When predictively encoding a video signal using an interlace scanning method, the first field of N frames is predicted from the first field of N-1 frames, and the second field of N frames is predicted from the first field of N frames and the first field of N+1 frames. A video signal encoding method that predicts from one field. 2. When predictively encoding a video signal using an interlace scanning method, the first field of N frames is predicted from the second field of N-1 frames and the second field of N frames, and the second field of N frames is predicted from N-1 frames second field. A video signal encoding method that predicts from the second field of a frame. 3. A video signal encoding device for encoding a video signal using an interlace scanning method, comprising: field order changing means for changing the time order of fields of an input video signal; and a field order changing means changing the time order by the field order changing means. a prediction error calculation means for calculating a prediction error signal by comparing a video signal that has been changed with a prediction signal to be described later; and an encoding means for encoding the prediction error signal and outputting a prediction error code;
A video signal encoding device comprising: local decoding means for decoding the prediction error code to obtain a prediction signal. 4. Field order changing means includes first and second field memories for recording an input video signal, an output of the first field memory, an output of the second field memory, and an output of the input video signal. a switching means for selecting one of them; and a control means for controlling reading and writing of the first and second field memories and controlling the switching means; Frame 2nd field is N+1
4. The video signal encoding apparatus according to claim 3, wherein the time order is changed so that the frame is located after the first field. 5. Field order changing means includes first and second field memories for recording an input video signal, an output of the first field memory, an output of the second field memory, and an output of the input video signal. a switching means for selecting one of them; and a control means for controlling reading and writing of the first and second field memories and controlling the switching means; 4. The video signal encoding apparatus according to claim 3, wherein the time order is changed so that the first field of the frame is located after the second field of the Nth frame. 6. The local decoding means comprises: a motion vector detection means for obtaining a motion vector of an input video signal; a decoding means for decoding a prediction error code to obtain a reproduced prediction error signal; an addition means for obtaining a reproduced signal from a predicted signal, and a first
a first field memory that obtains a predicted signal of the first field; a second field memory that records the reproduced signal and obtains a second predicted signal by giving a shift to the pixel coordinates by the motion vector when read out; Field interpolation means for obtaining a third predicted signal by linear calculation of the predicted signal and the second predicted signal, and switching means for selecting the predicted signal from the first, second, and third predicted signals. The video signal encoding device according to claim 3, characterized in that: