JPH04252509A - Pulse width correction circuit - Google Patents

Abstract

PURPOSE:To optimize a delay time of a variable delay circuit 2 by controlling a reference voltage 7 with an external logic signal so as to output a signal with a pulse width in response to the reference voltage 7. CONSTITUTION:An inputted pulse signal is varied with a variable delay circuit 2 and a signal having the pulse width in response to the delay time is generated by an R/S flip-flop circuit 3. The signal is given to a low pass filter circuit 4, in which harmonic components of the signal are eliminated to obtain a DC component and the voltage of the DC component and a voltage of a reference voltage generating circuit 7 are added by an operational amplifier circuit 5 to control the variable delay circuit thereby forming stably a signal having an object pulse width.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a pulse width correction circuit used for magnetic disks, and in particular, even if the transfer speed of the magnetic disk changes and the input frequency changes, the present invention can stabilize the pulse width to 1/n of the period of the input signal. The present invention relates to a pulse correction circuit that outputs a pulse width of .

0002

2. Description of the Related Art Conventional pulse correction circuits have a configuration in which a flip-flop is set at the leading edge of an input pulse, and a fixed delay circuit is used to delay the flip-flop circuit by a certain period of time to reset the flip-flop circuit.

0003

[Problems to be Solved by the Invention] In the conventional pulse correction circuit described above, when the frequency of the input signal changes, a flip-flop is set at the leading edge of the input pulse, and a fixed delay circuit is used to delay the pulse by a certain period of time. Since the flip-flop is reset, there is a drawback that the output signal of the pulse correction circuit does not have a value of 1/n of the period of the frequency, unlike the value of the fixed delay circuit and the value of 1/n of the period of the target frequency.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pulse width correction circuit which eliminates the above-mentioned drawbacks and allows the pulse width of the output signal waveform to be 1/n of the frequency period even if the input frequency changes. It is in.

[0005]

[Means for Solving the Problems] The pulse width correction circuit of the present invention includes a variable delay circuit that controls a delay time, and an output signal from the variable delay circuit to set and reset pulses according to the delay time. a flip-flop circuit that sends out a pulse signal with a width of and an operational amplifier circuit that performs addition with the signal and sends the signal to the variable delay circuit as a control signal for the variable delay circuit.

The pulse width correction circuit of the present invention also includes a reference signal generation circuit that generates the reference voltage by high-level and low-level voltages to the flip-flop circuit, and a control that controls the voltage of the reference signal generation circuit. A signal line is provided.

[0007]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart diagram for explaining the operation of this embodiment.

This pulse width correction circuit includes a variable delay circuit 2
, R/S flip-flop circuit 3, and low-pass filter circuit 4
, an operational amplifier circuit 5 , and a reference voltage generation circuit 7 . Further, the input terminal 1 is connected to the reset terminal of the variable delay circuit 2 and the R/S flip-flop circuit 3, and the variable delay circuit 2 is connected to the set terminal of the R/S flip-flop circuit 3. The circuit 3 is connected to the low-pass filter circuit 4, the output terminal 6, and the reference voltage generation circuit 7, the low-pass filter circuit 4 is connected to the inverting terminal of the operational amplifier circuit 5, and the operational amplifier circuit 5 is connected to the variable delay circuit 2. The reference voltage generation circuit 7 is connected to the non-inverting terminal of the operational amplifier circuit 5, and the control signal line 8 is connected to the reference voltage generation circuit 7.

Next, regarding the circuit operation of this embodiment, FIG.
This will be explained with reference to FIG. In particular, the case where a pulse width of 1/2 of the period of the input signal is output will be explained. Normally, when the input signal shown in FIG. 2 is input from the input terminal 1, it is delayed by the variable delay circuit 2, and the signal on the signal line b shown in FIG. 2 is output. The R/S flip-flop circuit 3 is set at the rising edge of the signal line b, and reset at the rising edge of the input terminal 1. Furthermore, the output signal of the R/S flip-flop circuit 3 has high frequency components removed by a low-pass filter circuit 4, and a voltage of 1/2 of the amplitude of the waveform of the output signal of the R/S flip-flop circuit 3 is removed from the low frequency component. Filter circuit 4
is output from. At this time, the reference voltage generation circuit 7 has R
1/2 of the high level voltage and low level voltage of the output of the /S flip-flop circuit 3 is supplied, and the control voltage that allows the variable delay circuit 2 to generate the delay time to maintain the above state is operationally amplified. The output of the circuit 5 is supplied to the variable delay circuit 2. At this time, a logic signal having a pulse width of 1/2 of the period of the signal input from the input terminal 1 is output from the output terminal 6.

Next, when the input frequency increases, the delay time of the variable delay circuit 2 does not change at first, so the input signal a
The time from the rising edge of signal line b to the rising edge of input signal a is longer than the time from the rising edge of signal line b to the rising edge of input signal a, so R/S
The output signal of the flip-flop circuit 3 is longer when it is at a low level than when it is at a high level, and the output voltage of the low-pass filter circuit 4 is lower than the voltage input from the reference voltage generation circuit 7. The output voltage of circuit 5 increases, the control voltage of variable delay circuit 2 increases, the delay time of variable delay circuit 2 decreases, and the time from the rising edge of the input signal to the rising edge of signal line b and the rising edge of signal line b The difference between the time from the rising edge of the input signal to the rising edge of the input signal becomes smaller, and if this is repeated, the difference between the time from the rising edge of the input signal a to the rising edge of the signal line b and the time from the rising edge of the signal line b to the input signal becomes smaller. The time to the rising edge of the signal becomes equal.

Furthermore, when the input frequency becomes low, the delay time of the variable delay circuit 2 does not change at first, so the time from the rising edge of the input signal a to the rising edge of the signal line b is longer than the time from the rising edge of the signal line b to the input signal line b. Because it is shorter than the time to the rising edge of signal a, R/S
The output signal of the flip-flop circuit 3 has a low level time shorter than a high level time, and the low-pass filter circuit 4
The output voltage is higher than the voltage input from the reference voltage generation circuit 7. Then, the output voltage of the operational amplifier circuit 5 decreases, the control voltage of the variable delay circuit 2 decreases, the delay time of the variable delay circuit 2 increases, and the time from the rising edge of the input signal to the rising edge of the signal line b and the signal The difference in time between the rising edge of line b and the rising edge of the input signal becomes smaller. By repeating this, eventually the time from the rising edge of the input signal to the rising edge of signal line b becomes equal to the time from the rising edge of signal line b to the rising edge of the input signal. As a result, when the conditions are changed using the control signal line 8, a logic signal c having a pulse width of 1/n of the period of the signal input from the input terminal 1 is output from the output terminal 6.

0012

As explained above, even if the transition speed of the magnetic disk drive changes and the frequency of the input signal changes, the present invention can control the delay time of the delay circuit based on the pulse width value of the signal. This has the effect of stably outputting a pulse width of 1/n of the period of the input signal even if the input frequency changes.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart diagram for explaining the operation of FIG. 1;

[Explanation of symbols]

2 Variable delay circuit 3 R-S flip-flop circuit 4 Low-pass filter circuit 5 Operational amplifier circuit 7 Reference voltage generation circuit

Claims (2)

[Claims] 1. A variable delay circuit that controls a delay time; a flip-flop circuit that is set and reset by an output signal from the variable delay circuit and sends out a pulse signal with a pulse width corresponding to the delay time; A low-pass filter that removes high-frequency components of the pulse signal, a reference voltage that serves as a reference signal for setting, and an output signal of the low-pass filter circuit and the reference signal are added together to control the variable delay circuit. and an operational amplifier circuit that sends a signal to the variable delay circuit as a signal. 2. The device according to claim 1, further comprising a reference signal generation circuit that generates the reference voltage by high-level and low-level voltages applied to the flip-flop circuit, and a control signal line that controls the voltage of the reference signal generation circuit. pulse width correction circuit.