JPH0425238A - Multi-frame synchronizing circuit - Google Patents

Abstract

PURPOSE:To avoid the increase in a circuit scale attending on the increase in the classifications of multi-patterns by outputting an expected value of an address and a multi-frame timing signal based on an address and a timing signal. CONSTITUTION:A comparator 105 compares an address 5 with its expected value 6 and outputs a coincident or non-coincident output as the result of comparison 7. In this case, a protective circuit 10 protects multi-frame synchronization based on the result of comparison 7. Then a multi-frame timing generating circuit 107 establishes multi-frame synchronization to a data string 3 according to a timing signal 2, the address 5, the result 7 and synchronous, information 8 and outputs a multi-frame timing signal 9. Thus, the need for plural multi- frame pattern detection circuits is eliminated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multi-frame synchronization circuit, and in particular, one multi-frame is composed of a plurality of frames, and two or more frames in one multi-frame are individually distinguishable. The present invention relates to a multi-frame synchronization circuit that synchronizes data strings having multi-frame patterns.

[Conventional technology]

Conventionally, this type of multiframe synchronization circuit has a multiframe structure as shown in Figure 2, and in order to establish multiframe synchronization for a data string with a different multiframe pattern for each frame, a multiframe synchronization circuit is used. In order to avoid dependence on the synchronization establishment time, the pattern detection circuit is used not only for multi-frame pattern MF, but also for multi-frame pattern MF2. MP,...MFI...
- It had n pattern detection circuits for MF and l, making it possible to establish multiframe synchronization from any frame.

[Problem to be solved by the invention]

The conventional multiframe synchronization circuit described above has multiple pattern detection circuits so that the establishment of synchronization does not depend on the multiframe period, and multiframe synchronization can be established from any frame. As the period becomes longer, the number of types of multi-patterns that exist in a multi-frame increases, and many pattern detection circuits are required, resulting in an increase in circuit scale.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiframe synchronization circuit in which the circuit size does not increase even when the types of multipatterns existing in a multiframe increases, and the synchronization establishment time does not depend on the multiframe cycle. It is in.

[Means to solve the problem]

The multi-frame synchronization circuit of the first invention inputs a data string containing different multi-frame synchronization patterns and a frame pulse of the frames to at least two frames out of a plurality of frames constituting one multi-frame. A multiframe synchronization circuit that outputs a multiframe timing signal includes a timing generation circuit that outputs a timing signal of the multiframe synchronization pattern based on the frame pulse, and a timing generation circuit that separates the multiframe synchronization pattern from the data string based on the timing signal. an address generation circuit that generates an address indicating where in the multiframe the frame containing the multiframe synchronization pattern from the separation circuit is located; and the address from the address generation circuit. and an expected value of the address and outputs a comparison result; a protection circuit that outputs multi-frame synchronization protection information based on the comparison result; and a protection circuit that outputs multi-frame synchronization protection information, the comparison result, the address and The apparatus further includes a multi-frame timing generation circuit that outputs the expected value of the address and the multi-frame timing signal based on the timing signal.

The multi-frame timing generation circuit includes an expected address value generation circuit that adds a predetermined number to the address input from the address generation circuit and outputs the result as an expected value of the address to be input next. It's okay.

The multi-frame timing generation circuit adds a predetermined number to the address input from the address generation circuit in the multi-frame synchronization hunting process and outputs the expected value of the address, and in other than the hunting process, the multi-frame timing generation circuit adds the expected value of the address to the address input from the address generation circuit. It may be configured to generate the expected value of the address by self-running in synchronization with a timing signal.

A multi-frame synchronization circuit according to a second aspect of the invention inputs a data string containing a different multi-frame synchronization pattern and a frame pulse of the frame to at least two frames among a plurality of frames constituting one multi-frame. A multiframe synchronization circuit that outputs a multiframe timing signal includes a timing generation circuit that outputs a timing signal of the multiframe synchronization pattern based on the frame pulse, and a timing generation circuit that separates the multiframe synchronization pattern from the data string based on the timing signal. an address generation circuit that generates an address indicating where in the multiframe the frame that included the multiframe synchronization pattern from the separation circuit is located; a multi-frame synchronization pattern expected value generation circuit that outputs the multi-frame synchronization pattern to be input next as an expected value based on the frame synchronization pattern; and a multi-frame synchronization pattern expected value generation circuit that outputs the multi-frame synchronization pattern expected value generation circuit and the separation circuit a comparison circuit that compares the multi-frame synchronization pattern with the multi-frame synchronization pattern and outputs a comparison result; a protection circuit that outputs multi-frame synchronization protection information based on the comparison result; and a protection circuit that outputs multi-frame synchronization protection information, the comparison result, the address and and a multi-frame timing generation circuit that outputs the multi-frame timing signal based on the timing signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In FIG. 1, 101 is a timing signal generation circuit;
A circuit that is controlled by frame pulse 1 generated as a result of establishing frame synchronization for data string 3 and outputs timing signal 2; 102 is a separation circuit that separates multi-frame pattern 4 in data string 3 using timing signal 2; The circuit 103 is an address generation circuit which outputs an address for the multi-frame pattern 4, that is, an address 5 representing the position within the multi-frame of the frame in which the multi-frame pattern 4 was included. 1
04 is an expected value generation circuit, which adds address 5, holds address 5 for multi-frame pattern 4 to be separated by separation circuit 102 in the next cycle using timing signal 2, and outputs it as expected value 6. be.

105 is a comparison circuit that compares address 5 itself and address 5.
A circuit that compares the expected value 6 of 1 and outputs a comparison result 7, 10
6 is a protection circuit, which performs synchronization protection based on comparison result 7 and timing signal 2, and outputs synchronization information 8; 107 is a multi-frame timing generation circuit, which protects synchronization using comparison result 7 and timing signal 2; and 107, a multi-frame timing generation circuit; Address 5. This circuit establishes multiframe synchronization for the data string 3 based on the comparison result 7 and synchronization information 8, and generates a multiframe timing signal 9.

Next, referring to the frame format in Figure 2,
The operation of the illustrated embodiment will be explained.

In Fig. 2, F is a frame pattern, MF1 to MF
, represent n (in the case of FIG. 2, n is equal to the number of frames in one multiframe) distinguishable multiframe patterns, and DATA represents the main signal to be transmitted.

The relative relationship between frame pulse 1 and data string 3 is determined after frame synchronization is established.

According to the timing signal 2 output from the timing signal generation circuit 101, the separation circuit 102 separates the multi-frame pattern 4 (MF+ in this case) in the data string 3.

Since the multi-frame pattern 4 is different for each frame, if the multi-frame pattern (MFl) 4 can be identified, it can be determined which frame of the multi-frame the multi-frame pattern is. The address generation circuit 103 inputs the separated multi-frame pattern (MFI) 4,
During what frame of multiframe (determine whether it is a turn,
Address 5 corresponding to the i-th frame in the multi-frame
The 0 expected value generating circuit 104 that outputs the address 5 inputs the address 5, adds +1, and holds the expected value 6 corresponding to the i+1th frame. If l or ) is output, the address generation circuit 103 outputs address 5 corresponding to the i+1th frame. As a result, comparison circuit 1
05 compares address 5 and expected value 6 and outputs a match as comparison result 7. If the multi-frame pattern 4 output from the separation circuit 102 is other than MF++, the address generation circuit 103 outputs address 5 other than the i+1th frame, so the comparison circuit 105 compares address 5 and expected value 6. do not match, and a mismatch is output as comparison result 7. The protection circuit 106 protects multiframe synchronization based on the comparison result 7. The multi-frame timing generation circuit 107 receives timing signal 2, address 5. Multiframe synchronization is established for data string 3 according to comparison result 7 and synchronization information 8, and multiframe timing signal 9 is output.

As explained above, the embodiment shown in FIG. 1 generates an address corresponding to a multi-frame pattern and holds the next address as an expected value in the circuit, so multiple multi-frame pattern detection circuits You can respond without having to have one.

Furthermore, if a ROM or the like is used as the address generation circuit, it is highly expandable and can easily accommodate additions and changes to multi-frame patterns.

Furthermore, although we have described the case where the number N of frames constituting one multiframe is equal to the number n of multiframe patterns, for example, even if N/4 = n, the addition in the expected value generation circuit 104 is set to +4. By doing so, you can obtain the expected value in the same way, and the same effect can be obtained.

Furthermore, regarding the separation of multi-frame patterns, M F
Although the explanation was limited to the case where I is separated, (MF +
10MF l+2 +MF ++3 +MF +. 4)
Even when a multi-frame pattern is separated across multiple frames, such as (MF, -, +MF +
+ MF +42 + MF ++3) and (MF, +MF I+(+ MF +12 +
If a multi-frame pattern is used that makes it possible to distinguish the combination of M F I +3 >, the expected value can be obtained in the same way, and the same effect can be obtained.

FIG. 3 is a block diagram showing a second embodiment of the invention.

The embodiment shown in FIG. 3 is similar to the expected value generation circuit 104 and the multi-frame timing generation circuit 1 of the embodiment shown in FIG.
07 is replaced with a multi-frame timing generation circuit 108.

The multi-frame timing generation circuit 108 generates timing signals 2. Address 5 based on comparison result 7 and synchronization information 8
This circuit determines whether or not to take the data into the data string 3, establishes multi-frame synchronization with the data string 3, and outputs a reference address 10 indicating the reference multi-frame address and a multi-frame timing signal 9. The other circuits are the same as those in FIG.

Judging from the comparison result 7 and the synchronization information 8, which are signals representing the state of synchronization, the multiframe timing generation circuit 108 runs by the timing signal 2 and generates the reference address 10 and the multiframe except during the hunting process of multiframe synchronization. A timing signal 9 is output. On the other hand, in the hunting process, address 5 for multi-frame pattern 4 is taken in as an internal multi-frame address, the address 5 is used as a reference, timing signal 2 is used to operate, and reference address 10 is output. That is, in the synchronization process other than the hunting process, the forward protection process, and the backward protection process, the reference address 10 is outputted in a self-running manner, and in the hunting process, the reference address 10 is outputted in the same manner as the expected value generation circuit 104 in FIG. . Comparison circuit 105 compares address 5 with reference address 10 and outputs comparison result 7.

As explained above, the embodiment shown in FIG. 3 also generates an address corresponding to a multi-frame pattern and compares it with the reference address output from the multi-frame timing generation circuit 108, so multiple multi-frame patterns can be detected. This can be done without the need for a circuit, and by using a ROM or the like as the address generation circuit, it is highly expandable and can easily accommodate additions and changes to multi-frame patterns.

Further, even when N/4=n, for example, if comparison is performed every four frames, similar comparison results can be obtained and similar effects can be obtained.

Furthermore, even when the multi-frame pattern is separated over multiple frames (
MF + 10MF I+1+MF I+z +MFI+
3> and (MF +-1+MF + +MF r or 1+M
If a multi-frame pattern is configured so that Fμ2) can be separately identified, a reference address can be obtained in the hunting process as well, and the same effect can be obtained.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

The embodiment shown in FIG. 4 replaces the expected value generation circuit 104 and comparison circuit 105 of the embodiment shown in FIG.
9 and a comparison circuit 110.

The expected value generation circuit 109 is a circuit that generates another multi-frame pattern to be separated and outputted from the separation port 1?8102 in the next cycle based on the multi-frame pattern 4, holds it using the timing signal 2, and outputs it as an expected value 11. It is. The comparison circuit 110 is a circuit that compares the multi-frame pattern 4 itself from the separation circuit 102 with the expected value 11 predicted and generated by the expected value generation circuit 109 based on the previous multi-frame pattern, and outputs a comparison result 7. . The other circuits are the same as those in FIG.

Whereas the embodiment shown in FIG. 4 compares the multi-frame pattern 4 itself from the separation circuit 102 and the expected value 11 of the multi-pattern generated by the expected value generation circuit 109 in the comparison circuit 110, a comparison result 7 is obtained. 1, except that the comparison circuit 105 compares the address 5 from the address generation port BIO3 and the expected value 6 of the address generated by the expected value generation circuit 104 to obtain the comparison result 7. In other words, the operation of the embodiment of FIG. 4 is the same as that of the embodiment of FIG.

As explained above, the embodiment shown in FIG.
Figure 1 shows that since the multi-frame pattern that is to come in the next cycle is predicted using the multi-frame pattern separated in step 02 and held as an expected value, it can be handled without the need for multiple multi-frame pattern detection circuits. This is the same as in the embodiment.

Furthermore, if a ROM or the like is used as the address generation circuit 1039 and the expected value generation circuit 109, it is highly expandable, and the addition and change of multi-frame patterns and the multi-frame period depend only on the capacity and contents of these ROMs. This can be easily accommodated.

Furthermore, even if we set N/4 = n, for example, the multi-frame pattern that should be predicted and generated as an expected value is 4.
If it is set after the period, it can be handled in the same way.

Furthermore, even when a multi-frame pattern is separated over multiple frames, (MF, +MF,
M F I +2 + M F μ3
) and (MF+-+ +MF l+MF ++t
Similarly to the embodiment shown in FIG. 1, if the multi-frame pattern is configured so that the ``+MF ++z'' can be separately identified, the same thing can be done.

〔Effect of the invention〕

As explained above, the first invention inputs a plurality of multi-frame patterns to an address generation circuit, generates an address in the multi-frame corresponding to the multi-frame pattern, and compares it with an internal multi-frame address serving as a reference. In addition, the second invention predicts the multi-frame pattern that will come in the next cycle from the input multi-frame pattern, holds it in the circuit as a special price, compares it, and synchronizes. By establishing this, both inventions can establish multiframe synchronization with a small circuit scale even when the types of multiframe patterns increase, and without having multiple multiframe pattern detection circuits. Also, since the multi-frame pattern corresponds to the address, it is possible to easily create a multi-frame timing signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
The figure is a diagram for explaining the frame format of data string 3 in FIG. 1, and FIGS.
FIG. 3 is a block diagram showing an example and a third example, respectively. 101... Timing signal generation circuit, 102... Separation circuit, 103... Address generation circuit, 104, 10
9...Expected value generation circuit, 105, 110-comparison circuit,
106... Protection circuit, 107, 108... Multi-frame timing generation circuit.

Claims (1)

[Claims] 1. Multiframe timing is determined by inputting a data string including a different multiframe synchronization pattern and a frame pulse of the frames to at least two frames among a plurality of frames constituting one multiframe. In a multi-frame synchronization circuit that outputs a signal, a timing generation circuit that outputs a timing signal of the multi-frame synchronization pattern based on the frame pulse, and a separation circuit that separates the multi-frame synchronization pattern from the data string based on the timing signal. and an address generation circuit that generates an address indicating where in the multiframe the frame that included the multiframe synchronization pattern from this separation circuit is located, and the address from this address generation circuit and the address. a comparison circuit that compares the expected value of and outputs a comparison result; a protection circuit that outputs multiframe synchronization protection information based on the comparison result; and the multiframe synchronization protection information, the comparison result, the address, and the timing signal. A multi-frame synchronization circuit comprising: a multi-frame timing generation circuit that outputs the expected value of the address and the multi-frame timing signal based on the multi-frame timing signal. 2. The multi-frame timing generation circuit includes an expected address value generation circuit that adds a predetermined number to the address input from the address generation circuit and outputs the result as an expected value of the address to be input next. The multi-frame synchronization circuit according to claim 1. 3. The multi-frame timing generation circuit adds a predetermined number to the address input from the address generation circuit in the multi-frame synchronization hunting process and outputs the expected value of the address, and in other than the hunting process, the 2. The multi-frame synchronization circuit according to claim 1, wherein the multi-frame synchronization circuit generates the expected value of the address by self-running in synchronization with a timing signal. 4. A multiframe that outputs a multiframe timing signal by inputting data strings each containing a different multiframe synchronization pattern and the frame pulse of the frame to at least two of the plurality of frames constituting one multiframe. The synchronization circuit includes: a timing generation circuit that outputs a timing signal of the multi-frame synchronization pattern based on the frame pulse; a separation circuit that separates the multi-frame synchronization pattern from the data string based on the timing signal; an address generation circuit that generates an address indicating where in the multiframe the frame in which the multiframe synchronization pattern was included is located; A multi-frame synchronization pattern expected value generation circuit that outputs the multi-frame synchronization pattern as an expected value, and a comparison between the expected value from this multi-frame synchronization pattern expected value generation circuit and the multi-frame synchronization pattern from the separation circuit. a protection circuit that outputs multiframe synchronization protection information based on the comparison result; and a protection circuit that outputs multiframe synchronization protection information based on the comparison result, the multiframe timing based on the multiframe synchronization protection information, the comparison result, the address, and the timing signal. A multi-frame synchronization circuit comprising a multi-frame timing generation circuit that outputs a signal.