JPH04252068A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the storage capacitance of a semiconductor device having a static capacitor as well as to improve the yield of the device. CONSTITUTION:A semiconductor device is constituted comprising a capacitor Q constituted of a storage electrode 4 formed by providing extendedly conductive fins 4b toward the internal direction and the external direction from the peripheral walls of a bottomed cylinder-shaped conductive film 4a provided on a semiconductor layer (a silicon substrate) 2, a storage electrode 28 formed by extending outside the conductive fins toward the internal direction and the external direction from both sidewalls of the conductive film of a U-shaped section provided on the layer 2 or counter electrode 42 formed into a lattice type section on the layer 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a static capacitor.

0002

2. Description of the Related Art In order to increase the storage capacity of a capacitor in a dynamic RAM, various structures have been proposed for a static capacitor provided on a diffusion layer 81 of a transfer transistor 80, as shown in FIG. ing.

For example, as shown in FIG. 8A, a dielectric layer 83 is grown along the surface of a cylindrical storage electrode 82.
A capacitor having a structure on which a counter electrode 84 is formed,
As shown in FIG. 2B, a cell is formed in which a storage electrode 85 having outwardly extending fins is formed on a diffusion layer 81, and a dielectric layer 86 and a counter electrode 87 are provided around the storage electrode 85.
As shown in FIG. 8C, a box-shaped storage electrode 89 having an opening 88 on the top surface is provided, the bottom surface of which is connected to the diffusion layer 81, and a dielectric layer 90 and a counter electrode 9 are formed around it.
There is a capacitor that provides 1.

Next, the manufacturing process of the above cell will be briefly explained. FIG. 10 is a cross-sectional view showing the process of forming the cylindrical storage electrode 82. First, as shown in FIG. After stacking the silicon film 93, it is patterned to provide a window 94 on one diffusion layer 81 of the transfer transistor 80 (FIG. 10(A)).

Next, after patterning the interlayer insulating film 92 to form an opening 95 smaller than the window 94 therein (see (B) in the same figure), a second polycrystalline silicon film 96 is laminated over the entire surface. (Figure (C)).

Following this, two polycrystalline silicon films 9
By patterning the polycrystalline silicon films 93 and 96, the polycrystalline silicon films 93 and 96 are left on and around the diffusion layer 81 (FIG. 3(D)). As a result, a cylindrical storage electrode 82 made of polycrystalline silicon is completed.

After this, the surface of the storage electrode 82 is thermally oxidized to grow SiO2, and this is formed into a dielectric film 83 as shown in FIG. An electrode 84 is used.

FIG. 11 is a cross-sectional view showing the process of forming a storage electrode 85 having a fin structure. First, as shown in FIG. 2A, the upper layer of the interlayer insulating film 92 is formed of silicon nitride, and then a SiO2 film 97, a polycrystalline silicon film 98, and an SiO2 film 99 are formed in this order. An opening 100 is formed above the diffusion layer 81 by patterning the interlayer insulating film 92 and the layers 97 to 99 thereon.

Next, inside the opening 100 and the SiO2 film 99
After laminating a second polycrystalline silicon film 101 thereon (FIG. 11(B)), further polycrystalline silicon films 98, 1
01 and SiO2 films 07 and 99 are patterned by photolithography, thereby leaving these films on and around the diffusion layer 81 (FIG. 11(C)).
).

After this, SiO2 on the interlayer insulating film 92 is
If the films 97 and 99 are selectively removed using hydrofluoric acid, the result shown in FIG.
A storage electrode 85 having a fin structure as shown in FIG. 11(B) is formed (FIG. 11(D)). Next, a dielectric layer 86 and a counter electrode 87 are formed on the surface of the storage electrode 85.

FIG. 12 is a cross-sectional view showing the process of forming the box-shaped storage electrode 90, in which a first polycrystalline silicon film is formed on the diffusion layer 81 of the transfer transistor 80 and on the interlayer insulating film 92 around it. After patterning 102, SiO
2 films 103, second polycrystalline silicon film 104 and S
The iO2 films 105 are sequentially stacked (FIG. 12(A)). Then, the three films 103 to 105 from the top are patterned to expose the peripheral region of the first polycrystalline silicon film 102 (FIG. 3(B)).

Next, a conductive sidewall 106 is formed to connect the side of the second polycrystalline silicon film 104 and the peripheral edge of the first polycrystalline silicon film 102, and two SiO2 films 103, 105 are formed. An opening 107 passing through is provided in the center (FIG. 1(C)).

After that, by supplying a hydrofluoric acid solution through the opening 107 and removing the SiO2 films 103 and 105, a box-shaped storage electrode 90 as shown in FIG. 8(C) is formed on the diffusion layer 81. ((D) in the same figure).

[0014]

[Problem to be solved by the invention] By the way, FIG. 8(A)
In a cell with a structure as shown in FIG. 1, in order to increase the storage capacity of the capacitor, it is necessary to make the storage electrode 82 higher. However, this increases the height difference between the storage electrode 82 and the interlayer insulating film 92. There is a problem in that the resolution decreases in the exposure process when forming the contact hole 92.

On the other hand, according to a cell having a structure as shown in FIG. 8(B), the storage capacity can be increased by increasing the area of the fins in the lateral direction.

However, if the fins of the storage electrode 85 are made thinner in order to suppress the height of the capacitor, the mechanical strength of the fins becomes weaker, and as shown in FIG. There is a problem that the interlayer insulating film 92 is likely to come into contact with the interlayer insulating film 92, resulting in a decrease in yield.

Furthermore, in the case of the box-shaped capacitor shown in FIG. 8(C), the capacitance can be increased by narrowing the opening 88 of the storage electrode 89 and increasing the lateral area; Since the etching solution is supplied and discharged from the storage electrode 88, etching residue is likely to be formed inside the storage electrode 89, resulting in a disadvantage that the yield is reduced.

The present invention has been made in view of these problems, and it is an object of the present invention to provide a semiconductor device having a structure capable of increasing storage capacity and improving its yield.

[0019]

[Means for solving the problem] The above problem can be solved as shown in Figure 2 (
H) As illustrated in FIG. The counter electrode 4
This is achieved by a semiconductor device having a capacitor Q constituted by a dielectric film 7 covering the dielectric film 7 and a counter electrode 8 stacked around the dielectric film 7.

Alternatively, as illustrated in FIG. 5(I),
A storage electrode 28 having conductive fins extending inwardly and outwardly from both side walls of a conductive film having a U-shaped cross section provided on the semiconductor layer 2; and a dielectric film 29 covering the counter electrode 28. This is achieved by a semiconductor device having a capacitor Q formed of a dielectric film 29 and a counter electrode 30 stacked around the dielectric film 29.

Alternatively, as illustrated in FIG. 7(F),
A counter electrode 42 formed in a cross-sectional lattice shape on the semiconductor layer 2 , a dielectric film 43 covering the counter electrode 42 , and a dielectric film 4
This is achieved by a semiconductor device having a capacitor Q formed by a counter electrode 44 stacked around a capacitor Q3.

[0022]

[Function] According to the first invention, the bottomed cylindrical conductive film 4
By extending conductive fins 4b inwardly and outwardly from the peripheral wall of capacitor Q, the counter electrode 4 of capacitor Q is
is formed.

For this reason, the fins 4 constituting the storage electrode 4
fins 4b are supported at or near the center of the fins 4b rather than at their ends, making them difficult to bend even if the fins 4b are made thinner.

Moreover, compared to the conventional device shown in FIG. 8(B), since only the support position of the fins has been changed, the storage capacity can be increased without reducing the surface area.

Furthermore, when the etching solution is supplied between the fins provided inside the bottomed cylindrical conductive layer 4a, the area of the fins is formed to be narrow, making it difficult for residue to form inside the fins. .

According to the second invention, conductive fins are formed inwardly and outwardly from both side walls of the conductive film having a U-shaped cross section, and these conductive fins are used as the storage electrodes 28.

Therefore, for the same reason as in the first invention, the fins are less likely to bend, and the storage capacity is increased.

According to the third invention, the storage electrode 42 is formed in a lattice-like cross-section. Therefore, the mechanical strength of the storage electrode 42 of the capacitor Q becomes stronger, and the lateral fins can be made larger accordingly to increase the storage capacitance.

[0029]

[Example] (a) Explanation of the first embodiment of the present invention Figures 1 and 2 are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and Figure 2 (H) shows the completed device by this process. A cross-section of the device is shown.

In FIG. 2(H), reference numeral 1 denotes a DRAM transfer transistor formed on a p-type silicon substrate 2, and a capacitor Q is formed on an interlayer insulating film 3 covering this transfer transistor 1. The storage electrode 4 constituting the capacitor Q is connected to one side of the n+ type diffusion layer 6 of the transfer transistor 1 through the contact hole 5 of the interlayer insulating film 3.

Furthermore, the storage electrode 4 is connected to the contact hole 5.
It has a bottomed cylindrical conductive film 4a formed in a region including the conductive film 4a, and fins 4b protruding inwardly and outwardly from its peripheral wall. A counter electrode 8 made of conductive polycrystalline silicon is provided,
These constitute a capacitor Q.

In the figure, reference numeral G denotes a word line gate electrode of the transfer transistor 1 formed on the silicon substrate 2 via an insulating film 9, and 10 denotes a word line gate electrode formed on the upper surface of the silicon substrate 2 in a region surrounding the transfer transistor 1. This is a selective oxide film.

In this embodiment, since the fins 4b constituting the storage electrode 4 are supported by the conductive film 4a at or near the center rather than at the ends, the fins 4b
Even if b is made thinner, it will not curve, and since the supporting position is simply changed, the storage capacity can be increased without reducing the surface area.

Next, the manufacturing process of the above-mentioned embodiment device will be explained. First, as shown in FIG. 1(A), a transfer transistor 1 is placed on a silicon substrate 2 surrounded by a selective oxide film 10.
After forming, an interlayer insulating film 3 is laminated thereon. In this case, the upper layer of the interlayer insulating film 3 is made of silicon nitride.

The interlayer insulating film 3 is then patterned by photolithography to form a contact hole 5 on one side of the n-type diffusion layer 6 which will become the source/drain of the transfer transistor 1.

Next, first to third polycrystalline silicon films 11,
12 and 13 are laminated by CVD to a thickness of about 1000 Å each (FIG. 1(B)). For example, its growth temperature is 6
The temperature is around 00°C and the growth pressure is 0.2 Torr.

In this case, polycrystalline silicon is grown using SiH4 gas, but when growing the second polycrystalline silicon film 12, PCl3 gas is supplied to increase the concentration of phosphorus in the film to 1×1021. /cm3.

Thereafter, a photoresist 14 is applied, exposed and developed to form a mask covering the contact hole 5 and its surroundings. Then, the first to third polycrystalline silicon films 11 to 13 exposed from the photoresist 14 are etched away by reactive ion etching (RIE) using chlorine gas (FIG. 1C).

Next, after removing the photoresist 14, the polycrystalline silicon film 13 on the contact hole 5 is removed.
A resist mask 16 is formed with a window 15 exposing the area (FIG. 1(D)).

Thereafter, the first and second polycrystalline silicon films 12 and 13 exposed through the window 15 are etched by RIE to form an opening 17 in the center of these films 12 and 13.
(Fig. 2(E)). In this case, a chlorine-based gas is used as the etching gas.

Next, when an etching solution containing nitric acid and hydrofluoric acid is supplied to the polycrystalline silicon films 11 to 13, the second polycrystalline silicon film 12 containing phosphorus is etched laterally from the outside and inside the opening 17. It is selectively etched and its area is reduced to become narrower than the other polycrystalline silicon films 11 and 13 (FIG. 2(F)). On the other hand, the non-doped polycrystalline silicon films 11 and 13 have a small etching rate and the degree of shrinkage is small.

By the way, the concentration of phosphorus is 1×1021/cm
In the case of No. 3, the etching rate is 40 nm/min, and in the case of non-doping, it is 5 nm/min.

The polycrystalline silicon films 11 to 13 patterned in this manner are used as the storage electrode 4, and its shape is such that two fins 4b are protruded from both sides of the peripheral wall of the conductive film 4a in the shape of a cylinder with a bottom. Become something.

Next, in order to impart conductivity to the storage electrode 4, phosphorus is ion-implanted and activated by heat.

Then, the surface of the storage electrode 4 is thermally oxidized to form a dielectric film 7 (FIG. 2(G)), and polycrystalline silicon containing phosphorus is further grown around it to form a counter electrode 8. (Figure 2(H)).

By the way, the fins 4 constituting the storage electrode 4
Since b is supported by the conductive film 4a at its center, it does not curve during the manufacturing process, and the yield is greatly improved. Furthermore, in the storage electrode 4, since the fins 4b extend in the inner and outer directions of the conductive film 4a, a sufficient surface area can be secured even if the area of the fins 4b extending inside is narrowed, and the second polycrystalline silicon film 12 can be During etching, the etching solution reaches the internal corners through the opening 17, making it difficult for residue to form inside.

In the above-described embodiment, the storage electrode 4 is formed by providing the fins 4b on the inner and outer sides of the peripheral wall of the conductive film 4a having a cylindrical shape with a bottom. A support membrane may be provided, and fins may be formed protruding from both sides of the two side walls. Its cross-sectional shape is shown in Figure 2 (H).
becomes the same as

(b) Description of the second embodiment of the present invention The device of the above embodiment has a structure with two fins, but it is also possible to have a plurality of fins.

Next, a method for forming three fins using a process different from that of the first embodiment will be described with reference to FIGS. 3 to 5.

First, as in the first embodiment, a transfer transistor 1 is formed in a region of a p-type silicon substrate 2 surrounded by a selective oxide film 10, and is further covered with an interlayer insulating film 3. is patterned to form a contact hole 5 on the n+ type diffusion layer 6 (see FIG. 3(
A)).

Next, the polycrystalline silicon film 20 containing phosphorus is
After stacking about 000 Å, this is patterned to remain on the interlayer insulating film 3 in and around the contact hole 5 (FIG. 3(B)).

After this, a film thickness of 1000 Å was formed by CVD method.
5 layers of PSG films 21 to 25 are stacked (Fig. 3(C)
)). In this case, the film growth temperature is, for example, 670° C., and the gas pressure is about 0.6 Torr. In addition, the growth gas includes Si(OC2H5)4, P(OCH3)3,0
A mixed gas of 2 is used, but the ratio of the mixed gas is changed for each layer, and the PSG films 21, 23, and 2 of the first, third, and fifth layers are used.
5, the phosphorus content is 5.0 wt%,
When depositing the second and fourth PSG films 22 and 24, the phosphorus content is set to 8. Adjust to 5wt%.

Next, a resist mask 19 having a window is provided in a region surrounding the contact hole 5, and the PSG films 21 to 25 exposed through the window are etched by RIE to form a cylindrical opening 26 (see FIG. 4(D)).

After this, the resist mask 19 is removed, and
Next, the PSG films 21 to 25 are immersed in a hydrofluoric acid solution, and the second and fourth PSG films 22 and 24, which have a high phosphorus concentration, are etched laterally from the opening 26 to form a cylindrical opening. Inward and outward protrusions are formed in the portion 26 as the PSG films 22 and 24 are reduced in size (FIG. 4(E)).

By the way, 22 of the PSG film with a high phosphorus concentration,
The etching rate of PSG film 24 is about 2800 Å/min, but the etching rate of the other PSG films 21, 23, and 25 is about 100 Å/min, and the second and fourth PSG films 22 and 24 are selectively etched. That will happen.

Next, a polycrystalline silicon film 27 containing phosphorus is grown by the CVD method, and the inside of the opening 26 is filled with the polycrystalline silicon film 27 (FIG. 4(F)).

Furthermore, the polycrystalline silicon film 27 on the fifth layer PSG film 25 is removed by RIE using chlorine-based gas (FIG. 5(G)), and then all the PSG films 21 to 25 are removed. 25 is removed with a hydrofluoric acid solution (Figure 5 (H))
.

As a result, the polycrystalline silicon 20 and 27 remain on the substrate 2, and a storage electrode 28 having three fins is formed, the shape of which is the same as in the first embodiment.

Thereafter, the surface of the storage electrode 28 is thermally oxidized to form SiO2, which is used as a dielectric film 29, and a counter electrode 30 made of polycrystalline silicon is grown on the surface (see FIG. 5(I)). )).

In the above embodiment, the storage electrode 28 having three fins was formed by alternately laminating five layers of PSG films with high phosphorus concentration and PSG films with low phosphorus concentration. It is of course possible to increase the number of sheets.

Furthermore, the openings 26 formed in the PSG films 21 to 25 are not limited to the cylindrical shape;
Two opposing openings may be provided in the area sandwiching the area. According to this, as already explained in the first embodiment, a storage electrode having a shape in which a plurality of fins are attached to the side wall of a conductive layer having a U-shaped cross section is formed.

(C) Explanatory diagrams 6 and 7 of the third embodiment of the present invention
FIG. 3 is a cross-sectional view showing the manufacturing process of a device according to a third embodiment of the present invention.

First, as in the first and second embodiments shown in FIGS. 1A and 3A, a transfer transistor 1 is formed on a silicon substrate 2, and a contact hole is formed to expose the n+ type diffusion layer 6. An interlayer insulating film 3 is formed. Note that the upper layer portion of the interlayer insulating film 3 is made of silicon nitride.

In this state, the polycrystalline silicon film 3 containing phosphorus
1, 33 and SiO2 films 32, 34, two layers each 10
The film is grown to a thickness of 00 Å. And contact hole 5
A resist mask 37 having two windows 35 and 36 is formed on the interlayer insulating film 3 on both sides (FIG. 6(A)).

Next, the windows 35 and 36 of the resist mask 37
The SiO2 films 32, 34 and polycrystalline silicon films 31, 33 exposed from the opening 3 are etched by RIE method.
8 and 39 are formed, and then the resist mask 37 is removed (FIG. 6(B)).

After this, silicon containing phosphorus is grown by the CVD method to form a polycrystalline silicon film 40 inside the openings 38 and 39 and on the uppermost SiO2 film 33 (FIG. 6(C)). ).

Next, after forming a resist mask 41 covering the region between the two openings 38 and 39 and the outer periphery thereof, the SiO2 film 32 exposed from the resist mask 41 is
, 34 and the polycrystalline silicon films 31, 33, and 40 are etched by RIE, and then the resist mask 41 is removed (FIG. 7(D)).

After this, the interlayer insulating film 3 is coated with a hydrofluoric acid solution.
The upper SiO2 films 32, 34 are selectively etched away, and the remaining polycrystalline silicon 31, 33, 40 forms a storage electrode 42 of the capacitor (FIG. 7(E)).

Subsequently, the surface of the storage electrode 42 is thermally oxidized to form a dielectric film 43 made of SiO2, and a counter electrode 44 is further formed from polycrystalline silicon containing phosphorus, thereby forming the capacitor Q. do.

By the way, since the storage electrode 42 of the capacitor Q has a lattice-like cross-section, its mechanical strength is strong, and the lateral fins can be increased accordingly, so that the surface area of the storage electrode 42 can be increased. It also becomes possible.

Note that in the above three embodiments, the dielectric film 7
, 29, and 43 were formed by thermally oxidized SiO2 films, but
A CVDSiO2 film or a CVD nitride film may also be used.

[0072]

[Effect of the invention] As described above, according to the first invention,
The opposing electrode of the capacitor is formed by extending conductive fins inward and outward from the peripheral wall of the bottomed cylindrical conductive film, so the fins constituting the storage electrode are The fins are supported not at the ends but at or near the center, making it difficult for the fins to curve.

Furthermore, compared to the conventional device shown in FIG. 8(B), the storage capacity can be increased without reducing the surface area because the supporting position of the fins has only been changed.

[0074] Furthermore, when the etching solution is supplied between the fins provided inside the bottomed cylindrical conductive layer, since the area of the fins is narrow, it is difficult to form a residue inside the fins. It becomes possible.

According to the second invention, conductive fins are formed inwardly and outwardly from both side walls of the conductive film having a U-shaped cross section, and these are used as storage electrodes. For the same reason as in the invention, the storage capacity can be increased by making the fins less likely to curve.

According to the third invention, since the storage electrode is formed in a cross-sectional lattice shape, the mechanical strength of the storage electrode of the capacitor is increased, and the horizontal fins are correspondingly enlarged to increase the storage capacity. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view (part 1) showing the manufacturing process of a device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view (Part 2) showing the manufacturing process of the device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view (part 1) showing the manufacturing process of the device according to the second embodiment of the present invention.

FIG. 4 is a cross-sectional view (Part 2) showing the manufacturing process of the device according to the second embodiment of the present invention.

FIG. 5 is a sectional view (part 3) showing the manufacturing process of the device according to the second embodiment of the present invention.

FIG. 6 is a sectional view (part 1) showing the manufacturing process of the device according to the third embodiment of the present invention.

FIG. 7 is a cross-sectional view (Part 2) showing the manufacturing process of the device according to the third embodiment of the present invention.

FIG. 8 is a sectional view showing first to third examples of conventional devices.

FIG. 9 is an enlarged sectional view showing problems with the conventional device.

FIG. 10 is a sectional view showing the manufacturing process of a first example of a conventional device.

FIG. 11 is a sectional view showing the manufacturing process of a second example of the conventional device.

FIG. 12 is a sectional view showing the manufacturing process of a third example of the conventional device.

[Explanation of symbols]

1 Transfer transistor 2 Silicon substrate (semiconductor layer) 3
Interlayer insulating film 4 Storage electrode 5 Contact hole 6 N+ type diffusion layer 7 Dielectric film 8 Counter electrode 28, 42 Storage electrode 29, 43 Dielectric film 30, 44 Counter electrode

Claims (3)

[Claims] 1. A storage electrode formed by extending conductive fins (4b) inwardly and outwardly from the peripheral wall of a bottomed cylindrical conductive film (4a) provided on a semiconductor layer (2). (4), a dielectric film (7) covering the counter electrode (4), and a dielectric film (7) covering the counter electrode (4).
) and a counter electrode (8) stacked around the capacitor (Q). 2. A storage electrode (28) formed by conductive fins extending inwardly and outwardly from both side walls of a conductive film with a U-shaped cross section provided on the semiconductor layer (2); Electrode (28
) and a counter electrode (30) stacked around the dielectric film (29). 3. A counter electrode (42) formed in a cross-sectional grid shape on the semiconductor layer (2), a dielectric film (43) covering the counter electrode (42), and the dielectric film (43). A semiconductor device having a capacitor (Q) formed by a counter electrode (44) stacked around the capacitor (Q).