JPH04251493A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To independently process the plural kinds of data by one chip without any synchronism correcting circuit by independently operating a data input circuit and a data output circuit synchronously with a data write clock and a read clock. CONSTITUTION:When writing data, for the data of data input terminals Din 0-5, the data of high-order 4 bits and low-order 2 bits among the data of 6 bits are written through a data input buffer 102 to a 770 bit write data register 105 synchronously with serial write clocks SWC1 and SWC2. When reading data from a read data register 113, the data of high-order 4 bits and low-order 2 bits in the data of 6 bits are outputted through a data output buffer 116 to data output terminals Dout 0-5 synchronously with serial read clocks SRC1 and SRC2.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and is particularly characterized in that input/output processing of a plurality of types of data is performed independently and asynchronously within one chip. 2. Description of the Related Art At present, with the advancement of digitalization in the field of video, it has become popular to perform digital image processing using an image memory in video devices such as video tape recorders. [0003] The video signal consists of a luminance signal (hereinafter referred to as Y signal) and a color difference signal (hereinafter referred to as C signal), and during digital signal processing, the Y signal is 910 times the horizontal scanning frequency (hereinafter referred to as fH) of 15.75 kilohertz. Generally, the C signal is controlled at a frequency of 4fsc, which is four times the color subcarrier frequency (hereinafter referred to as fsc) of 3.58 MHz. The value of 910fH and the value of 4fsc are both 14.3 MHz, which is the same value theoretically, but 910fH locks to fH and 4fsc locks to fsc, and because they are created by separate circuits, there is actually a phase difference. is occurring. [0004] When processing image information using a memory with a dual port configuration, such as Matsushita Electric Co., Ltd.'s MN-4700 and NEC Corporation's μPD42270, each having only one system of serial read/serial write ports,
Methods that have been adopted include synchronizing the processing of the Y signal and the C signal using one system of clock signal control, or providing a memory for signal processing of the Y signal and the C signal, respectively. However, in the single system clock signal control method, a phase difference correction circuit must be provided. Furthermore, if memories are provided for each of a plurality of signals, there may be problems such as increased costs. Problems to be Solved by the Invention [0006] In the image memory of the prior art described above, when processing multiple signals such as the Y signal and the C signal, if one chip attempts to process the signals, one system of clock signals must be controlled. Errors occur because the synchronization is performed using a synchronization method, and a peripheral circuit for synchronization correction must be added. [0007] Furthermore, if separate memories are used for each signal processing, a problem arises in that the cost increases. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory that can input and output a plurality of types of data within one memory by independently controlling clock signals without requiring a correction circuit. [Means for Solving the Problems] The present invention includes a plurality of data write clock inputs that can operate independently, and a plurality of data input circuits that input data in synchronization with the data write clocks. It has a plurality of data read clock inputs and a plurality of data output circuits that output data in synchronization with the data read clocks. According to the above structure, the data input circuit operates in synchronization with a plurality of data write clocks, and the data output circuit operates in synchronization with a plurality of data read clocks. Embodiment FIG. 1 shows a block diagram of an embodiment of the present invention. The memory cell array 101 has a configuration of 1155,000 bits (250 rows x 770 columns x 6 bits), approximately 1.2 megabits, which means that the NTSC television signal can be transmitted at four times the color subcarrier frequency (hereinafter referred to as fsc) of 3.58 MHz. The configuration corresponds to the effective screen area of a television receiver when sampling at a frequency of 4 fsc. Data is written to the data input terminal DTn.
0 to 5, and the first serial write clock (
Hereinafter, the upper 4 bits of the 6-bit data are synchronized with SWC1 (overline), and the lower 2 of the 6-bit data are synchronized with the second serial write clock (hereinafter referred to as SWC2 (overline)). Bit data is written via the data input buffer 102 to the position indicated by the pointer of the serial selector 104 on the 770-bit write data register 105 (hereinafter referred to as write data register) through the data transfer gate 180. In addition, the serial selector 104 selects two serial write clocks SWC1 ((overline)) input to the serial write control timing generation circuit 103.
), shifted in synchronization with SWC2 (Overline). FIG. 2 shows a timing chart of a serial write cycle. When the writing of data for one line (770×6 bits) to the write data register 105 is completed, the write data is transferred from the write data register 105 to the memory cell array 101. For write data transfer, stop the two serial write clocks SWC (Overline) and SWC2 (Overline),
A write enable signal (hereinafter referred to as WE (overline)) input to the read/write timing generation circuit 106
After setting the signal) to low level, the timing generation circuit 10
Row address strobe signal (hereinafter referred to as RA) input to
In synchronization with the fall of the S (overline signal), data in the write data register is transferred to the row of the memory cell array designated by the row address counter 108, which is a collection of 770×6 bits. The row to which data is transferred is designated by a row address signal output from a row address counter 108 via an address selector 109, an address input buffer 110, and an address decoder 111. The row address counter 108 is reset by the row count reset signal RCR (overline), and is reset by the increment signal INC (
One address is added by inputting the DEC signal (overline), and one address is subtracted by inputting the decrement signal DEC (overline). Write data register 1
FIG. 3 shows the timing of the write data transfer cycle from 05 to the memory cell array 101. Refreshing of the memory cell array 101 is performed for a row designated by a refresh address signal output from a refresh address counter 112 in response to a refresh signal REF (overline) input to a timing generation circuit 107. At this time, the RAS (overline) signal must be at a high level. 770-bit read data register from memory cell array 101 (hereinafter referred to as read data register)
Read data transfer to the memory cell array 101 is performed by setting the WE (overline) signal to high level and then in synchronization with the falling edge of the RAS (overline) signal, to one row in the memory cell array 101 specified by the row address counter 108. 770 minutes of data via the data transfer gate 181.
×6 bits are collectively transferred to the read data register 113. Data is read from the read data register 113 using the first serial read clock (hereinafter referred to as SR).
The upper 4 bits of the 6-bit data are synchronized with C1 (overline), and the lower 2 bits of the 6-bit data are synchronized with the second serial read clock (SRC2 (overline)). However, from the position indicated by the serial selector 115, the output buffer 116
The data are output to data output terminals Dout0 to Dout5. The serial selector 115 shifts in synchronization with two serial read clocks SRC1 (overline) and SRC2 (overline) input to the serial read control timing generation circuit 114. FIG. 4 shows a timing chart of a read data transfer cycle from the memory cell array 101 to the read data register 113, and FIG. 5 shows a timing chart of a serial read cycle. An overall timing chart for one embodiment is shown in FIG. FIG. 7 shows an application example of the semiconductor memory of this embodiment. As shown in the figure, two semiconductor memories of this embodiment are connected to data input terminals Din0 to Din5 and data output terminals D.
All terminals below out0 to out5 are connected to common. As a result, the memory has a configuration of 250 rows x 700 columns x 12 bits. This memory device is grounded inside a video tape recorder and used as a field memory for an NTSC TV. When performing television signal digital image processing, the brightness signal (hereinafter referred to as Y signal) is 1
For the horizontal scanning frequency (hereinafter referred to as fH) of 5.75 kilohertz, the frequency is 910 fH, or approximately 14.3 MHz, and for the color difference signal (hereinafter referred to as C signal), the color subcarrier frequency (hereinafter referred to as fsc) is 3.58 MHz. For 4f
It is common to control at a frequency of sc, that is, about 14.3 MHz. Therefore, in order to process the Y signal using the memory device of this embodiment, the clock control signal generated from 910fH is input to the SWC1 (Oher line) and SRC1 (Oher line) terminals, and the 8-bit data is input to the C For signal processing, the clock control signal generated from 4fsc is used.
It is input to the SWC2 (Overline) and SRC2 (Overline) terminals to perform signal control as 4-bit data. Here, the frequency bandwidth of the C signal is approximately 1.5 MHz, narrower than the frequency bandwidth of the Y signal of approximately 4.2 MHz, and does not require the same sampling rate as Y signal processing. reduces the sampling rate to 1/2. Furthermore, since the C signal is composed of two color difference signals (hereinafter referred to as R-Y signal and B-Y signal), the sampling rate for each of the R-Y signal and B-Y signal is 1/4 of that of the Y signal. It turns out that. Therefore, the 8-bit quantized C signal data is written to the serial write register or read from the serial read register twice for each 4-bit data. [0021] By using the above method, it becomes possible to process the Y signal and C signal independently and asynchronously.
Data processing based on multiple signals can be performed without providing independent memories or special synchronization circuits. To give an overview of the signal processing in this application example, for the Y signal, an 8-bit A-D converter 8
01 is 8-bit quantized at a sampling frequency of 910fH and generated from 910fH under SWC1 (overline) control to control Din0 to Din0 of each memory.
R-Y input as a total of 8-bit data from the Din3 terminal
As for the signal and the BY signal, the RY signal and the BY signal are first multiplexed by an analog signal multiplexer 802 under fsc control. The situation is shown in Figure 8 (A) (
Shown in B). The multiplexed analog RY signal and BY signal are 8-bit quantized by an 8-bit AD converter 803 at a sampling frequency of 2fsc, and a multiplexer 804 divides the 8-bit data into 4-bit data under 2fsc control. The state of the A/D conversion multiplex is shown in FIGS. 8(C) to 8(F). Then, R-
Y signal and B-Y signal are SWC2 generated from 4fsc
(Overline) and each Din4~
It is input as Din5, a total of 4 bits of data. Data reading is performed at 9 for the Y signal.
D in synchronization with 10fH SRC1 (Oher line)
From out0 to Dout3, the R-Y signal and B-Y signal are outputted from Dout4 to Dout5 in synchronization with 4fsc SRC2 (Oher line), and then the Y signal is outputted to 910 by an 8-bit D-A converter 806.
It is demodulated into an analog signal by fH control, and the R-Y signal and B-
For the Y signal, 4-bit data is demultiplexed into 8-bit data through the latch circuit 808, and then the R-
Regarding the Y signal, 8 is controlled by fsc (overline).
It is demodulated into an analog signal by a bit D-A converter 807, and the B-Y signal is converted into an 8-bit D-A converter by fsc control.
The A converter 809 demodulates the signal into an analog signal. [0025] According to the present invention, in the field of image processing, multiple types of data can be processed independently within one chip without the need for a synchronization correction circuit, and the number of memories used can be reduced. There is an effect that can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing a serial write cycle of one embodiment.

FIG. 3 is a timing chart showing a write data transfer cycle of one embodiment.

FIG. 4 is a timing chart showing a read data transfer cycle of one embodiment.

FIG. 5 is a timing chart showing a serial read cycle in one embodiment.

FIG. 6 is a comprehensive timing chart of one embodiment.

FIG. 7 is a block diagram showing an example of application of one embodiment.

FIG. 8 is a timing chart showing color difference signal processing in an applied example.

[Explanation of symbols]

101 Memory cell array 102 Data input buffer 103 Serial write control timing generation circuit 104 Serial selector 105 770-bit write data register 106
Read/write timing generation circuit 107 Timing generation circuit 108 Row address counter 109 Address selector 110 Address input buffer 111 Address decoder 112 Refresh address counter 113 7
70-bit read data register 114 Serial read control timing generation circuit 115 Serial selector 116 Data output buffer

Claims (1)

[Claims] 1. A plurality of data write clock inputs, a plurality of data input circuits that input data in synchronization with the data write clock, a plurality of data read clock inputs, and a plurality of data input circuits that input data in synchronization with the data read clock. 1. A semiconductor memory device comprising a plurality of data output circuits, the data input circuit and the data output circuit being able to operate independently in synchronization with a data write clock and a data read clock, respectively.