JPH0424965A - Image sensor - Google Patents

Abstract

PURPOSE:To prevent crosstalk between signal lines, and accurately read electric charge stored in capacitance of the signal lines, by decreasing electric influence between wirings in an image sensor of a thin film transistor(TFT) switching element type. CONSTITUTION:A wiring structure 13 is formed on both sides of a photodetector array 11, and a plurality of photodetector 11'' are divided to constitute one block. The wirings of signal lines 14 are connected in the order of the distance which is short between a switching element in a block and a switching element in the adjacent block. The wirings of signal lines are alternately arranged for the main scanning direction of the photodetector array 11 in each block unit. The shorter wirings of the connecting signal lines are arranged in order on the photodetector array 11 side, and wirings of constant potential are formed between signal lines. As the result, the signal lines do not intersect with each other, and the wirings of constant potential formed between signal lines arranged in parallel prevent crosstalk between signal lines.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image sensor used in facsimiles, scanners, etc., and more particularly to an image sensor having a wiring structure that reduces electrical influence between wirings.

(Prior Art) Some conventional image sensors, particularly contact type image sensors, project image information of a document or the like on a one-to-one basis and convert it into an electrical signal. In this case, the projected image is divided into a large number of pixels (light-receiving elements), and the charge generated by each light-receiving element is temporarily stored in the capacitance between wirings in specific blocks using thin film transistor switching elements (TPT). There is a TPT-driven image sensor that sequentially reads out electrical signals in time series at a speed of several hundred KH2 to several MH2.

The second TPT drive type image sensor is capable of reading with a single drive IC due to the operation of the TPT, so the number of drive ICs for driving the image sensor is reduced.

For example, as the equivalent circuit diagram of the TPT-driven image sensor is shown in FIG.
A plurality of thin film transistors Tj,j (i
-1 to N, j=1 to n);
It is composed of matrix-like multilayer wiring 53.

The light receiving element array 51 is divided into N blocks of light receiving element groups, and the n light receiving elements 51' forming one light receiving element group are photodiodes Pi,j (i=L
~N, j-1~n). Each light receiving element 51' is connected to the drain electrode of each thin film transistor T i,j, respectively. The source electrodes of the thin film transistors Ti, j are connected to n common signal lines 54 for each light receiving element group via multilayer wiring 53 connected in a matrix, and the common signal line 54 is connected to a driving IC 55. It is connected to the.

The gate electrode of each thin film transistor Ti, j is connected to a gate pulse generation circuit 56 so as to be electrically conductive for each block. After the photocharges generated in each photodetector 51' are accumulated in the parasitic capacitance of the photodetector and the overlap capacitance between the drain and gate of the thin film transistor for a certain period of time, the photocharges generated in each photodetector 51' are transferred block by block using thin film transistors Ti, j as switches for charge transfer. The wiring capacitance Cj(j−
1 to n) are transferred and stored.

That is, the keto pulse φ transmitted from the gate pulse generation circuit 56 via the gate signal lines Gj (i-1 to n)
Gl or the thin film transistor T1 of the first block. l
=TL,n is turned on, and each light receiving element 5 of the first block
The charges generated at 1' are transferred and accumulated in each wiring capacitor C4. Then, the potential of each common signal line 54 changes due to the charge accumulated in each wiring capacitor Cj, and this voltage value is applied to the driving IC.
The analog switches SWj (1-1-n) in 55 are sequentially turned on to extract the signal to the output line 57 in time series.

Then, by gate pulses φG2 to φcn, the second to Nth
Thin film transistors T2.1 to T2n to T
By turning on each of N,] to TN, and n, the charge on the light receiving element side is transferred block by block, and by reading them out sequentially, one line of image signal in the main scanning direction of the document is obtained, and the document is fed by rollers, etc. The original is moved by means (not shown) and the above operations are repeated to obtain an image signal of the entire original (see Japanese Patent Laid-Open No. 63-9358).

The structure of the matrix-shaped multilayer wiring 53 is as shown in FIG. 12, which is a plan view, and FIG. 13, which is a cross-sectional view. Insulating layer 33. It is constructed by sequentially forming upper layer signal lines 32. The lower layer signal line 3] and the upper layer signal line 32 are arranged so as to be orthogonal to each other, and a contact hole 34 is provided to connect the upper and lower signal lines.

(Problem to be Solved by the Invention) However, in the configuration of the image sensor as described above, the multilayer wiring portion is in a matrix shape, and the 13th
As shown in the cross-sectional explanatory diagram of the multilayer wiring in the figure, since the signal lines in the upper and lower layers intersect with each other via the insulating layer 33, the coupling capacitance (coupling As a result, at the intersection of signal lines, the output from one signal line is affected by the potential difference with the output from the other signal line, causing crosstalk, which makes it difficult to accurately calculate the charge. This poses a problem in that it cannot be detected and the reproducibility of gradations on the image sensor deteriorates.

Therefore, a light-receiving element array including a plurality of light-receiving elements arranged in a line in the main scanning direction as one block, a plurality of switching elements that transfer charges generated in the light-receiving elements block by block, and In an image sensor having a driving IC that outputs an image signal as an image signal, a switching element in a block in the light-receiving element array and a switching element in an adjacent block are connected by wiring in the order of shortest distance, and The wiring from the switching element to the switching elements in the blocks on both sides are connected so as to be located on opposite sides with respect to the main scanning direction of the light-receiving element array, and the light-receiving elements are arranged in the order of shortest length of the connected wiring. An image sensor is being considered that is characterized by arranging elements in order of proximity to the element array.

This image sensor has a wiring structure provided on both sides of the photodetector array, instead of the conventional wiring structure provided only on one side of the photodetector array in the main scanning direction of the photodetector array, and inside the photodetector array. A plurality of light-receiving elements are divided into one block, and the wiring connecting the switching elements connected to the light-receiving elements in each block in the light-receiving element array and the switching elements in an adjacent block is adjacent to the switching element in the block. Wiring connections are made in descending order of distance to the switching elements in the block to be connected, and the wiring connecting the switching elements in the block to the switching elements in the adjacent block is connected in the main scanning direction of the photodetector array in units of blocks. The wires are arranged alternately1, and the shorter wires are placed on the photodetector array side in order, so the signal wires do not cross each other, so the wires do not affect each other. It is possible to accurately read out the charge accumulated in the wiring capacitance of the wiring.

However, with the image sensor configuration described above, n signal lines run long in parallel as if threading through the photodetector array, so coupling capacitance (coupling capacitance) increases between the parallel signal lines. ), and as a result, the output from one signal line is affected by the potential difference with the output from the other signal line, resulting in crosstalk, which prevents accurate charge detection and reduces the gradation in the image sensor. There was a problem that the reproducibility of the data was deteriorated.

In addition, in the image sensor described above, when forming a load capacitance in the wiring part of the sensor, it is necessary to equalize the load capacitance in each signal line in order to read the accurate charge from each signal line. There was a problem in that the area of the load capacity had to be reduced in order to achieve miniaturization.

The present invention was made in view of the above-mentioned circumstances, and it reduces the electrical influence between signal lines in an image sensor.
An object of the present invention is to provide an image sensor that can accurately output charges from a signal line.

(Means for Solving the Problems) The invention according to claim 1 for solving the problems of the above-mentioned conventional example comprises arranging a plurality of blocks in a line in the main scanning direction, each block including a plurality of light receiving elements. An image sensor having a light receiving element array, a plurality of switching elements respectively connected to the plurality of light receiving elements that transfer charges generated in the light receiving elements block by block, and a driving IC that outputs the charges as an image signal. , a switching element in a block in the light receiving element array and a switching element in an adjacent block are connected by wiring in order of distance from each other to form a signal line, and a signal line is connected from a switching element in a block in the light receiving element array to a switching element in the blocks on both sides. Wiring of signal lines to the switching elements is connected so as to be located on opposite sides of the main scanning direction of the light receiving element array, and the signal lines are connected to the light receiving element in order of shortest length of the connected signal lines. The device is characterized in that it is arranged in the order of proximity to the element array, and that a wiring with a constant potential is provided between the signal line and the adjacent signal line.

The invention according to claim 2 for solving the above-mentioned problems of the conventional example provides a light-receiving element array in which a plurality of light-receiving elements are arranged in a line in the main scanning direction as one block; In an image sensor having a plurality of switching elements respectively connected to the plurality of light receiving elements that transfer generated charges block by block, and a driving IC that outputs the charges as an image signal, The switching element and the switching elements in adjacent blocks are connected by wiring in the order of distance from each other to form a signal line, and the signal line is wired from the switching element in the block in the light receiving element array to the switching elements in the blocks on both sides. are connected so as to be located on opposite sides of the light receiving element array with respect to the main scanning direction, and the connected signal lines are arranged in order of shortest length to the light receiving element array, The present invention is characterized in that a wiring with a constant potential is provided between the signal line and an adjacent signal line, and a wiring with a constant potential is provided further outside the signal line disposed outermost from the light receiving element array.

(Function) According to the invention as claimed in claim 1, the wiring structure is provided on both sides of the light receiving element array instead of the conventional wiring structure provided only on one side of the light receiving element array with respect to the main scanning direction of the light receiving element array. Then, a plurality of light-receiving elements in the light-receiving element array are divided into one block, and a signal line is provided to connect the switching elements each connected to the light-receiving elements in the block in the light-receiving element array and the switching elements in the adjacent block. The wiring connects the switching element in the block to the switching element in the adjacent block in order of shortest distance, and further connects the wiring of the signal line connecting the switching element in the block to the switching element in the adjacent block. The wires are placed alternately in the main scanning direction of the photodetector array in block units, and the connected signal lines are placed with the shorter wires facing the photodetector array in order, and a constant potential is applied between the signal lines. Since the wiring is provided, the signal lines do not cross each other, and the constant potential wiring between the signal lines arranged in parallel prevents crosstalk between the signal lines and The charge accumulated in the capacitor can be read out accurately.

According to the invention as set forth in claim 2, the wiring structure is provided on both sides of the light receiving element array instead of the conventional wiring structure provided only on one side of the light receiving element array with respect to the main scanning direction of the light receiving element array, Then, the plurality of light receiving elements in the light receiving element array are divided into one block, and the wiring of signal lines connecting the switching elements connected to the light receiving elements in each block in the light receiving element array and the switching elements in the adjacent block is The switching elements in the block are connected to the switching elements in the adjacent block in order of shortest distance, and the wiring of signal lines connecting the switching elements in the block and the switching elements in the adjacent block is connected in units of blocks. The wires are arranged alternately in the main scanning direction of the light-receiving element array, and the shorter wires of the connected signal lines are arranged in order toward the light-receiving element array, and a wire with a constant potential is provided between the signal lines. , since the wiring with a constant potential is provided further outside of the signal line placed farthest from the photodetector array, the signal lines do not cross each other, and the signal lines placed in parallel do not cross each other. The wiring with a constant potential prevents crosstalk between the signal lines, and the wiring with a constant potential further outside the signal line located farthest from the photodetector array prevents crosstalk between the signal lines. The load capacitance between the line and the inner signal line becomes uniform, and the charge accumulated in the capacitance of the signal line can be read out accurately.

(Example) An example of the present invention will be described with reference to the drawings.

FIG. 1 is an equivalent circuit diagram of an image sensor according to an embodiment of the present invention, and FIG. 2 is a diagram showing a light receiving element, a charge transfer section, and a part of the wiring structure of an image sensor according to an embodiment of the present invention. FIG.

The image sensor has one block of n sandwich-type light receiving elements (photodiodes P) 11' arranged in parallel on an insulating substrate such as glass, and a light receiving element array 1 having N blocks. ], (Pl, 1~PN, n
), and thin film transistors Tl, l-TN connected to each light receiving element 11', respectively.

n charge transfer units 12, a wiring group 13 connecting the charge transfer units 12 in adjacent blocks, and n wires corresponding to each light receiving element group in the block from the charge transfer unit 12 via the wiring group 13. A common signal line 14, a drive ICl3 connected to the common signal line 14, and an analog switch for time-sequentially extracting the potential of the n common signal lines 14 in the drive ICl3 to an output line 17 (COM). It is composed of SWI to SWn.

As shown in FIG. 2 and FIG. 3, which is a cross-sectional explanatory view taken along line A-A' in FIG. 26
, hydrogenated amorphous silicon (aSi:H) layer, n raw hydrogenated amorphous silicon (n” a-5i: H
) layer is formed, on which a band-shaped metal electrode 22 made of chromium (Cr 2) or the like is formed as a common electrode at the bottom of the light receiving element 11', and a hydrogen layer is formed separately for each light receiving element 11' (for each bit). A photoconductive layer 23 made of oxidized amorphous silicon (a-3i:H) and an upper transparent electrode 24 made of indium tin oxide (ITO) formed in a similar manner are sequentially laminated to form a sandwich type. .

Note that here, the lower metal electrode 22 is formed into a strip shape in the main scanning direction, the photoconductive layer 23 is formed on the metal electrode 22 by being discretely divided, and the upper transparent electrode 24 is also formed in a discrete manner. By dividing and forming individual electrodes,
A portion of the photoconductive layer 23 sandwiched between the metal electrode 22 and the transparent electrode 24 constitutes each light receiving element 11', and a collection thereof forms the light receiving element array 11. A constant voltage VB is applied to the metal electrode 22.

Further, one end of the transparent electrode 24 formed in a discrete manner is connected to one side of a wiring 30a made of aluminum or the like, and the other side of the wiring 30a is connected to a thin film transistor T of the charge transfer section 12.
It is connected to the lead-out portion 41' of the N, n drain electrode 41. Further, in the light receiving element 11', it is also possible to use Cd5e (cadmium selenium) or the like as the photoconductive layer instead of hydrogenated amorphous silicon. In this way, the photoconductive layer 23 and the transparent electrode 24 are separated by a
-3i: If the H photoconductive layer 23 is a common layer, the photoelectric conversion effect occurring in a particular light receiving element 11'' may cause interference with the adjacent light receiving element 11'', so this interference is reduced. It's for a reason.

Further, the thin film transistor T constituting the charge transfer section 12
As shown in FIG. 2 and FIG. 4, which is a cross-sectional explanatory view of the section BB' in FIG. A silicon nitride (S i Nx ) film as the insulating layer 26 , a hydrogenated amorphous silicon (a-5i:H) layer as the semiconductor active layer 27 , and a top insulating layer 29 provided facing the gate electrode 25 . Silicon nitride (S
i Nx ) film, n-biohydrogenated amorphous silicon (n” a-3i as ohmic contact layer 28)
: H) layer, a chromium layer (Cr2) as a drain electrode 41 and a source electrode 42 is sequentially laminated, and an aluminum layer 30 is connected thereon via an insulating layer such as polyimide, which is a transistor with an inverted staggered structure. .

Here, the ohmic contact layer 28 is formed separately into a portion 28a layer that contacts the drain electrode 41 and a portion 2gb layer that contacts the source electrode 42, and the chromium layer (Cr 2) thereon also contacts the drain electrode 41. Source electrode 42
It is formed separately. And the drain electrode 4
The light-receiving element 11'' is attached to the drawn-out part 41' drawn out from 1.
The aluminum wiring 30a from the transparent electrode 24 is connected, and the aluminum wiring 30b from the source electrode 42 to the wiring group 13 is connected.

In this embodiment, instead of extending the wiring 30a above the drain electrode 41 and contacting the drain electrode 41, the chromium part of the drain electrode 41 is connected to the light receiving element 1.
A drawn-out portion 41' is formed by drawing it out to the 1' side, and the wiring 30a is brought into contact with the drawn-out portion 41'. With such a configuration, the width of the thin film transistor itself can be reduced, and the space can be effectively utilized when a thin film transistor and an adjacent thin film transistor are close to each other as in this embodiment.

Further, the configuration of the wiring group 13 will be explained in detail with reference to FIGS. 1 to 5. However, in FIG. 5, in order to simplify the explanation, the light receiving element 11' and the charge transfer section 12 are collectively represented by boxes 1 to n for each block.

The configuration of the wiring group 13 is, for example, as shown in FIG.
A common signal line]4 (signal lines 1' to n') is led out from the driving ICl5a located at the bottom of the block, and the thin film transistors T1, 1 to T of the first block are connected to the signal lines 1' to n' along the way. 1. n sos electrodes 42 are connected to each other, and as shown in the plan view of the light receiving element, the thin film transistor, and a part of the wiring group in FIG. The signal lines 1' to n' are passed through the insulating layer of aluminum (AI) metal wiring formed thereon, and the signal lines 1' to n' are passed above the light receiving element array 11 in the direction of the second block. ' is extended, and the signal lines 1' to n are passed again between the light receiving elements 11' via an insulating layer such as polyimide, and an Al metal wiring formed thereon, and the thin film transistors T2. The n-72 and L source electrodes 42 are connected to each other.

Specifically, the signal line 1' is connected to the source electrode 42 of the thin film transistor T1,1 of the first block, and the second block is connected to the source electrode 42 of the thin film transistor T1,1 of the first block.
Block thin film transistor T2. n source electrode 42
are connected to the signal line 2', and the source electrodes 42 of the thin film transistors T1, 2 of the first block are connected to the signal line 2', and the thin film transistors T2. n-1 source electrode 42
The source electrodes 42 of the thin film transistors T in adjacent blocks are connected to each other via a signal line in order of distance so that the source electrodes 42 of the thin film transistors T of the first block are connected to the signal line n'. connection,
The source electrode 42 of the thin film transistor T2,1 of the second block will be connected. In other words, the source electrodes 42 of thin film transistors T that are close to each other in adjacent blocks are successively connected to each other by signal lines.

In this case, as shown in FIG. 5, the connected signal lines are arranged along the light receiving element array 11 in descending order of distance (
(in the main scanning direction), it is arranged close to the light receiving element array 11 and above the light receiving element array 11. In other words, the first
Specifically, between the blocks and the second block, the shortest signal line n' is arranged closest to the light receiving element array 11, and then the signal line n'-1 is arranged closest to the light receiving element array 11.
The longest signal line 1
' is placed at the outermost position of the signal line. With the above configuration, the first and second blocks
There are no signal lines that cross between blocks, so there is no need to worry about crosstalk.

Next, the wiring group 13 between the second block and the third block
The specific configuration will be explained. Thin film transistors T2,1 to T2 of the second block. n respective source electrodes 42
and the third block thin film transistor T3. n-T3,
Each of the source electrodes 42 of 1 is the light receiving element array 11.
The signal lines n' to 1' are connected to each other by signal lines n' to 1' arranged on the lower side.

Specifically, the signal line n' is connected to the source electrode 42 of the thin film transistor T2,1 of the second block, and the thin film transistor T3.1 of the third block is connected to the signal line n'. The source electrodes 42 of the thin film transistors T2, 2 of the second block are connected to the signal line n'-1, and the source electrodes 42 of the thin film transistors T3. The source electrode 42 of n( is connected.

In this way, the source electrodes 42 of the thin film transistors T in adjacent blocks are connected to each other by a signal line in order of distance, and then the thin film transistors T2, . n source electrode 42 and the third block thin film transistor T3,1
It is connected to the source electrode 42 of the signal line 1' by the signal line 1'. In other words, the source electrodes 42 of thin film transistors T that are close to each other in adjacent blocks are successively connected to each other by signal lines.

Regarding the wiring group 13 between the second block and the third block, as shown in FIG. 11 and below the light receiving element array 11. In other words, in the wiring between the second block and the third block, the shortest signal line 1' is placed closest to the light receiving element array 11, and then the signal line 2' is placed the second closest to the light receiving element array 11. In this way, the longest signal line n' is placed at the outermost position among the signal lines. Since the configuration is as above,
There are no signal lines that cross between the second and third blocks.

No worries about stalks.

The overall situation is shown in a schematic diagram in FIG. 5. When connecting from an odd block to an even block using a wiring group 13, the wiring group 13 is placed above the light receiving element array 11, and from an even block to an odd block, the wiring group 13 is connected. In the case where the light receiving element array 11 is connected, the light receiving element array 11 is arranged under the light receiving element array 11. Therefore, the wiring group 13 from odd-numbered blocks to even-numbered blocks and the wiring group 13 from even-numbered blocks to odd-numbered blocks do not intersect.
There is no need to worry about crosstalk.

In this embodiment, assuming that the N-th block is an even-numbered block, the driving IC 15b is provided below the N-th even-numbered block in the same way as the driving IC 15a is provided below the first block. . Here, the driving IC 15
Signal line 1 is connected to analog switches SW1 to SWn in a.
They are connected in the order of ' to n'. Then, the source electrodes 4 of the thin film transistors TN, l to TN, n of the Nth block
The signal lines to which 2 are connected are connected to the driving IC 15b, or are connected to the analog switch SW in the driving IC 15b.
1 to SWn are connected to signal lines continuing from the driving IC 15a in the order of signal lines n' to 1', respectively.

Analog switch 5WI in drive IC 15a, 15b
The n common signal lines 14 connected to -5Wn are drawn out from the wiring group 13, and the potential of the common signal line 14 changes due to the charge accumulated in the wiring of the signal lines of this wiring group 13. The value is extracted to the output line 17 (COMl, 2) by operation of an analog switch.

Here, in the driving ICs 15a and 15b, the potential values of the signal lines of the analog switches 5WI to 3Wn are read out in this order.

Next, the constant potential wiring provided between the signal lines will be explained using FIGS. 2 and 5.

The constant potential wiring provided between the signal lines may be, for example, a ground line connected to earth (grounding). As shown in FIG. 5, among the plurality of signal lines formed so as to weave through the light-receiving element array 11, a ground line 43 is connected between the signal lines arranged in parallel and the adjacent signal lines. Made of aluminum with the same metal layer. here,
It is convenient for design to make the wiring pitches of the signal line and the ground line 43 equal.

In this embodiment, each ground line 43 is connected (grounded) to the ground provided on the upper and lower sides of the light receiving element array 11.
The structure is such that it is connected to a wiring 44 made of chromium (Cr1). In addition, drive ICs 15a and 15b
Regarding the part where the common signal line 14 is connected to, a ground line 43 is arranged between the common signal lines 14, and a wiring 44 is connected to the ground just before the driving ICs 15a and 15b.
is provided, and the ground line 43 is connected to this wiring 44.

The specific structure of the light receiving element 11' of the ground line 43, the thin film transistor of the charge transfer section 12, and the vicinity of the light receiving element array 11 will be explained with reference to FIG. The ground line 43 on the upper side of the light receiving element array 11 is the common signal line 1
4, and just as the common signal line 14 connects the blocks, the ground line 43 also connects the blocks along the common signal line 14. The end of the ground line 43 is connected by a contact hole to a wiring 44 made of chromium (Cr 1) that is connected to a ground (ground) provided near the top of the light receiving element array 11 in the main scanning direction. It has become.

Further, the ground line 43 on the lower side of the light receiving element array 11 is
The aluminum layer 30, which is a light-shielding metal layer that is disposed between the common signal lines 14 and is formed to shield the a-8i:H layer of the thin film transistor, is brought out below the light-receiving element array 11 and connected to the ground. A ground line 43 is formed so that the common signal line 14 connects between blocks.
The blocks are also connected along the common signal line 14.

That is, the ground line 43 extends from the aluminum layer 30 of the light-shielding metal layer and is connected to the aluminum layer 30 of the light-shielding metal layer of the adjacent block. The ground wire 43 is a chromium (C) wire that is connected (grounded) to a ground provided near the bottom of the light receiving element array 11 in the main scanning direction.
It is connected to a wiring 44 formed by a contact hole (rl) through a contact hole.

Furthermore, as shown in the schematic diagram of the wiring group in FIG. A ground line 43 is formed. Compared to the inner signal line of the wiring group 13, the signal line disposed at the outermost side of the light receiving element array 11 forms a load capacitance with the ground line 43 provided on both sides of the inner signal line. Since the outermost signal line forms a load capacitance only by the ground line 43 on one side, the load capacitance cannot be made uniform. Therefore, in order to achieve the same condition as the inner signal line, three ground lines 43 are placed further outside the outermost signal line.
By providing this, it is possible to equalize the load capacitance and output accurate charge.

In this embodiment, three ground lines 43 are provided on the outermost side, but the number of ground lines 43 on the outermost side after calculating the load capacitance value differs depending on the sensor. Note that the value of the load capacitance can be designed based on the total wiring length, wiring width, wiring pitch, wiring material, and material of the insulating layer.

In addition, in FIG. 5, the shape of the wiring group 13 is shown as vertical wiring, horizontal wiring,
Wiring group 13 is formed using diagonal wiring.
This is to shorten the total wiring length.

Next, a method for manufacturing an image sensor according to an embodiment of the present invention will be explained.

First, a first chromium (Cr 1) layer that will become the gate electrode 25 is connected to the ground of the wiring group 13 on a substrate 21 such as glass that has been inspected and cleaned, and is connected to both sides of the light receiving element array 11 and the driving ICl 3. A first chromium (Cr 1) layer, which will become the wiring 44 to be formed immediately before, is deposited to a thickness of about 7,508 mm by DC sputtering. Next, this Crl is patterned by a photolithography process and an etching process. And B
After performing HF treatment and alkaline cleaning, a thin film transistor (TPT) is formed on the Crl pattern of the gate electrode 25.
A silicon nitride film (
SiNx) to a thickness of about 3000A, hydrogenated amorphous silicon (a-3i:H) to a thickness of about 500A, and silicon nitride film (SiNX) to a thickness of about 1500A to a thickness of about 1500A by plasma CVD (without breaking the vacuum). P-CVD)
A film is formed by

Here, the lower gate insulating layer 26 in the TFT is
ot t om-5i Nx (b-5i Nx), and the upper top insulating layer 29 is top-3iNx (t
−8iNx). Continuous film deposition without breaking the vacuum can prevent contamination at each interface, resulting in a low S/N ratio.
It is possible to improve the ratio.

The conditions for forming the b-3iNx film by P-CVD are that the substrate temperature is 300 to 400°C, and the gas pressure of SiH and NH3 is 0. SiH at 1-0.5 Torr.

The gas flow rate is 10~50SCCffl, the NH gas flow rate is 100~300sec, and the RF power is 50~2
It is 00W.

a-5i: The conditions for forming the H film by P-CVD are that the substrate temperature is 200 to 300°C and the SiH gas pressure is 0.
1~0. 5 Torr, SiH, gas flow rate 100 ~
RF power is 50-200W at 300SCCm.

The conditions for forming the t-5iNx film by P-CVD are that the substrate temperature is 200 to 300°C, and the gas pressures of SiH and NH3 are 0, 1 to 0, and 5 Torr.

The gas flow rate is 10~50SCCm, the NH gas flow rate is 100~300sCCffl, and the RF power is 50~2
It is 00W.

Next, in order to form the top insulating layer 29 in a shape corresponding to the gate electrode 25, a resist is applied on the top insulating layer 29, and the shape pattern of the gate electrode 25 is masked from the back side of the substrate 21. The top insulating layer 2 is formed by performing backside exposure, developing, and peeling off the resist.
Form 9 patterns.

Further, BHF treatment is performed, and an n-medium type a-3i:H film is deposited thereon to a thickness of about 100 OA as an ohmic contact layer 28 by P-CVD. Next, the drain electrode 41 and source electrode 42 of the TFT and the light receiving element 11'
The second chromium (Cr2) becomes the metal electrode 22 at the bottom of the
A layer is deposited to a thickness of about 150 OA by DC magnetron sputtering, and becomes the photoconductive layer 23 of the light receiving element 11'.
-3i:H is deposited to a thickness of about 13000A by P-CVD to form an ITO film that will become the transparent electrode 24 of the light receiving element 11'.
A film with a thickness of about 600A is deposited by DC magnetron sputtering. At this time, alkaline cleaning is performed before each film deposition.

Thereafter, in order to form individual electrodes of the transparent electrode 24 of the light-receiving element 11'', ITO is patterned by a photolithography process and an etching process.Next, a-8i:H of the photoconductive layer 23 is dried using the same resist pattern. Patterning is performed by etching.Here, the metal electrode 22 is patterned using chromium (
The Cr2) layer acts as a stopper during dry etching of a-3i:H and will remain unpatterned. During this dry etching,
Since the a-Si:H layer of the photoconductive layer 23 is heavily side-etched, ITO is etched again before the resist is removed. Then, the ITO is further processed and stamped from the peripheral back side to form ITO having the same size as the a-5i:H layer of the photoconductive layer 23.

The conditions for forming the above a-5i:H film by P-CVD are as follows:
The substrate temperature is 170-250°C, and the SiH4 gas pressure is 0. 3-0. 7 Torr, SiH.

Gas flow rate is 150-300sec, RF power is 1
00-200W.

Furthermore, the conditions for forming the above ITO by DC sputtering are as follows:
When the substrate temperature is room temperature, the gas pressure of A' and 02 is 1.5X.
At 10-3 Torr, Ar gas flow rate is 100-150
SCCIII, 02 gas flow rate is 1-2 sccm, D
C power is 200 to 400W.

Next, the chromium layer of the metal electrode 22 of the light receiving element 11' and the TP
Cr2, which will become the chromium layer of the drain electrode 41 and source electrode 42 of T, is patterned by a photolithography process and an etching process, and using the same resist pattern, an n medium-sized a- 3i
: Etching the H layer and the n medium type a-5i:H layer of the ohmic contact layer 28 of the TFT.

Next, in order to form a pattern for the TPT gate insulating layer 26, the b-8iNx is patterned by a photolithography process. Then, an insulating layer of polyimide is applied to a thickness of about 1150 OA so as to cover the image sensor, prebaking is performed, a photolithography process is performed to form each contact portion, and baking is performed again. As a result, in the light receiving element 11'', the contact portion that supplies power to the metal electrode 22 and the transparent electrode 2
In the TPT, the contact part connects the wiring 30a that transfers the charge generated in the light receiving element 11' and the contact part leads the charge to the signal line, and in the wiring group 13, the ground line 43 is connected to the ground. A contact portion connecting to the wiring 44 is formed. After this, in order to completely remove the polyimide remaining on the contact parts, etc., the
Do cum.

Next, aluminum (A1) was sputtered at 15,000 A by DC magnetron sputtering to cover the entire image sensor.
The film is deposited to a certain thickness and subjected to tK turning in a photolithography process to obtain the desired pattern. As a result, in the light receiving element 11', a wiring part that supplies power to the metal electrode 22, a wiring 30a part that extracts charges from the transparent electrode 24 and connects to the lead-out part 41' of the drain electrode 41 of the TPT, and a wiring group. In 13, TPT
A common signal line 1 configured to be connected to the source electrode 42 of
4 patterns and /Z turns of the ground line 43 are formed.

Finally, polyimide to form a passivation layer (not shown) is applied, prebaked, patterned in a photolithography process, and further baked to form a passivation layer. After this, Descum is performed to remove unnecessary remaining polyimide.

Thereafter, driving ICs 15a, 15b, etc. are mounted, wire bonding and assembly are performed, and the image sensor is completed.

The common signal line 14 is connected to the source electrode 42 of the TPT, and is formed entirely of aluminum (AI) in a meandering pattern around the light receiving element array 11 or the light receiving element array row. This makes it possible to lower the overall resistance value.

In addition, as another configuration of the wiring group, the vertical signal line portion of the wiring group 13 may be used especially for the light receiving element 11' adjacent to the light receiving element 11'.
′ is formed at the same time as forming the chromium (Cr 1) pattern constituting the gate electrode 25.
It is also conceivable to provide a contact hole in and make it of aluminum. In this case, the wiring 44 connected to the ground provided on both sides of the light receiving element array 11 is
Instead of forming the gate electrode 25 using chromium (Cr 1), the gate electrode 25 is formed of aluminum on the insulating layer 26 similarly to the wiring group 13.

With the above configuration, even if the distance between the light receiving element 11'' and the adjacent light receiving element 11' cannot be sufficiently wide, if the wiring is configured using Crl, the light receiving element 1
A signal line can be formed between the light receiving element 1' and the adjacent light receiving element 11', and since a certain bias voltage is applied to the metal electrode 22 of the light receiving element 11', the voltage of the adjacent light receiving element 11' is This metal electrode 22 has the effect of shielding the Crl signal line from the influence of change (crosstalk).

Next, a method for driving an image sensor according to an embodiment of the present invention will be described.

When a document (not shown) placed on the light-receiving element array 11 is irradiated with light from a light source (not shown), the reflected light illuminates the light-receiving element (photodiode P) and changes the density of the document. A corresponding charge is generated and accumulated in the parasitic capacitance of the light receiving element 11'. When the thin film transistor T is turned on based on the gate pulse φG transmitted from the gate pulse generation circuit (not shown) via the gate signal line Gi, the photodiode P is connected to the common signal line 14 side and the light receiving element The charge accumulated in the parasitic capacitance etc. of 11' is transferred to wiring group 1.
The signal is transferred and accumulated in the wiring capacitance of the common signal line 14 at No. 3.

Specifically, the photodiodes P11 to P of the first block
1. To explain the case where a charge is generated in the photodiode P1゜1-PLn, when the gate pulse φGl is applied from the gate pulse generation circuit, the thin film transistors TI,1 to T1,n are turned on, and a charge is generated in the photodiode P1゜1 to PLn. Charges are uniformly distributed throughout the common signal line 14 in the wiring group 13 and transferred and accumulated. In other words, the photodiode P
The charges of I and l are transferred to the overall wiring capacitance of signal line 1', the charges of photodiodes P1 and 2 are transferred to the overall wiring capacitance of signal line 2', and the charges of photodiode P L and n are transferred to signal line n
Transferred and accumulated to the general wiring capacitance.

Next, as shown in FIGS. 1 and 5, since two driving ICs 15a and 15b are provided in this embodiment, the mutual operational relationship between the two driving ICs 15a and 15b will be described.

The two driving ICs 15a and 15b are connected to each other as shown in FIG. 6, and the driving IC 15a is configured to read a start signal φS from the outside to start reading the potential generated in the wiring capacitance. , when the start signal φS is read by the signal reading terminal STI, the potential of the wiring capacitance regarding the first block is read into the driving IC 15a, and the switch S Wl =
By sequentially turning on SWn, the charges generated in the photodiodes Pi, 1-PL, and n of the first block and accumulated in the wiring capacitances of the signal lines 1' to n' are read out from COMI.

When the reading of the first block is completed, the signal is transferred from the signal generation terminal CRI in the driving IC 15a to the driving IC 15.
The signal is transmitted to the signal reading terminals ST2 and CS2 in b,
The drive IC 15b that received the signal is the drive IC
Switches SWI to SWn in 15b are sequentially turned on to turn on the photodiodes P2,1 to P2 of the second block. The charges generated in the signal lines 1' to n' and accumulated in the wiring capacitances of the signal lines 1' to n' are read out from the C0M2. Since the terminal ST2 and the terminal C82 are internally connected to an OR circuit, when a signal is input to either one, the driving IC 15b becomes operational, and the charge of one block (here, the second block) is It operates to read.

Furthermore, when the reading of the second block is completed, the signal is transmitted from the signal generation terminal CR2 in the drive IC 15b to the signal read terminal C8l in the drive IC 15a, and the drive IC 15a that receives the signal Charges related to the three blocks will be read from C0M1. Similarly to the terminal CS2, when a signal is transmitted to the terminal C3I, the terminal C3I operates to read the charge of one block (here, the third block).

In this way, charges from the first block to the Nth block of the light receiving element array 11 are transferred to the COM of the driving IC 15a.
I and C0M2 of the driving IC 15b are to be read alternately to COM, and when a signal is generated from CRI, the output from COMI will be in an OFF state until a signal is input to C8l, and similarly, from CR2 When a signal is generated, the output from C0M2 remains off until a signal is received at C32.

Clock pulses φCK are sent to the drive ICs 15a and 15b from the outside at regular intervals, and the COMI
By the alternating output operations from C0M2 and C0M2, the charge of the Nth block is read, and the operation of the driving IC is completed, and the reading of one line of the original is completed.

Then, COMI and C0M2 are connected, and the image signals alternately output from COMI and C0M2 to COM become the entire image signal from the first block to the Nth block.

In this way, the drive IC 15a reads the charges related to the odd blocks, and the drive IC 15b reads the charges related to the even blocks.As shown in the diagram explaining the output from the drive IC in FIG. This is because the readout order (direction) of charges in even-numbered blocks is reversed. In other words, the driving IC 15a connects the signal lines 1' to
The charge accumulated in n' is transferred to analog switches SWI~SW
Since the signals are read in the order of signal lines 1' to n' and output from COMI, if you want to read the charges of the 1st block to the Nth block, the 1st of photodiodes P in the odd blocks The charges from th to nth are signal line 1'
~ n', so it is read out in the order of signal lines 1' to n', or in even-numbered blocks, the 1st to nth charges of photodiodes P are accumulated in signal lines n' to 1'. Therefore, signals are read out in the order of signal lines n to 1', so the order of reading out signals is reversed in even-numbered blocks. Therefore, the driving IC 15a selectively reads out only the charges in the odd blocks.

On the contrary, in the driving IC 15b, charges in even blocks are normally read out. In other words, in an even block, the 1st to nth charges of the photodiode P are accumulated in the signal lines n' to 1', but the driving IC 15b reads the charges of the signal lines n to 1' in the order and outputs it at C0M2. Therefore, the charges generated in the first to nth photodiodes P of the even-numbered blocks are outputted to C0M2 as an image signal. Conversely, in odd-numbered blocks, the 1st to nth charges of photodiodes P are accumulated in signal lines 1' to n', but the driving I
Since the C15b reads charges in the order of signal lines n' to 1', the order of reading signals is reversed in odd-numbered blocks.

Therefore, the driving IC 15b selectively reads out only the charges in even blocks.

As described above, when the drive ICs 15g and 15b selectively output the odd and even blocks from C0M1 and C0M2, and then combine them alternately and output them from COM, as shown in COM in FIG. It is possible to sequentially output the image signals of the block to the Nth block.

According to this embodiment, a plurality of light-receiving elements 11' constitute one block, and the source electrode 42 of the thin-film transistor connected to each light-receiving element 11' in the block and the source electrode 42 of the thin-film transistor connected to each light-receiving element 11' in the adjacent block. Wiring of the common signal line 14 between the source electrodes 42 connects the source electrodes 42 of thin film transistors in a block to the source electrodes 42 of thin film transistors in an adjacent block in order of shortest distance, and then The wiring of the common signal line 14 between the electrode 42 and the source electrode 42 of the thin film transistor in the adjacent block is arranged alternately in the main scanning direction of the light receiving element array 11 in block units, and the connected common signal line 14 is The shorter communication lines 14 are arranged in order on the light receiving element array 11 side, a ground line 43 is provided between the common signal lines 14, and the signal line (signal line 1 ' or signal line n') and three ground lines 4 further outside.
3, the signal lines do not cross each other, and the ground line 43 provided between the common signal lines 14 arranged in parallel prevents crosstalk between the common signal lines 14. In addition, the three ground lines 43 provided further outside the signal line placed farthest from the light receiving element array 11 on the outside make the load capacitance between the outermost signal line and the inner signal line uniform. The charge accumulated in the wiring capacitance of the common signal line 14 in the wiring group 13 can be accurately read out, which has the effect of improving the reproducibility of the gradation of the image sensor.

Further, by arranging the ground line 43 between the common signal lines 14, a load capacitance can be formed in a small area, which has the effect of reducing the size of the image sensor.

In addition, in this embodiment, two driving ICs are provided,
One driving IC 15a reads out the charges generated in the odd-numbered blocks, and the other driving IC 15b reads out the charges generated in the even-numbered blocks, and the outputs from both driving ICs are combined to form an image signal. This has the effect of making output processing easier than when outputting image signals with one driving IC.

As another example, the load capacity in the wiring group 13 can be further increased by changing the configuration shown in FIG. 5 to the configuration shown in the schematic diagram of the wiring group in FIG. 8. This is because the configuration shown in FIG. 8 allows the length of the entire wiring to be longer, thereby increasing the load capacity of the wiring group 13.

Furthermore, the wiring length of the common signal line 14 of the wiring group 13 is such that the two driving ICs 15a and 1 are located below the light receiving element array 11.
5b, the signal line n' to signal line 1' are longer in the order (signal line 1' is the longest), and therefore the load capacitance of the common signal line 14 is also smaller than the signal line n'.
.about.signal line 1'. Therefore, as a means of correcting the difference in the load capacitance of each common signal line] 4, for example, the length of the common signal line 14 is changed from signal line 1' to By increasing the length of the signal lines n' and making the lengths of the common signal lines 14 the same as a whole, it is possible to make the load capacitance of each common signal line 14 uniform. Here, the load capacitance was corrected by changing the length of the signal line immediately before the common signal line 14 was connected to the drive IC 5b. It is also possible to correct the load capacitance by changing the width of the signal line immediately before connection.

In addition, as another means for correcting the difference in load capacitance of each common signal line 14, an insulating layer 33 is provided between the aluminum common signal lines 14, as shown in the cross-sectional diagram of the wiring portion in FIG. The ground line 43 is formed of chromium on the substrate 21 through the wire, and the overlap area with the ground line 43 is increased for a signal line with a short wiring length, and the overlap area with the ground line 43 is made large for a signal line with a long wiring length. By narrowing the overlap area, the load capacitance of the common signal line 14 can be made uniform. Specifically, the overlapping area with the ground line 43 is increased in the order of the signal lines 1' to n'. The configuration in which the ground line 43 is formed of chromium on the substrate 21 with the insulating layer 33 interposed between the signal lines may be used for the entire wiring group 13 or for a portion thereof.

Furthermore, as another means for correcting the difference in the load capacitance of each common signal line 14, an insulating layer 33b is provided between the aluminum common signal lines 14, as shown in the cross-sectional diagram of the wiring portion in FIG. 9(b). The ground line 43 is formed of aluminum in a layer above the signal line through the signal line, and the overlap area with the ground line 43 is widened for a signal line with a short wiring length, and the overlapping area with the ground line 43 is widened for a signal line with a long wiring length.
By narrowing the overlap area with the common signal line 14, the load capacitance of the common signal line 14 can be made uniform.

The wiring configuration shown in the cross-sectional explanatory diagrams of the wiring part in FIGS. 9(a) and 9(b) is for a case where the distance between the common signal lines 14 is narrow, and the ground line 43 is placed between the signal lines using the same layer of aluminum. In cases where this is not possible, the ground line 43 is formed on a separate layer rather than on the same layer as the signal line, which reduces crosstalk between the signal lines to some extent and is also useful for forming load capacitance. .

In addition, if the sensor is made smaller and the load capacity is desired to be increased, a pattern of a metal layer (for example, a ground layer) with a constant potential is formed on the upper or lower layer of the wiring group 13 so as to cover the wiring group 13. It is possible that In this case, the load capacitance can be increased regardless of whether the ground line 43 is provided between the common signal lines 14 or not.

In this embodiment, among the common signal lines 14 of the wiring group 13, there are three ground lines further outside the signal line (signal line 1' or signal line n') arranged outermost from the light receiving element array 11. 43 is provided to equalize the load capacitance of each common signal line 14. However, in order to read out more accurate charges, as shown in the schematic diagram of the wiring group in Figure 10, the outermost A thin film transistor switching element (TPT) is connected to the middle one of the three ground lines 43 provided outside the signal line placed in the dummy line 45, and the general signal line is connected to the ground line 43 by gate pulses. By varying the potential so that the feed-through phenomenon in which the instantaneous potential increases also occurs on the dummy line 45, charges can be output accurately in the same environment as the signal lines inside the wiring group 13.

The operation of the dummy line 45 connected to the TPT is linked to the gate pulse φGl of the first block to the gate pulse φGn of the Nth block, and turns on/off the TPT at the same timing as the charge transfer in each block. be. Here, a dummy photodiode is also connected to the TPT of the dummy line 45 as the potential changing means 46. However, this dummy photodiode does not receive light.

(Effects of the Invention) According to the invention described in claim 1, in a TPT-driven image sensor, a wiring structure is provided on both sides of the light-receiving element array in the main scanning direction, and a plurality of wiring structures in the light-receiving element array are provided. The light-receiving elements are divided into one block, and the signal lines connecting the switching elements connected to the light-receiving elements in each block in the light-receiving element array and the switching elements in the adjacent block are adjacent to the switching elements in the block. The wiring of signal lines connecting switching elements in a block to switching elements in an adjacent block is connected in the order of shortest distance to the switching elements in the block, and the wiring of the signal lines connecting switching elements in a block and switching elements in an adjacent block is connected to each other in the main scanning direction of the light receiving element array. The wires are placed alternately, and the shorter wires of the connected signal return wires are placed in order toward the photodetector array side, and wires with a constant potential are provided between the signal wires, so the signal wires are connected to each other. The lines do not cross, and the constant potential wiring between the signal lines placed in parallel prevents crosstalk between the signal lines, making it possible to accurately read out the charge accumulated in the capacitance of the signal lines. This has the effect of improving the gradation reproducibility of the image sensor.

According to the second aspect of the invention, in the TPT-driven image sensor, a wiring structure is provided on both sides of the light receiving element array with respect to the main scanning direction, and the plurality of light receiving elements in the light receiving element array are divided. One block is assumed, and the wiring of the signal line connecting each switching element connected to the light receiving element in the block in the light receiving element array and the switching element in the adjacent block is the wiring between the switching element in the block and the switching element in the adjacent block. The wiring of the signal lines connecting the switching elements in a block to the switching elements in the adjacent block is arranged in order of distance from the nearest one, and the wiring is arranged alternately in the main scanning direction of the light receiving element array in each block. The connected signal lines are placed in order with the shorter wires facing the photodetector array side, and wiring with a constant potential is provided between the signal lines, and further Since the wiring with a constant potential is provided on the outside,
The signal lines do not cross each other, and the constant potential wiring between the signal lines arranged in parallel prevents crosstalk between the signal lines. The constant potential wiring provided further outside the signal line equalizes the load capacitance between the outermost signal line and the inner signal line, making it difficult to accurately read out the charge accumulated in the signal line capacitance. This has the effect of improving the gradation reproducibility of the image sensor.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram of an image sensor according to an embodiment of the present invention, and FIG. 2 is an explanatory plan view of a part of a light receiving element, a charge transfer section, and a wiring group of an image sensor according to an embodiment of the present invention. , FIG. 3 is a cross-sectional explanatory diagram of the section A-A' in FIG. 2, FIG. 4 is a cross-sectional explanatory diagram of the section B-B' in FIG. 2, and FIG. 5 is an image according to an embodiment of the present invention. 6 is a schematic diagram of a sensor wiring group, FIG. 6 is a connection configuration diagram of a driving IC of an image sensor according to an embodiment of the present invention, FIG. 7 is an explanatory diagram of the output from the driving IC of FIG. 6, and FIG. The figure is a schematic diagram of a wiring group of an image sensor according to another embodiment of the present invention, FIGS. 9(a) and (b) are cross-sectional explanatory diagrams of a wiring group according to another embodiment, and FIG. A schematic diagram of a wiring group of an image sensor according to another embodiment, FIG. 11 is an equivalent circuit diagram of a conventional image sensor, FIG. 12 is an explanatory plan view of the multilayer wiring structure in FIG. 11, and FIG.
The figure is an explanatory cross-sectional view taken along line c-c' in FIG. 12. 11. 12. 13. 14. 15. 51... Light receiving element array 52... Charge transfer section... Wiring group 54... Common signal line 55...・Drive IC 17, 57... Output line 21... Substrate 22... Metal electrode 23... Photoconductive Layer 24...Transparent electrode 25...Gate electrode 26...Insulating layer 27...Semiconductor active layer 28...Ohmic contact layer 29.
......Top insulating layer 30......Aluminum layer 3]...
...Lower layer signal line 32...Upper layer signal line 33...Insulating layer 34...Contact hole 35...
...Signal line 36...Contact part 41...Drain as pole 42...Source electrode 43... ...Ground wire 4......Ground connection wiring 5...
...Dummy wire 6...Potential changing means 3...Multilayer wiring application person: Fuji Serotox Co., Ltd. - Agent
Patent Attorney Kiyotaka Sakamoto Agent Patent Attorney Ship
Nobuhiro TsuFigure 2Figure 3Figure 4Figure 9

Claims (2)

[Claims] (1) A light-receiving element array consisting of a plurality of light-receiving elements arranged in a line in the main scanning direction, each block having a plurality of light-receiving elements; In an image sensor having a plurality of switching elements to be connected and a driving IC that outputs the charge as an image signal, the switching elements in a block and the switching elements in an adjacent block in the light receiving element array are arranged close to each other. The wiring of the signal lines from a switching element in a block to switching elements in blocks on both sides of the light-receiving element array is on opposite sides with respect to the main scanning direction of the light-receiving element array. the connected signal lines are arranged in order of shortest length and closest to the light receiving element array, and wiring with a constant potential is connected between the signal lines and adjacent signal lines. An image sensor characterized by: (2) A light-receiving element array consisting of a plurality of light-receiving elements arranged in a line in the main scanning direction, each block having a plurality of light-receiving elements; In an image sensor having a plurality of switching elements to be connected and a driving IC that outputs the charge as an image signal, the switching elements in a block and the switching elements in an adjacent block in the light receiving element array are arranged close to each other. The wiring of the signal lines from a switching element in a block to switching elements in blocks on both sides of the light-receiving element array is on opposite sides with respect to the main scanning direction of the light-receiving element array. the connected signal lines are arranged in order of shortest length and closest to the light receiving element array, and wiring with a constant potential is connected between the signal lines and adjacent signal lines. An image sensor characterized in that a wiring having a constant potential is provided further outside the signal line disposed outermost from the light receiving element array.