JPH04249429A - Digital data transmission apparatus - Google Patents

Abstract

PURPOSE:To shorten convergent time for reducing a processing amount for equalizing a received signal and for obtaining the optimum timing in a digital data transmission apparatus that carries out bilateral transmission of digital data. CONSTITUTION:The digital data transmission apparatus is provided with an equalizing section 4 consisting of an amplitude variable equalizer 6 and a delay time variable equalizer 7, or an equalizing section 4 unifying these equalizers, and based on the correlation between a discriminate output signal from a discriminate feedback type equalizer 5 and an error signal, digital data is successively calculated under the tap coefficient update control realting to precursor, main cursor, and postcursor, a variable coefficient of transfer function is obtained, a received signal is equalized, and the optimum timing is obtained for equalization.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data transmission device for transmitting and receiving digital data. Digital data transmission equipment that bidirectionally transmits high-speed, multivalued digital data using digital subscriber lines is equipped with echo cancellers, equalizers, timing regeneration circuits, etc., which reduces the amount of processing. Moreover, it is desired to shorten the convergence time.

[0002] A system for bidirectionally transmitting digital data via a digital subscriber line, for example, as shown in FIG. 55 is connected, and on the exchange side, a line termination device (LT) 52 is connected to the exchange network switch (NW) 54, and a digital subscriber network is connected between the line termination device 52 and the network termination device 51 on the subscriber side. They are connected by a line 53, and bidirectional transmission of digital data is performed using a transmission code such as a 2B1Q code.

[0003] The network termination device 51 and the line termination device 52 have almost the same configuration, and conventionally, for example, the configuration shown in FIG. 6 or 7 is known. In Figure 6, 61
is a hybrid circuit (H), 62 is a reception low-pass filter (RLF), 63 is an AD converter (A/D), 64 is a waveform shaping filter (WSF), 65 is an adder, 66 is an equalizer (EQL), 67 is a decision feedback equalizer (DFE), 6
8 is a decoder (DEC), 69 is a timing recovery circuit (
70 is an echo canceller (EC), 71 is a coder (COD), 72 is a DA converter (D/A), 73 is a transmission low-pass filter (SLF), and 74 is a square sum calculation unit. Each part other than the reception low-pass filter, hybrid circuit, and transmission low-pass filter is realized by an integrated logic circuit, or by an arithmetic function such as a DSP (digital signal processor). Also, the transmitter includes a coder 71 and a DA converter 72.
The receiving section includes a receiving low-pass filter 62, an AD converter 63, a waveform shaping filter 64, an equalizer 66, a decision feedback equalizer 67, a decoder 68, etc. ing.

[0004] The hybrid circuit 61 is for connecting the transmitting section and the receiving section to a two-line line such as a digital subscriber line, and transmitting data is converted by a coder 71 into a transmitting code, for example, a 2B1Q code. The signal is converted into, for example, a four-value analog signal by the DA converter 72, harmonic components are removed by the transmission low-pass filter 73, and sent to the digital subscriber line via the hybrid circuit 61. At that time, a part of the transmitted signal goes around to the receiving side via the hybrid circuit 61 and becomes an echo component.

The received signal is also applied from the hybrid circuit 61 to the AD converter 63 via the reception low-pass filter 62, sampled by the timing signal from the timing regeneration circuit 69, and converted into a digital signal. In this case, an oversampling type AD converter is often used. Then, the waveform shaping filter 64 shapes the waveform into a waveform that temporarily becomes negative polarity at a time before the main cursor of the solitary wave response is generated, and the waveform is added to the adder 65. A pseudo echo signal from an echo canceller 70 is added to this adder 65, and the echo component, which is a part of the transmitted signal that has passed through the hybrid circuit 61, is canceled out. This adder 65 can also be referred to as an echo canceller.

The equalizer 66 is called a root f equalizer, and in a digital subscriber line transmission system, the transmission level is a constant value, and the loss near the DC component of the cable and the loss near the high frequency component are eliminated. Since there is a correlation regardless of the type of cable, the sum of squares calculation section 74 calculates the sum of squares of the amplitude of the received signal within a certain time, and the parameters of the equalizer 66 are calculated from that size. . This equalizer 6
Since the inter-symbol interference component cannot be sufficiently reduced even with the filter 6, a decision feedback equalizer 67 is provided.

This decision feedback type equalizer 67 has, for example, 3
The determination section includes a transversal filter section having a large number of taps such as 2 taps, a determination section that determines a four-value level, and an error calculation section that outputs the difference between the input and output signals of this determination section as an error signal. The determination output signal is decoded by the decoder 68 from a multilevel signal to binary received data. Further, the judgment output signal from the judgment section and the error signal e from the error calculation section are applied to the timing regeneration circuit 69 to regenerate a timing signal, and this timing signal is sent to the AD converter 63.
added to. Also, from the echo canceller 70, a pseudo echo signal is formed based on the error signal e and the transmission data, and is added to the adder 65 to cancel the echo component. In the case of a network terminal (NT) on the subscriber side, in order to perform clock regeneration in synchronization with the received signal, a phase-locked loop (PLL) (not shown), etc., which constitutes a clock generation circuit from the timing regeneration circuit 69, etc. Clock control data is added to.

In FIG. 7, the same reference numerals as in FIG. 6 indicate the same parts, 75 is a variable delay time equalizer (DEQ), 76 is
, 77 are coefficient conversion units (KD, KE), and the AD converter 63 is adapted to convert the received signal into a digital signal by adding a timing signal of a constant frequency. Further, the coefficient conversion units 76 and 77 convert the delay time variable equalizer 7 using the error signal e and the judgment output signal from the decision feedback equalizer 67.
5 and the equalizer 66,
Control is performed using the variable delay time equalizer 75 so that determination can be made at the optimum timing.

FIG. 8 is an explanatory diagram of a solitary wave response.
The waveform shaping filter 64 after the AD converter 63 corresponds to the second decimation filter in the oversampling AD converter, and by controlling the passband characteristics of this filter including the phase characteristics, , the waveform becomes negative once before the main cursor is generated. Then, if the amplitude at t=0 is the main cursor, the amplitude at a point (-T) before the baud rate period T is called the first precursor, and the point (-2T) before T is called the second precursor, T,2 after the main cursor
The amplitude at the points T, 3T, ... is calculated by the first post cursor, the second post cursor, the third post cursor, ...
It is called. If the timing when the value of this first precursor becomes zero is the optimal timing, then T
Later, the value of the main cursor at approximately the peak point of the amplitude will be obtained.

Therefore, the timing recovery circuit 69 in FIG. 6 understands that when the first precursor value has positive polarity, the timing is behind, and on the other hand, when it is negative, the timing is advanced. , the timing is adjusted so that the timing is optimal, that is, the first precursor value becomes zero. In addition, in FIG. 7, the value of the first precursor is calculated based on the determination output signal and the error signal e in the coefficient conversion section 76, and the value of the first precursor is calculated in the variable delay time equalizer 7.
The timing is adjusted by controlling the parameters No. 5 and changing the delay time.

[0011]

[Problems to be Solved by the Invention] The equalizer 66 has a transversal filter configuration of at least two taps, and in the conventional example shown in FIG. Because of the configuration used, in the case of a digital subscriber line at a distance where an equalizer is not provided, the equalization residual becomes large. In addition, in the conventional example shown in FIG. 7, the parameter corresponding to the distance of the digital subscriber line or the tap coefficient of one of the two taps is found continuously, but in order to convert from that parameter to the tap coefficient of the other tap. calculation is required.

[0012] Also, the master clock on the switching center side becomes the reference for the entire system, and the network terminal equipment (NT) on the subscriber side
A signal from a line termination device (LT) on the exchange side is received, and the frequency and phase of a clock generation circuit including a phase-locked loop (PLL) etc. are controlled to match the timing of this received signal. Since transmission is based on the clock from this clock generation circuit, the line termination device (LT)
), reception processing can be performed by adjusting only the phase using the master clock. In the configuration of FIG. 6,
By adjusting the sampling timing in the AD converter 63, the above-mentioned phase can be adjusted, and in the configuration of FIG. 7, the delay time can be adjusted by changing the parameters of the variable delay time equalizer 75. Although the above-mentioned phase is adjusted, since the frequency cannot be adjusted, this configuration can only be applied to line termination equipment (LT).

[0013] Regarding the optimization of the timing in the line termination device (LT), the configuration shown in FIG. Since the training is performed using a training method that must be performed during communication, it is necessary to draw in the echo canceller 70, equalizer 66, and decision feedback equalizer 67 at the same time, and if the timing is changed, all new This corresponds to finding a coefficient, and has the disadvantage that it takes a long time to pull in.

Furthermore, in the configuration shown in FIG. 7, since the delay time of the variable delay time equalizer 75 is changed, it is possible to perform this separately from the pull-in of the echo canceller 70.
Convergence time is significantly shorter. However, with only the variable delay time equalizer 75, the baud rate period T or its half period (T/2
), the order of the filter needs to be quite high, which has the disadvantage of complicating the configuration. Note that if the order of this filter is not made high, there is a problem that waveform distortion cannot be ignored.

[0015]Also, since the timing adjustment of the network termination device (NT) can be performed with the coefficients of the echo canceller 70 fixed, it is easier than that of the line termination device (LT), but the timing can be adjusted to the optimum timing. Until now, inter-symbol interference occurred due to the non-zero precursor value, resulting in large errors and a disadvantage that the convergence time was lengthened. An object of the present invention is to reduce the amount of processing for equalizing received signals and shorten the convergence time to obtain optimal timing.

[0016]

[Means for Solving the Problems] The digital data transmission device of the present invention will be described with reference to FIG. In this case, the receiving section is an AD
It has a configuration in which a converter 2, a waveform shaping filter 3, an equalizer 4, and a decision feedback equalizer 5 are connected in cascade, and the equalizer 4
is composed of a variable amplitude equalizer 6 and a variable delay time equalizer 7 that adaptively update variable coefficients based on the decision output signal and error signal from the decision feedback equalizer 5.

Further, the transfer function of the variable amplitude equalizer 6 is expressed as -
C0 (1-C+1・z-1), and the variable coefficient C0,
The configuration is such that C+1 is sequentially calculated and controlled by tap coefficient update control related to the main cursor and the first post cursor, respectively.

Further, the transfer function of the variable delay time equalizer 7 connected after the variable amplitude equalizer 6 is defined as C-2+C-1.
z-1+z-2+Cx z-3, coefficient Cx is an arbitrary fixed value, and variable coefficients C-2 and C-1,
The configuration is such that the tap coefficients are sequentially calculated and controlled by tap coefficient update control related to the second precursor and the first precursor, respectively.

Further, the transfer function of the equalization section 4 which integrates the variable amplitude equalizer 6 and the variable delay time equalizer 7 is expressed as C0 (C-
2+C-1・z-1+z-2+C+1・z-3+C+2
・Z-4) and variable coefficients C-2, C-1, C0, C
+1 and C+2 are sequentially calculated and controlled by tap coefficient update control related to the second pre-cursor, first pre-cursor, main cursor, first post-cursor, and second post-cursor, respectively.

A high-pass filter with a transfer function of (1-z-1) is connected after the waveform shaping filter 3, and the echo component contained in the output signal of this high-pass filter is removed by an echo canceller, and the equalization section 4 The transfer function of this equalizer 4 is defined as C0 (C-2+C-1
・z-1+z-2+C+1・z-3+C+2・z-4)
/(1-a・z-1), and the variable coefficients C-2, C-1,
The configuration is such that C0, C+1, and C+2 are sequentially calculated and controlled by tap coefficient update control related to the second pre-cursor, first pre-cursor, main cursor, first post-cursor, and second post-cursor, respectively.

A convergence determination section is provided for inputting the absolute value sum or square sum of the error signal from the decision feedback equalizer 5 and the value of the coefficient C-1 corresponding to the first precursor to determine convergence. , the sampling timing in the AD converter 2 is set to T/m (T = baud rate period, m = an integer of 4 or more) until the convergence determination unit determines that the convergence has converged.
The configuration is such that the address is shifted and the pull-in process is repeated.

[0022] Also, the difference (C-
1-ka) with a determination threshold value and controls the clock phase based on the comparison result.

[0023]

[Operation] The received signal is converted into a digital signal by the AD converter 2, the waveform is shaped by the waveform shaping filter 3 so that the amplitude becomes negative polarity before the main cursor, and the transmission distortion is equalized by the equalizer 4. , the intersymbol interference components are removed by the decision feedback equalizer 5. This decision feedback equalizer 5
has a known configuration including a transversal filter section, a determination section, and an error calculation section, and based on the correlation value between the determination output signal from the determination section and the error signal from the error calculation section, It adaptively updates the variable constants of the variable amplitude equalizer 6 and the variable delay time equalizer 7 that constitute the equalization unit 4,
For the variable amplitude equalizer 6, in addition to the main cursor value, parameters with a high correlation with the post-cursor value are used, and for the variable delay time equalizer 7, for example, the first precursor value and the second precursor value are used. Use parameters related to values.

Further, the transfer function of the variable amplitude equalizer 6 is −C0
(1-C+1・z-1), and the variable coefficients C0, C+
Regarding 1, tap coefficient update control related to the main cursor and the first post cursor is performed, for example, the taps related to the main cursor, the first and second pre-cursors, and the k-th post cursor at time j. Letting the coefficients be h0,j, h-1,j, h-2,j, h+k,j, the tap coefficient at time (j+1) is as follows, where α is the step size, h0,j+1 = h0,j +α・
aj-2 ・ej-2
...(a) h-1,j+1=h-1,j
+α・aj−1・ej−2
...(b) h-2, j+1=h-
2,j+α・aj・ej−2
...(c) h+k,j+1
=h+k,j+α・aj−k−2・ej−2
...It can be expressed as (d). Regarding the above-mentioned transfer function, the tap coefficient determined by equation (a) can be set as C0, and the tap coefficient determined by equation (d) with k=1 can be set as C+1.

Further, the transfer function of the variable delay time equalizer 7 is expressed as C-
2+C-1・z-1+z-2+Cx・z-3, the coefficient Cx is an arbitrary fixed value, and the variable coefficients C-2, C-
1, performs tap coefficient update control related to the second precursor and the first precursor, respectively,
Regarding the above-mentioned transfer function, the tap coefficient found by equation (a) is C0, the tap coefficient found by equation (d) with k=1 is C+1, and the tap coefficient found by equation (b) is given a negative sign to be C. -1, and by adding a negative sign to the tap coefficient determined by equation (c), it can be set as C-2. Then, the second terms on the right-hand sides of equations (a) to (d) are controlled to settle to zero on average, and the determination timing is optimized.

Further, the equalization section 4 is formed by integrating the variable amplitude equalizer 6 and the variable delay time equalizer 7, and its transfer function is expressed as C0 (
C-2+C-1・z-1+z-2+C+1・z-3+C
+2・z−4), and the variable coefficients C−2, C−1, C0
, C+1, and C+2, tap coefficient update control related to the second pre-cursor, first pre-cursor, main cursor, first post-cursor, and second post-cursor is performed, respectively.For this transfer function, equation (a) is used. The tap coefficient found by equation (b) is given a negative sign as C-1, the tap coefficient found by equation (c) is given a negative sign as C-2, and k
Let C+1 be the tap coefficient found by equation (d) with =1, and C+1 be the tap coefficient found by equation (d) with k=2.
It can be set to +2.

A high-pass filter having a transfer function of (1-z-1) is connected after the waveform shaping filter 3 to compensate for the attenuation of high frequency components and to reduce the tailing of the solitary wave response. At this time, in the case of short-distance cables, the attenuation of high frequency components is small and this high-pass filter causes overcompensation, so the transfer function of the equalizer 4 is changed to C0 (C-2+
C-1・z-1+z-2+C+1・z-3+C+2・z
-4)/(1-a.z-1) to cancel the characteristics of the high-pass filter. Variable coefficients C-2, C-1 in this case
, C0, C+1, and C+2 are sequentially calculated by tap coefficient update control related to the second pre-cursor, first pre-cursor, main cursor, first post-cursor, and second post-cursor, respectively. Also, each variable coefficient C-2
, C-1, C0 , C+1, C+2 are (a) to (d)
It can be determined using the formula. In addition, the coefficient a is a parameter related to the cable distance, and at the beginning of the pull-in, a
=0.

The convergence determination section determines whether or not convergence has occurred based on the correlation value between the determination output signal of the decision feedback equalizer 5 and the error signal, and when it has not converged, the AD converter 2 The sampling timing in AD converter 2 is shifted by T/m and the pull-in process is repeated, and when it is determined that convergence has been achieved, the sampling timing in AD converter 2 is fixed and training is completed. In this case, m is a value of 4 or more. Thereby, it is possible to speed up the pull-in by the variable delay time equalizer 7 and the like.

Further, the difference between the coefficient C-1 corresponding to the first precursor of the variable delay time equalizer 7 and the constant value ka is compared with the determination threshold THa by a comparator or the like to control the clock phase. This makes it possible to optimize the reception decision timing at the network terminal (NT) on the subscriber side.

[0030]

[Embodiment] FIG. 2 is a block diagram of the first embodiment of the present invention, and 11 is a hybrid circuit (H
), 12 is a reception low-pass filter (RLF), 13 is A
D converter (A/D), 14 is a waveform shaping filter (WSF)
), 15 is an adder, 16 is an amplitude variable equalizer (EQL),
17 is a decision feedback equalizer (DFE), 18 is a decoder (
DEC), 19 is a delay time variable equalizer (DEQ), 20
is an echo canceller (EC), and 21 is a coder (COD).
, 22 is a DA converter (D/A), 23 is a transmission low-pass filter (SLF), 24 is a comparator (CMP), 25 is a switch, 26 is a correlator, 27 is an error evaluation unit, and 28 is a convergence determination unit. be. The switch 25 is turned on in the case of a network termination device (NT), and is connected to the output signal of the correlator 26 and the threshold value THa.
The comparator 24 compares the data with the clock control data ct of +1, 0, and -1, and applies the clock control data ct of +1, 0, and -1 to a clock generation circuit (not shown). The transmitting section includes a coder 21, a DA converter 22, a transmitting low-pass filter 23, etc., and the receiving section includes a receiving low-pass filter 12, an AD converter 13, a waveform shaping filter 14, a variable amplitude equalizer 16, and a delay time. It includes a variable equalizer 19, a decision feedback equalizer 17, a decoder 18, and the like.

[0031] The transmission data is transmitted to the coder 21 and the DA converter 22.
, the transmission low-pass filter 23, and the hybrid circuit 11 to transmit the signal to the digital subscriber line, which is the same as the conventional example. The received signal is also applied to a reception low-pass filter 12 via a hybrid circuit 11, high frequency components are removed, and applied to an AD converter 13, where it is converted into a digital signal. Then, the waveform shaping filter 14 shapes the waveform so that the amplitude becomes negative before the main cursor, and the waveform is added to the adder 15 and sent to the echo canceller 20.
A pseudo echo signal from is added to perform echo component removal. Then, the cable characteristics of the digital subscriber line are corrected by the variable amplitude equalizer 16, the timing is adjusted by the variable delay time equalizer 19, and the signal is applied to the decision feedback equalizer 17. This decision feedback equalizer 17 is
As mentioned above, it includes a transversal filter section, a determination section, and an error calculation section, and for example, when the transmission code is a 2B1Q code, level determination of +3, +1, -1, -3 is performed,
In addition, an error signal ej of the difference (yj - aj) between the input signal yj and the decision symbol aj is output. Note that j indicates the time for each baud rate cycle T. Further, the +3, +1, -1, -3 decision symbols aj from the decision feedback equalizer 17 are applied to the decoder 18 and decoded into binary received data.

Further, the correlation between the decision symbol aj and the error signal ej is determined by the correlator 26, and a signal s4 containing data related to at least the main cursor and the first post-cursor is applied to the variable amplitude equalizer 16, and A signal s3 including data related to at least the first precursor is applied to the variable delay time equalizer 19 and the convergence determination section . The error evaluation section 27 obtains an evaluation signal s2 from the sum of absolute values or the sum of squares of the error signal ej, and this evaluation signal s2 is added to the convergence determination section 28. Also, convergence determination section 2
8 is a signal s1 that changes the sampling timing of the AD converter 13 to T/m when it is determined that it has not converged.
This outputs the following. Note that m can be a value of 4 or more, for example, m=8.

As mentioned above, the signal s3 from the correlator 26
, s4, the tap coefficients of the variable amplitude equalizer 16 and the variable delay time equalizer 19 are updated. For example, the tap coefficient related to the main cursor at time j is changed to h0.
,j, the tap coefficient h0,j at time (j+1)
+1 is h0,j+1 =h0,j +α・aj−2・e
j-2...
Calculated using (1). Note that α is a step size of a small positive number.

Similarly, the first precursor and second precursor at time j
The tap coefficients related to the precursor are h-1, j, h-2
, j, then h-1, j+1=h-1, j+α・aj-1・e
j-2
...(2) h-2, j+1=h-2, j+α・aj
・ej-2
...Calculated by (3). Also, the tap coefficient related to the k-th post cursor at time j is h+k,
If j, then h+k, j+1=h+k, j+α・a
j-k-2 ・ej-2
...Calculated by (4). The step size α in each of the above equations does not need to be the same value in each equation, and in each equation, the case is shown in which the error signal ej-2 of 2T ago is used. In equations (2) to (4), it is also possible to use the error signal ej-1 from 1T ago. There is also a method, such as the sine algorithm, in which the amount of change at one time is fixed to the step size α, regardless of the error or symbol value. For example, in the case of the sine algorithm,
Equation (1) is: h0,j+1 =ho,j +α・sign [aj
−2 ・ej−2 ] …(5
).

Among the methods of calculating the tap coefficients related to each cursor based on the correlation between the decision symbol value aj and the error signal ej, at least for the post-cursor, the tap coefficients in the conventional decision feedback type equalizer are calculated. The methods used to do this can be used. Therefore,
The decision feedback equalizer 17 and the correlator 26 can also be collectively referred to as a decision feedback equalizer.

Transfer function Ha of the above-mentioned variable amplitude equalizer 16
Ha=C0 (1-C+1・z-1)

...(6), and the transfer function H of the variable delay time equalizer 19 is
p as Hp=C-2+C-1・z-1+z-2+Cx
・z-3
...(7). Here, it is best to set CX = -C-1 for the variable delay time equalizer 19, but other values are also possible, for example, Cx = 0. Also, the tap coefficient h0,j+1 found by equation (1) is C
0, the tap coefficient h+1, j+1 obtained when k=1 in equation (4) is set as C+1, and the tap coefficient h-1, j+1 found by equation (2) with a negative sign is C-.
1, and further the tap coefficient h-2, which is found by equation (3),
By adding a negative sign to j+1 and setting it as C-2, the variable amplitude equalizer 16 and the variable delay time equalizer 19 can be quickly converged over a relatively wide range regarding the timing phase.

The equalizers 16 and 19 having the transfer functions shown in equations (6) and (7) above, and the decision feedback type equalizer 17 at the subsequent stage, use equations (1) to (4). As mentioned above, good convergence results can be obtained by updating the tap coefficients using Therefore, if the timing is not significantly deviated from the optimal point (for example, by about T/8 or more), if the tap coefficients are repeatedly updated by the calculation process using equations (1) to (4), the solitary wave response (judgment feedback This is because the values at all cursor points (viewed from the input point of the determining section in the type equalizer 17) can be brought closer to ideal values. This ideal value means 1 at the main cursor point and 0 at other cursor points. If it deviates from this ideal value, the second term on the right-hand side of equations (1) to (4) will become positive or negative on average, and therefore the value on the right-hand side will change and eventually the second term on the right-hand side will become positive or negative. As the term settles to zero on average, it approaches the ideal value.

[0038] When calculating the product of the above equations (6) and (7), we get
Ha・Hp=C0・C-2+C0 (C-1-C
+1・C-2)z-1 +C0
(1-C+1・C-1)z-2 +C0 (-C-
1-C+1)z-3 +C
0 ・C+1・C-1・z-4
...(8). If the first term on the right side corresponds to the second pre-cursor, the second term corresponds to the first pre-cursor, the third term corresponds to the main cursor, and the fourth term corresponds to the first post-cursor, the above-mentioned result is obtained. (1) to (4), but the second term includes (C0 ・C+1・C
-2), and the third term includes (C0 ・C+1・C-1) in addition to the main force C0, and the fourth term includes (C0 ・C+1) in addition to the main force C0.・C-1) is included. In each term, when the values other than the main force become large, it becomes difficult to converge. For example, if there is a large deviation from the optimal timing, the amount of delay must be changed significantly, so the values of C-2 and C-1 become large, and values other than the main value become large. As a result, convergence is slow.

Therefore, the convergence status is determined in the convergence determining section 28, and if it is not converged, the sampling timing in the AD converter 13 is shifted by T/8, for example, m=8, and the optimal The pull-in process is performed again closer to the timing. As a result, if it is determined that the timing has not converged again, the process is repeated by further shifting by T/8 to reduce the deviation from the optimal timing. If it is determined that convergence has been achieved, the sampling timing in the AD converter 13 is fixed and training is completed. That is, large timing adjustments can be made by the sampling timing in the AD converter 13, and adjustments to bring the timing closer to the optimum timing can be made by the variable delay time equalizer 19.

The convergence determination section 28 receives the first signal from the correlator 26.
It is determined whether or not convergence has occurred based on the signal s3 containing data related to the precursor and the evaluation signal s2 of the absolute value sum or the sum of squares of the error signal ej from the error evaluation section 27. Since the absolute value of error becomes smaller when it converges, the judgment threshold is set as THp, -THp,T
If He, THp>s3>-THp
…(9
) THe>s2

...Convergence is determined when both equations (10) are satisfied.

[0041] The tap coefficient h-1 according to the above equation (2),
When adding a negative sign to j+1 and using it as C-1, (
8) As can be seen from the formula, -C-1 cannot be accurately called a precursor value [that is, the accurate precursor value is -C0 (C-1-C+1・C-2)] However, when it converges, C-2 becomes almost zero, so -C-1 can be regarded as the precursor value when the main cursor value is 1. That is, -C-1 cannot be regarded as a precursor value at the initial stage of the start of retraction, but can be regarded as a precursor value when the convergence state is approached. Optimal timing can be obtained by adjusting the timing so that this precursor value is zero.

Furthermore, in the network termination device (NT), since timing adjustment can be performed by changing the frequency of the external clock generation circuit, the above-mentioned convergence determination section 28
Without using
Assuming that the value extracted only once is h-1, the switch 25 is turned on according to the cycle, the difference from the constant ka is compared with the positive threshold THa by the comparator 24, and the clock phase φ is determined by the clock control data ct. is adjusted by Δ (minimal positive value) as shown below. When h-1-ka>THa
φ→φ+ΔTHa>h-1-ka>-THa
When , no change -THa>h-1-ka
When φ→φ−Δ In this way, the clock frequency can be controlled and the timing can be adjusted by the variable delay time equalizer 19. What should be noted here is that controlling the clock phase φ using the first precursor value under the conditions described above has been implemented in the prior art, but in the present invention, the clock phase φ is controlled using the first precursor value under the above conditions. The first precursor value is not necessarily required to be zero, and the evaluation value uses a value that cannot be said to be a strict first precursor value.

Furthermore, when k=1 in the above equation (4), (
Although it has been explained that the equation (6) is used to find the value of C+1, this equation (4) is also used to find the first tap coefficient of the decision feedback equalizer 17. Also, C in formula (6)
Since both +1 and the first tap coefficient of the decision feedback equalizer 17 are used to make the first post cursor zero, C+1 in equation (6) is used to make the first post cursor zero. When converging to
The tap coefficient is always zero, indicating that this first tap coefficient can be omitted. Note that the first
It is not possible to set C+1=0 in equation (6) by leaving the tap as it is. This is because the absolute value of the tap coefficient of the decision feedback equalizer 17 is set to 0.5 in order to ensure stability.
Although it is not desirable to exceed C+1=0,
This is because the value may exceed 0.5 depending on the cable distance. Therefore, it is also possible to set C+1 to, for example, 0.0, 0.5, or 0.75 depending on the cable distance, and also use the first tap of the decision feedback equalizer 17.

FIG. 3 is a block diagram of a second embodiment of the present invention, in which the same symbols as in FIG. 2 indicate the same parts, 31 is a transmission characteristic variable equalizer (APEQL1), and s5 is a first precursor. A signal s6 containing related data is a signal containing data related to the first precursor, main cursor, and first post-cursor. The variable transmission characteristic equalizer 31 in this embodiment is a combination of the variable amplitude equalizer 16 and the variable delay time equalizer 19 in the configuration shown in FIG. , Hap1=C0 [C-2+C-1・z-1+z-
2+C+1・z-3+C+2・z-4]


...(11), the tap coefficient h0,j+1 found by equation (1) is used as C0, and (2
) The tap coefficients h-1, j+1 given by formula (3) with a negative sign are C-1, and the tap coefficients h-2, j+1 found by formula (3) with a negative sign are given C-1.
2, and use the tap coefficients h+1, j+1 found when k=1 in equation (4) as C+1, and use the tap coefficients h+2, j+1 found when k=2 in equation (4) as C+2. As a result, it is possible to achieve good convergence even for a received signal whose timing phase is considerably deviated from the optimum value. Note that although the variable coefficient in equation (11) is different from the variable coefficient in equations (6) and (7), they are represented by the same symbols.

Like the transmission characteristic variable equalizer 31, the amplitude variable equalizer 16 and the delay time variable equalizer 19 are integrated, and the C
By introducing the +2 coefficient, decision feedback equalizer 1
7 can be set to zero at all times, and not only can the amount of calculation by the variable transmission characteristic equalizer 31 be reduced, but also the amount of calculation by the decision feedback equalizer 17 can be reduced. However, by setting C+2=0 in equation (11), the decision feedback equalizer 1
Leaving a second tap of 7 is not as difficult as it is for C+1. This is because even if the cable distance changes, the coefficient of the second tap of the decision feedback equalizer 17 does not change significantly. Also, depending on the function of the waveform shaping filter 14, C+2=0 is also possible. Conversely, it is also possible to increase the number of terms in equation (11), add terms C+3 and C+4, and delete the coefficients of the third and fourth taps of the decision feedback equalizer 17 instead. Further, the operation of adjusting the sampling timing in the AD converter 13 and outputting the clock control data ct from the comparator 24 is the same as in the first embodiment described above, and a redundant explanation of the operation will be omitted.

FIG. 4 is a block diagram of a third embodiment of the present invention, in which the same reference numerals as in FIGS. 2 and 3 indicate the same parts, and 3
2 is a transmission characteristic variable equalizer (APEQL2), 33 is a high pass filter (HPF), s7 is a signal containing data related to the first precursor value, s8 is the first precursor value,
This signal includes data related to the main cursor value and the first post cursor value. The transfer function Hhp of the high-pass filter 33 connected after the waveform shaping filter 14 is
Hhp=1-z-1
…
(12). Since this high-pass filter 33 performs processing to take the difference between sample values separated by a baud rate period T, it supplements the function of the waveform shaping filter 14 and has the effect of reducing the tailing of the solitary wave response. Since this tailing is a state in which the amplitude decreases extremely slowly, there is almost no difference between the amplitude of one cycle T ago and the amplitude of the current cycle. Therefore, by taking the difference from one cycle T ago, , the tailing of the solitary wave response becomes significantly smaller.

[0047] The above-mentioned skirting is achieved by cutting off the DC current by the hybrid transformer constituting the hybrid circuit 11, so that when the transmission code includes a DC component, the solitary wave response becomes zero for a long time as shown in FIG. This is caused by the fact that the amplitude does not change, and a non-negligible amplitude may remain even after 20T to 40T. Such a tailing phenomenon also occurs in the solitary wave response of the echo component that has passed through the hybrid transformer. Therefore, conventionally, the echo canceller 20 includes, for example, a 32-tap transversal filter and a first-order IIR filter (Inf.
The decision feedback equalizer 17 is typically configured using, for example, a 16-tap transversal filter and a first-order IIR filter. By reducing this skirting, the above-mentioned IIR filter of the echo canceller 20 becomes unnecessary, and there is an advantage that the number of taps of the transversal filter can also be reduced.

Further, in this embodiment, by providing the high-pass filter 33 having the transfer function shown in equation (12), the part before the tail part of the solitary wave response is greatly influenced. For example, in a signal transmitted by a long-distance cable, high-frequency components are attenuated, so this can be compensated for by the high-pass filter 33, but in a signal transmitted by a short-distance cable, the high-frequency components are attenuated to a small extent. , the received signal is subjected to distortion due to overcompensation by the high-pass filter 33. Therefore, after the echo component is removed by the echo canceller 20, it is necessary to cancel the characteristics of the high-pass filter 33.

Therefore, the transmission characteristic variable equalizer 32 in this embodiment, which integrates the amplitude variable equalizer 16 and the delay time variable equalizer 19, transforms the denominator of the transfer function Hap2 into a first-order one with respect to z-1. The influence of the high-pass filter 33 is compensated for by using a function of . Also, the numerator of this transfer function Hap2 is (1
1) Make it the same as the formula. That is, Hap2=[C0 (C-2+C-1・z-1+z
-2+C+1・z-3+C+2・z-4)]/
(1-a・z-1)
…
(13). Coefficients C-2, C-1, C0, C+1
, C+2 are calculated sequentially using equations (1) to (4) as in the case described above. Further, a may be zero in the case of a long-distance cable, and a value close to 1 in the case of a short-distance cable. That is, it is a parameter related to distance. Also C0
can also be said to be a parameter that changes depending on the cable distance. Therefore, at the initial stage, a = 0, and when the pull-in process has progressed to a certain extent, check the value of C0, and if the value is large, that is, in the case of a long distance, leave a = 0, and For example, in the case of middle distance, a=0
．． 50, and if the value is small, that is, in the case of a short distance, then a=0.75, for example. In addition,(
The variable coefficient in equation 13) is different from the variable coefficient in equations (6) and (7), but is represented by the same sign.

Furthermore, by providing the variable transmission characteristic equalizer 32 described above, the tap coefficients corresponding to the first and second post cursors of the decision feedback type equalizer 17 can be set to zero. Furthermore, since a=0 in the case of a long-distance cable, the skirting is short and its amplitude is small, and even in the case of a medium-distance cable, it is considerably small, so that the IIR of the decision feedback equalizer 17 is Although the filter cannot be omitted, its attenuation coefficient can be fixed. For example, an IIR filter has two parameters, an amplitude coefficient and an attenuation coefficient, but even if the attenuation coefficient is fixed to, for example, about 0.92, the error will not become large, which has the advantage of simplifying the configuration. There is.

Regarding the precursor, although the case where there is a first and second precursor is explained, if the function of the waveform shaping filter 14 is devised or if a slight increase in error can be tolerated, the second precursor may be used. Precursors can be ignored in many cases. In that case, as mentioned above, C-2=0
You can leave it as Also, including the first post cursor,
It is of course possible to include any number of post cursors after that. Also, adjustment of the sampling timing of the AD converter 13 and clock control data c from the comparator 24
Since the operation of the clock generation circuit due to t is the same as in the first and second embodiments described above, a redundant explanation of the operation will be omitted.

[0052]

As explained above, the present invention provides digital data transmission in which a transmitting section and a receiving section are connected to a two-line line such as a digital subscriber line via a hybrid circuit 1 that performs two-line and four-line conversion. In the device, the equalization unit 4 is configured with a variable amplitude equalizer 6 and a variable delay time equalizer 7, and its parameters are based on the decision output signal and error signal from the decision feedback equalizer 5. Since the process is performed sequentially, the amount of processing is reduced and the scale of the hardware can be reduced. Further, since it can be used in common with the hardware for determining the tap coefficients of the echo canceller 8 and the decision feedback equalizer 5, there is an advantage that the hardware can be downsized.

Regarding timing adjustment, the present invention uses the variable delay time equalizer 7 to adjust the timing from the optimum timing phase to T/
It is easy to converge even when the distance is about m,
Therefore, by shifting the sampling timing in the AD converter 2 by T/m, it is possible to quickly converge to the optimum timing. In addition, in a conventional example that does not include the variable delay time equalizer 7, for example, ±T/6
According to the present invention, there is an advantage that the convergence time can be significantly shortened, since the convergence cannot be performed unless the phase range is adjusted to about 4.

[0054] Also, an equalization section 4 that integrates a variable amplitude equalizer 6 and a variable delay time equalizer 7 (variable transmission characteristic equalizer 3 in FIG.
By providing 1) and controlling the amplitude and delay time using data related to the pre-cursor, main cursor, and post-cursor, the order of the filter can be kept the same and the amount of processing can be reduced. Furthermore, since it is possible to reduce the number of taps of the decision feedback equalizer 5 by one, there is an advantage that the amount of processing can be reduced and the hardware can be downsized.

[0055] Also, the baud rate period T of the waveform shaping filter 3
By providing a high-pass filter that receives the output series as input, it is possible to reduce the tailing of the solitary wave response and reduce the amount of processing in subsequent stages. That is, it becomes possible to omit the IIR filter required for the echo canceller 8, and the IIR filter of the decision feedback equalizer 5 can be omitted.
The IR filter also has an advantage in that the amount of processing can be reduced because the attenuation coefficient can be fixed.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention.

FIG. 2 is a block diagram of a first embodiment of the invention.

FIG. 3 is a block diagram of a second embodiment of the invention.

FIG. 4 is a block diagram of a third embodiment of the invention.

FIG. 5 is an explanatory diagram of a data transmission system.

FIG. 6 is a block diagram of a conventional example.

FIG. 7 is a block diagram of a conventional example.

FIG. 8 is an explanatory diagram of a solitary wave response.

[Explanation of symbols]

1 Hybrid circuit 2 AD converter 3 Waveform shaping filter 4 Equalization section 5 Decision feedback equalizer 6 Variable amplitude equalizer 7 Variable delay time equalizer 8 Echo canceller

Claims (7)

[Claims] 1. A digital data transmission device in which a transmitting section and a receiving section are connected to a two-line line via a hybrid circuit (1), wherein the receiving section includes an AD converter that converts a received signal into a digital signal. (2), a waveform shaping filter (3), an equalizer (4), and a decision feedback equalizer (5) are connected in cascade, and the equalizer (4) is connected to the Consists of a variable amplitude equalizer (6) and a variable delay time equalizer (7) that adaptively update variable coefficients based on the decision output signal and error signal from the decision feedback equalizer (5). A digital data transmission device characterized by: 2. The transfer function of the variable amplitude equalizer (6) is −C0 (1−C+1·z−1) (where z−1=exp(j2πfT), f=frequency,
T = baud rate frequency), and the variable coefficients C0, C+1
2. The digital data transmission apparatus according to claim 1, wherein the digital data transmission apparatus is configured to sequentially calculate and control the tap coefficients by update control of tap coefficients associated with the main cursor and the first post cursor, respectively. 3. The transfer function of the variable delay time equalizer (7) is C-2+C-1.z-1+z-2+Cx.z-3, the coefficient Cx is an arbitrary fixed value, and the variable coefficient C- 2,
Claim 1 characterized in that C-1 is configured to be sequentially calculated and controlled by tap coefficient update control related to the second precursor and the first precursor, respectively.
digital data transmission equipment. 4. The transfer function of the equalizer (4) is C0
(C-2+C-1・z-1+z-2+C+1・z-3
+C+2・z-4), and the variable coefficients C-2, C-1, C0, C+1, C+
Regarding No. 2, the present invention is characterized in that the tap coefficients are sequentially calculated and controlled by tap coefficient update control related to the second pre-cursor, the first pre-cursor, the main cursor, the first post-cursor, and the second post-cursor, respectively. A digital data transmission device according to claim 1. 5. A high-pass filter with a transfer function of (1-z-1) is connected after the waveform shaping filter (3),
The echo component contained in the output signal of the high-pass filter is removed by the echo canceler (8) and the echo component contained in the output signal of the high-pass filter is removed by the equalizer (4).
), and the transfer function of the equalizer (4) is
[C0 (C-2+C-1・z-1+z-2+C+1・
z-3+C+2・z-4)]/(1-a・z-1), and the variable coefficients C-2, C-1, C0, C+1, C+
Regarding No. 2, the present invention is characterized in that the tap coefficients are sequentially calculated and controlled by tap coefficient update control related to the second pre-cursor, the first pre-cursor, the main cursor, the first post-cursor, and the second post-cursor, respectively. A digital data transmission device according to claim 1. 6. Convergence determination is performed by inputting the absolute value sum or square sum of the error signals from the decision feedback equalizer (5) and the value of the coefficient C-1 corresponding to the first precursor. A convergence determination unit is provided, and the sampling timing in the AD converter (2) is shifted by T/m (T = baud rate period, m = integer of 4 or more) until the convergence determination unit determines convergence. 2. The digital data transmission device according to claim 1, wherein the digital data transmission device has the following configuration. 7. The first variable delay time equalizer (7)
2. The digital data transmission device according to claim 1, further comprising a configuration for controlling a clock phase by comparing a difference between a coefficient C-1 corresponding to the precursor and a constant value ka with a determination threshold value.