JPH04248635A - Probe effect eliminating method for parallel processing debugging - Google Patents

Abstract

PURPOSE:To eliminate the probe effect due to conventional debugging like a snapshot or a break point in an application program which performs the parallel processing. CONSTITUTION:The program is not devised at all. A monitor processor 5 is arranged on a high-speed bus 1 because all of information between central processing units 2a to 2n and various processors 3 and 4 flow on the high-speed bus 1, and information on the bus is monitored by a system console 6 and is interpreted, and a required part is taken in and is stored in a large-capacity memory or a disk 7.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for eliminating probe effects that occur when conventional debugging is applied to application programs that perform parallel processing.

0002

2. Description of the Related Art In the field of application programs that perform parallel processing, online and real-time processing is fundamental, and when a failure occurs, it is necessary to quickly identify the cause and take countermeasures. Various methods have been studied for debugging parallel processing, but the most common method is to apply snapshots and breakpoints. These are the orthodox debugging methods used in conventional sequential programs.
) allows you to modify the program by printing out the progress of the process on the console or writing it to a file.
A breakpoint is a function that temporarily interrupts processing when a program executes a specified address (ie, a breakpoint), and continues execution after checking the progress of the processing during the interruption.

0003

[Problems to be Solved by the Invention] However, since the above-mentioned snapshots, breakpoints, etc. are originally debugging methods for sequential programs, they cause particular problems when debugging parallel processing. In other words, if you set a snapshot or breakpoint in a program, the processing time of the entire program will be (
The program's original processing time) + (snapshot or breakpoint processing time) takes longer than the original processing time. This extra time, or the timing shift caused by the extra time in programs that perform parallel processing, is known as the probe effect.
fect). As described above, the orthodox debugging method involves delicate timing in a parallel processing environment, and there are cases in which failures cannot be reproduced. Even if the setting environment such as data at the time of failure is exactly the same,
Placing snapshots or breakpoints in a program creates a probe effect that prevents failures from occurring due to subtle timing discrepancies between tasks in a dynamic environment. In such a situation, you have to start up the system with the trap still in place and wait for the failure to occur again.

The present invention was devised in view of these problems, and while employing the conventional easy debugging method, it does not generate probe effects even in parallel processing and eliminates subtle timing discrepancies between tasks. The object of the present invention is to provide a method for removing the probe effect of parallel processing debugging, which enables the reproduction of system failures that could not be reproduced in the past, and the investigation of their causes.

[0005]

[Means for Solving the Problems] Means for solving the above problems in the present invention is a system that includes a central processing unit, an input/output processor, and a memory processor on a high-speed bus. In the method of removing the probe effect, without adding anything to the program, a monitor processor is placed on the high-speed bus, monitors and interprets the information flowing on the high-speed bus, and captures the necessary parts.
This is based on the probe effect removal method of parallel processing debugging to be recorded.

[0006]

[Operation] The present invention does not do anything to the program,
This eliminates the probe effect while leaving the program configuration and structure unchanged. Generally, in a system configuration of a single CPU unit, a central processing unit, an input/output processor, and a memory processor are connected to a high-speed bus, so that all information transmitted and received among them flows on the high-speed bus. In the present invention, by disposing a monitor processor on this high-speed bus, the information on this bus is monitored, interpreted, and necessary parts are taken in without interfering with the operation of each processor, and this information is stored in memory or Record to disc.

[0007]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of an embodiment of the present invention. In the figure, 1 is a high-speed bus, and a plurality of central processing units 2a to 2n, their corresponding input/output processors 3a to 3n, and a memory processor 4 are connected to the high-speed bus 1, and a system of a single CPU unit is implemented. It consists of In the present invention, a monitor processor 5 is disposed on the high-speed bus 1, and all information transmitted and received between the plurality of central processing units 2a to 2n, input/output processors 3a to 3n, and memory processor 4 is transmitted and received by the system console 6. monitor, interpret,
The necessary portions are captured and this information is recorded on a large capacity memory or disk 7. 8 in the figure is an external probe interface.

FIG. 2 is an explanatory diagram of the information contents flowing on the above-mentioned high-speed bus 1. Normally, information comes in two types: a request or a reply. In the case of a request, it consists of a request destination 21, request content 22, and a request source 23, and in the case of a reply, it consists of a reply destination 24, a reply content 25, and a reply source 26. There is. The format and contents of the request content 22 vary depending on the request destination and the request source, and the same applies to the response. The monitor processor 5 shown in FIG. 1 can take in any information flowing on the high speed bus 1 and can interpret all that information. Conversely, requests or instructions can be made to any processor. It is assumed that the monitor processor 5 includes hardware logic, firmware logic, and software logic that perform the above functions.

FIG. 3 is a block diagram of the monitor processor shown in FIG. 1. In the figure, the monitor processor includes a CPU 33 on an internal bus 32 connected to the high-speed bus 1 via a high-speed bus interface 31,
The program of the PU 33 is stored in the program memory 34. Also connected to the internal bus 32 are an internal high speed memory 35, a system console interface 36, and an external high speed memory interface 37. The high-speed bus interface 31 has a function of loading all the information on the high-speed bus 1 into the internal high-speed memory 35, and at this time, according to instructions from the CPU 33, specific information on the high-speed bus 1, information flowing on the high-speed bus 1, etc. Information for a certain period of time, express bus 1
It is possible to selectively collect information on a section specified by matching a specific pattern flowing above the express bus 1 and information on a section specified by specific semantic information flowing on the express bus 1. The monitor processor 5 can communicate with, give instructions to, and set each processor using operator commands, thereby allowing various debugging operations to be performed.

The main operating procedures for debugging are as follows. In the case of a breakpoint, (1) the operator instructs when to set a breakpoint and the conditions via the system console 6 and system console interface 36 (2) the monitor processor 5 uses this instruction to set the breakpoint (3) Once all breakpoints have been memorized, the information flowing on the high-speed bus is monitored based on the location and conditions. (4) When information matching the location and conditions is found, the monitor processor 5 In order to stop the processors on high-speed bus 1, the bus is held and a stop request is issued to each processor. (6) When the monitor processor 5 issues a command to cancel the breakpoint mode, the former active state is restored.

On the other hand, in the case of a snapshot, (1)
The operator instructs the location and conditions for taking a snapshot via the system console 6 and system console interface 36 (2) The monitor processor 5 stores the location and conditions for the snapshot based on this instruction (3) ) After storing all the snapshots, monitor the information flowing on the express bus according to the location and conditions. (4) When information matching the location and conditions is found, the monitor processor 5 stores the snapshots on the express bus 1. Monitors communication with passive processors accessed by the target active processor and captures necessary information (5) The monitor processor 5 collects register information, etc. inside the processor on the high-speed bus 1. A hardware probe is provided, which is connected inside each processor and similarly captures the necessary information according to the snapshot location and conditions (6) The captured information is edited and sent via the external high-speed memory interface 37. (7) Cancel the snapshot mode based on the location and conditions of the snapshot, and store it in an external memory (not shown) and display it on a display or print it out on a printer at the operator's request. Restore the original active state.

[0012] As described above, in this embodiment, by thoroughly collecting information indirectly, the occurrence of probe effects can be significantly reduced compared to the case where observation points are directly set in the program. In addition, the possibility of reproducing failures is high because the program does not have to be modified directly. Furthermore, since there is generally a dedicated CPU for the system console, there is also the advantage that it can be actively utilized.

[0013]

[Effects of the Invention] As explained above, according to the present invention, while employing the conventional easy debugging method, the probe effect does not occur even in parallel processing, and subtle timing discrepancies between tasks are eliminated. It is possible to provide a method for removing the probe effect of parallel processing debugging, which allows a system failure to be reproduced and the cause to be determined.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention;

FIG. 2 is an explanatory diagram of information content of the present invention;

FIG. 3 is a configuration diagram of a monitor processor of the present invention.

[Explanation of symbols]

1...High-speed bus, 2a-2n...Central processing unit, 3a-3n
...I/O processor, 4...Memory processor, 5...Monitor processor, 6...System console, 7...Large capacity memory or disk, 8...External probe interface, 31...High speed bus interface, 32...Internal bus, 33...CPU , 34...Program memory, 35...Internal high speed memory, 36...System console interface, 37 External high speed memory interface.

Claims (1)

[Claims] Claim 1: A method for removing the probe effect that occurs when debugging parallel processing in a system in which a high-speed bus includes a central processing unit, an input/output processor, and a memory processor, which involves monitoring the high-speed bus without installing anything in the program. A method for removing probe effects in parallel processing debugging, characterized by arranging a processor, monitoring and interpreting information flowing on a high-speed bus, and capturing and recording required parts.