JPH04248199A - Memory fault deciding method and semiconductor integrated circuit device using this method - Google Patents

Abstract

PURPOSE:To decide the fault contents of memory cells by writing the same or inverted data into a memory cell for testing separate from the memory cells at the time of data writing and making decision in accordance with the data of the memory cell for testing. CONSTITUTION:The same data are written into the memory cell for testing of a memory fault decision circuit 203 simultaneously when word data are written into the memory cells of a memory block 201. The data are independently read out. A write operation fail is decided if the result of the reading out data from the memory cell for testing is also a fail simultaneously with the writing of the data to the failed memory cell in the event of the memory cell fault. The read operation fail of the faulty memory cell is decided if the reading out rest of the memory cell for testing is correct. The similar results are obtd. as well even if the inverted data are written into the memory cell for testing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining failure details of a memory cell in a semiconductor integrated circuit device having a memory circuit, and a circuit device thereof.

0002

2. Description of the Related Art In a semiconductor integrated circuit device having a memory circuit, when it is assumed that a particular memory cell in the memory circuit has failed or will fail and the cause thereof is to be investigated, a test pattern is applied from an external pin. You can access the faulty memory cell and its surrounding memory cells to obtain as much information as possible regarding its malfunction, or add a test circuit to the memory circuit in advance to test the faulty cell from various angles. Perform analysis.

FIG. 4 shows an example of a conventional configuration in which a memory cell test circuit is added to a memory circuit of a semiconductor integrated circuit device to analyze internal memory cells for malfunctions and the like. The memory circuit includes a memory cell block 401, a word selection circuit 402, and a memory cell test circuit that tests the WRITE operation and READ operation of each memory cell (for example, a memory cell test circuit that tests data destruction on the way to the memory cell block 401). memory cell row (ROM) 404
, a memory cell column (COLUMN) 405, and word lines word(0) to word(n-1) are provided. As shown in FIG. 4, a memory cell test circuit 403
Since it is constructed using a large number of control signals and address signals, the circuit size generally tends to increase. Also, REA
The circuit becomes complicated to check the D/WRITE operation.

0004

[Problem to be Solved by the Invention] In order to analyze malfunctions of memory cells, it is necessary to use a test circuit provided in the memory circuit as described above, apply a test pattern from the outside, or use a test method. This is done by devising ways to do so. When a test circuit is provided internally, the scale of the circuit tends to increase, and the expected area of the memory cell block is often limited, which limits the items that can be tested. In addition, when applying a test pattern from the outside or devising a test method, there is no suitable method to date, and in these cases, detailed consideration is not required compared to when analyzing by setting up a test circuit. This is difficult and, if done at all, makes testing methods more complex. Furthermore, when a memory cell is malfunctioning, there is no effective means to determine whether the memory cell is failing when writing data or failing when reading data, and even if it could be implemented as a test circuit, The problem was complicated.

[0005]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the memory failure determination method of the present invention provides a method for determining a memory failure in a memory cell of a memory circuit of a semiconductor integrated circuit device. By making it possible to simultaneously write the same or inverted data to the memory cells and making it possible to read the data written to the test memory cell independently of the data read operation of the memory cells, when the memory cells fail. By reading the data written in the test memory cell, it is possible to determine whether the malfunctioning memory cell malfunctions during a write operation or a read operation.

Further, in the semiconductor integrated circuit device of the present invention, in a semiconductor integrated circuit device having a memory circuit, data is simultaneously written to a memory cell of the memory circuit and simultaneously written to a test memory cell other than the memory cell. Alternatively, the test device may have a means for writing inverted data, and a means for reading data written in the test memory cell independently of a data read operation of the memory cell.

[0007]

[Operation] With the above configuration, the same or inverted data can be written to a test memory cell other than the memory cell of the main body at the same time as data is written to the memory cell of the main body. While writing and reading are being performed, each time writing is performed, writing is simultaneously performed in the test memory cell, and the data is updated each time the address changes. Also,
If a memory cell in the main body fails, the means that makes it possible to read the data written in the test memory cell independently of the data read operation of the memory cell in the main body allows access to the faulty memory cell and simultaneously reads the same or The data of the test memory cell to which inverted data has been written is read, thereby making it possible to determine whether the faulty memory cell malfunctions during a write operation or during a read operation. Furthermore, by using the above memory failure determination method, failure determination can be made without changing the original functional configuration of the memory circuit, and a test circuit that can be easily applied to devices and configured with a small circuit scale can be built into the memory circuit. realizable.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flowchart of a memory failure determination method showing an embodiment of the present invention. Memory circuit is WRIT
Assume that a memory cell failure occurs during an E/READ operation. If no failure occurs in step 102, the memory circuit continues normal operation in step 101. Next, when a failure occurs, at the same time as writing to the memory cell in which the failure has occurred, WRITE/REA is executed on the test memory cell to which the same data is written.
D is executed, and it is determined in step 104 whether the result is the same as the read result of the failed memory cell.

At this time, if the read result of the test memory cell is the same fail result as the failed memory cell, that is, if both are fail results, step 1 is performed.
At 05, the faulty memory cell can perform at least a WRITE operation.
FAIL”. In the opposite case, that is, if the read result of the test memory cell is correct, step 1
06, the faulty memory cell performs at least the READ operation “F
AIL" can be determined.

As described above, since the test memory cells are memory cells that access the same word line and the same bit line to which the same data as the faulty memory cell is simultaneously written, there is no method that can determine the cause of this malfunction. Therefore, This determination is based on the assumption that the failure mode may occur, and using this result, more detailed failure analysis becomes possible.

In step 103 of FIG. 1, if the same data as the selected data of the address where the failure has occurred has been written in the test memory cell immediately before, it goes without saying that the READ operation continues. Furthermore, even when the write data is inverted data, the operation is similar to the above-mentioned operation for the same data.

FIG. 2 shows an example of a configuration in which a memory circuit for a semiconductor integrated circuit device using the above memory failure determination method is provided with a memory failure determination circuit for analyzing malfunctions of internal memory cells. This is what is shown. The memory circuit includes a memory cell block 201, a word selection circuit 202, a memory failure determination circuit 203 for elucidating the cause of a failed memory cell, a memory cell row (ROW) 204, and a memory cell column (COLUMN) 2.
05, word line word(0)~word(n-
1) A test word and a word control circuit 206 for controlling the test word are provided.

As can be seen from a comparison with FIG. 4, the memory failure determination circuit 203 as a test circuit for memory cell failure analysis includes a circuit of the same scale as a normal memory cell row and a word control circuit 206 that controls it. Therefore, it can be seen that it can be realized with a circuit configuration whose circuit scale is significantly reduced compared to the conventional one. Moreover,
This makes it possible to easily determine whether the cause of a memory cell malfunction is during WRITE or READ while constantly monitoring during normal operation and when a failure occurs.

FIG. 3 shows an example of a specific circuit diagram in which a memory failure determination circuit provided in a memory circuit of a semiconductor integrated circuit device using the above-mentioned memory failure determination method is added. In FIG. 3, the memory circuit includes a memory cell block 201, a word selection circuit 202, a memory failure determination circuit 203 for determining the cause of a failed memory cell, and word lines word(0) to word.
(n-1), test word and this test wo
A word control circuit 206 for rd control is provided. In addition, the control signal TESTW/R is applied to the READ/WRIT of the test memory cell independently of the main body memory cell.
This is a signal that controls the E operation, and the control signal READ/C
is a READ operation control signal of the main body memory cell. It can be seen that during normal operation, TESTW/R is "1" (high level), and as long as the main body memory cell repeats the write operation, the data will be updated and written to the test memory cell on the test word line. . Further, when the main body memory cell is in a read operation, READ/C is set to "1", and data in the main body memory cell can be read. At this time, if it is desired to read the data of the test memory cell independently, it is possible by setting TESTW/R to "0" (low level) and READ/C to "0". As shown in FIG. 3, it can be seen that such a small-scale circuit can realize a memory failure determination circuit that can perform failure determination for a desired purpose.

The control logic for the WRITE/READ operation of the main body memory cell and the WRITE/READ operation of the test memory cell is not limited to this embodiment, and the above-mentioned memory failure determination method can be applied even if a different control logic is used. It would be good if we could achieve this. Further, the circuit in FIG. 3 is an example of a specific circuit configuration for realizing the configuration shown in FIG. 2, and it goes without saying that it may be realized using other circuit configurations and transistors having the same function. . The same applies to the case of writing inverted data to the test memory cell as well.

[0016]

As described above, according to the present invention, it is possible to easily realize a test circuit that can easily analyze the cause of malfunction of a memory cell, etc., and to reduce the circuit scale and configure it in a memory circuit. Furthermore, it has become possible to determine whether a faulty memory cell malfunctions during a write operation or during a read operation, which has been difficult in the past. Furthermore, it can be used as a test circuit without affecting the operation of the main body as a memory circuit, and can be realized with a significantly reduced circuit scale, greatly improving analysis ability from the perspective of failure analysis of memory cells in memory circuits. This is something that can be improved.

[Brief explanation of the drawing]

FIG. 1 is a flowchart of memory failure determination showing an embodiment of the memory failure determination method of the present invention.

FIG. 2 shows an example of a structure in which a memory failure determination circuit is added for analyzing malfunctions of internal memory cells in a memory circuit of a semiconductor integrated circuit device using the memory failure determination method of the present invention. FIG.

FIG. 3 is a circuit diagram showing an example of a specific circuit added with a memory failure determination circuit provided in a memory circuit of a semiconductor integrated circuit device using the memory failure determination method of the present invention.

FIG. 4 is a configuration diagram showing an example of a structure in which a memory cell test circuit provided for analyzing malfunctions of internal memory cells is added to a memory circuit of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

201 Memory block 202 Word selection circuit 203 Memory failure determination circuit 204 Memory cell row (ROW) 205
Memory cell column (COLUMN) 206 word control circuit

Claims (3)

[Claims] 1. When data is written to a memory cell of a memory circuit of a semiconductor integrated circuit device, the same or inverted data is simultaneously written to a test memory cell different from the memory cell, and the data read operation of the memory cell is performed simultaneously. independently reads the data written to the test memory cell, and when the memory cell fails, the data written to the test memory cell is read out at the same time as the data is written to the failed memory cell. A method for determining a memory failure, characterized in that it is determined whether the malfunction of the memory cell occurs during a write operation or a read operation. 2. In a semiconductor integrated circuit device having a memory circuit, means for simultaneously writing the same or inverted data into a test memory cell other than the memory cell when writing data into a memory cell of the memory circuit. What is claimed is: 1. A semiconductor integrated circuit device comprising means for reading data written in the test memory cell independently of a data read operation of the memory cell. 3. The semiconductor integrated circuit device according to claim 2, wherein the memory cells are selected in units of row (ROW) addresses.